CMOS ULTRA-WIDEBAND LOW NOISE AMPLIFIER DESIGN A ...

CMOS ULTRA-WIDEBAND LOW NOISE AMPLIFIER DESIGN

A THESIS Submitted to the Graduate School of Electronics, Communications and Computer Engineering,

Egypt-Japan University of Science and Technology (E-JUST) In Partial Fulfillment of the Requirements for the Degree

of Master of Science

in Electronics and Communications Engineering

by Khalil Ismail Khalil Yousef

February 2012

CMOS ULTRA-WIDEBAND LOW NOISE AMPLIFIER DESIGN

Submitted by Khalil Ismail Khalil Yousef For The Degree of Master of Science

in

Electronics and Communications Engineering Supervision Committee

Signature

Prof. Mohammed El-Sayed Ragab, E-JUST Prof. Hongting Jia, Kyushu University

…………. ………….

Dr. Ahmed Allam, E-JUST

………….

Examination Committee

Approved

Prof. Mohammed El-Sayed Ragab Dean of School of Electronics, Communications and Computer Engineering, E-JUST

………….

Prof. Hadia El-Hennawy Professor, Ain Shams University

…………..

Prof. Zen Kawasaki Advisor of School of Electronics, Communications and Computer Engineering, E-JUST

…………..

Prof. Hossam Shalaby Chairperson, Electronics and Communications Engineering Department, E-JUST

…………..

Dr. Massoud El Ghoneimy Associate Professor, Department of Electronics and Communications Engineering, E-JUST

……………

Vice President for Education and Academic Affairs Prof.: Ahmed Abo Ismail

SUMMARY This thesis presents a new method for Ultra Wideband Low Noise Amplifier Design. Two different UWB LNA configurations will be investigated. Excellent specifications of the designed UWB LNA amplifiers were achieved. The first proposed UWB LNA achieves a gain of 16.9 ± 1.6 dB with noise figure (NF) less than 2.1 dB over the range of frequency 3.110.6 GHz. This UWB LNA has a good input and output impedance matching, good isolation and linearity over this band of frequency. This proposed UWB LNA consumes 14.9 mW of power from a 1.8V supply. A second configuration of the UWB LNA has a bandwidth of 2-16 GHz. The second proposed UWB LNA has a gain of 11.5 ± 0.85 dB and a NF less than 2.82 dB. Good input and output impedance matching, good isolation and linearity are achieved over the operating frequency band. The second proposed UWB LNA consumes 18.14 mW of power from a 1.8V supply. The two UWB LNAs are designed, simulated and implemented in TSMC 0.18 µm CMOS technology. Finally, the design of 3D monolithic integrated inductors will be discussed. The proposed 3D integrated inductors have high inductance values with enhanced quality factors (Q). A new method for 3D inductors design is presented. Using this method, a wide range of inductances and quality factor values can be realized. The proposed 3D inductors were designed in TSMC 0.18 µm technology and simulated using Momentum.

i

ACKNOWLEDGMENT First and foremost, I’m thanking ALLAH for providing me with the ability to complete this research work and write the thesis. I’m thankful to my supervisors, Prof. Mohammed El Sayed Ragab and Dr. Ahmed Allam, for their continual advice during this work. A special thanks to Prof. Hongting Jia, for his continuous help and supervision over the preparation of this work. I would like to thank Prof. Ramesh Pokharel and Prof. Keiji Yoshida, graduate school of Information Science and Electrical Engineering, Kyushu University. A great appreciation to my parents for their care, friendship, help, support and encouragement during my life. I would like to thank my brothers, sisters and their children. I especially wish to thank my eldest brother Eng. Mohammed Ismail for his advice and care during all of my studies. I also thank E-JUST housing supervisor, Mr.Walid Kotb for his great efforts. I would like also to thank my colleagues of E-JUST for many useful discussions and their support over the course of this study. Last, I’m thankful to Egyptian Ministry of Higher Education (MoHE) for funding my M.Sc. studies and Egypt-Japan University of Science and Technology (E-JUST) for offering the tools and equipments needed for the research work.

ii

TABLE OF CONTENTS SUMMARY................................................................................................................................ i ACKNOWLEDGMENT .......................................................................................................... ii TABLE OF CONTENTS ........................................................................................................ iii LIST OF TABLES ................................................................................................................... v LIST OF FIGURES ................................................................................................................ vi ABBREVIATIONS ............................................................................................................... viii

1.

INTRODUCTION ........................................................................ 1

1.1

Why Analog? ............................................................................................................... 1

1.2

Why CMOS? ................................................................................................................ 3

1.3

Why Ultra wideband (UWB)? ..................................................................................... 4

1.4

Why Low Noise Amplifier? ......................................................................................... 4

1.5

Why 3D integrated inductor? ....................................................................................... 5

1.6

Thesis Organization ..................................................................................................... 6

2.

TWO PORT NETWORK ............................................................ 7

2.1

Two Port Network Representations ............................................................................. 7

2.2

The Scattering Matrix .................................................................................................. 8

2.3

RF Basic Definitions .................................................................................................... 9

2.3.1

Gain of Two Port Networks............................................................................................................ 10

2.3.2

Noise of Two Port Networks ......................................................................................................... 12

2.3.3

Stability of Two Port Networks .................................................................................................... 16

3.

RECENT IMPLEMENTATIONS OF UWB LNA ................. 19

3.1

Cascaded Amplifiers .................................................................................................. 19

3.1.1

Circuit Description............................................................................................................................. 19

3.1.2

Circuit Analysis and Discussion ................................................................................................... 20

3.2

Shunt Resistive Feedback Amplifier.......................................................................... 21

3.2.1


3.2.2


3.3

Shunt Resistive Feedback Amplifier Using Active inductor. .................................... 25

3.3.1


3.3.2


4.

CMOS UWB LNAs DESIGN .................................................... 29

4.1

A 3.1-10.6 GHz UWB LNA ...................................................................................... 29

4.1.1

A 3.1-10.6 GHz UWB LNA Circuit Description........................................................................ 30

4.1.2

A 3.1-10.6 UWB LNA Simulation Results and Discussion ................................................. 31

4.1.2.1

Input Impedance Matching ....................................................................................................... 31

4.1.2.2

Power Gain ....................................................................................................................................... 31

iii

4.2

4.1.2.3

Noise Figure (NF) .......................................................................................................................... 33

4.1.2.4

Output Impedance Matching .................................................................................................... 33

4.1.2.5

Reverse Isolation ........................................................................................................................... 34

4.1.2.6

Linearity, DC Power consumption and stability ............................................................... 34

A 2-16 UWB LNA Design......................................................................................... 36

4.2.1

A 2-16 GHz UWB LNA Circuit Description ............................................................................... 37

4.2.2

A 2-16 GHz UWB LNA Simulation Results and Discussion ............................................... 38

4.3

5.

4.2.2.1

Input Impedance Matching ....................................................................................................... 39

4.2.2.2

Power Gain ....................................................................................................................................... 42

4.2.2.3

Noise Figure (NF) .......................................................................................................................... 43

4.2.2.4

Output Impedance Matching .................................................................................................... 46

4.2.2.5

Reverse Isolation ........................................................................................................................... 47

4.2.2.6

Linearity, DC Power Consumption and Stability .............................................................. 48

4.2.2.7

Layout ................................................................................................................................................ 49

Comparison ................................................................................................................ 53

DESIGN OF 3D INTEGRATED INDUCTORS FOR RFICs ................................................................................................... 54

5.1

RF Planar Integrated Inductor .................................................................................... 54

5.1.1

RF Planar Integrated Inductor Design....................................................................................... 54

5.1.2

Challenges of RF Planar Integrated Inductor Design .......................................................... 57

5.1.3

RF Planar Integrated Inductor Design Enhancement. ........................................................ 57

5.2

3D integrated Inductor Design ................................................................................... 58

5.2.1

3D Integrated Inductor Design Methodology ......................................................................... 58

5.2.2

3D RF Integrated Inductor Design .............................................................................................. 60

5.2.3

Proposed 3D Integrated Inductors and Results .................................................................... 62

6.

Conclusion and Future Work.................................................... 69

6.1

Conclusion ................................................................................................................. 69

6.2

Future Work ............................................................................................................... 69

REFERENCES ................................................................................................. 71 ARABIC SUMMARY ...................................................................................... 73 ARABIC COVER PAGE ................................................................................. 75

iv

LIST OF TABLES TABLE I. Proposed UWB LNAs performance summery and comparisson to recently published UWB LNA. ........................................................................................... 53

v

LIST OF FIGURES Figure (1.1) Analog to digital conversion and processing through a DSP core ....................... 2 Figure (1.2) Basic RF receiver building blocks ....................................................................... 5 Figure (2.1) Two port network representation ......................................................................... 7 Figure (2.2) Two port network representation using the scattering matrix .............................. 8 Figure (2.3) Two port network with its load and source terminations ................................... 11 Figure (2.4) Noise sources representation in two port network ............................................. 13 Figure (2.5) Noisy two port network representation .............................................................. 14 Figure (2.6) Noiseless two port network representation ........................................................ 14 Figure (2.7) Two port network including cascaded stages ..................................................... 15 Figure (2.8) Output stability circles for a conditional stable circuit (a) |S11|1 .... 18 Figure (3.1) Schematic circuit of a cascaded amplifier [3] .................................................... 20 Figure (3.2) Low noise amplifier uses a local shunt resistive feedback technique [8] .......... 22 Figure (3.3) Low noise amplifier uses global resistive feedback technique [17]................... 23 Figure (3.4) Shunt resistive feedback amplifier using active inductor [18] ........................... 26 Figure (3.5) Active circuit represents an active inductor [18] ............................................... 27 Figure (4.1) Schematic of the proposed UWB LNA .............................................................. 30 Figure (4.2) Simulation results of input return loss................................................................ 32 Figure (4.3) Simulation results of S21 ..................................................................................... 32 Figure (4.4) Noise figure simulation results ........................................................................... 33 Figure (4.5) Simulation results of output return loss.............................................................. 34 Figure (4.6) Simulation results of S12 ..................................................................................... 35 Figure (4.7) Simulation results of Mu factor .......................................................................... 35 Figure (4.8) Schematic of the proposed UWB LNA .............................................................. 38 Figure (4.9) Schematic of the inductive source degeneration technique ............................... 40 Figure (4.10)

Simulation results for input return loss........................................................... 41

Figure (4.11)

Simulation results of S21................................................................................ 42

Figure (4.12)

Equivalent circuit of the first stage of the proposed UWB LNA used for noise factor calculation [2] ....................................................................................... 45

Figure (4.13)

Simulation results for noise figure (NF) ......................................................... 46

Figure (4.14)

Simulation results of output return loss .......................................................... 47

Figure (4.15)

Simulation results of reverse isolation factor ................................................. 48

Figure (4.16)

Simulation results of Mu stability factor ........................................................ 49

Figure (4.17)

Layout of proposed CMOS UWB LNA ......................................................... 50

Figure (4.18)

Post and Pre-Layout simulation results of input return loss ........................... 50 vi

Figure (4.19)

Post and Pre-Layout simulation results of proposed UWB LNA gain ........... 51

Figure (4.20)

Post and Pre-Layout simulation results of noise figure (NF) ......................... 52

Figure (4.21)

Post and Pre-Layout simulation results of output return loss ......................... 52

Figure (5.1) Different integrated inductor realizations (a) Square (b) Octagonal (c) Hexagonal (d) Circular [24] .................................................................................................. 55 Figure (5.2) Layout and geometric parameters of an integrated spiral inductor .................... 56 Figure (5.3) Inductance comparison of standard inductor and its equivalent layout ............. 59 Figure (5.4) Quality factor comparison of the standard inductor and its equivalent layout... 60 Figure (5.5) General structure of 3D integrated inductor ....................................................... 61 Figure (5.6) Inductance and quality factor of a standard planar inductor .............................. 63 Figure (5.7) Inductances comparison of 3D proposed inductors ........................................... 63 Figure (5.8) Comparison of 3D proposed inductors’ quality factors ..................................... 64 Figure (5.9) 3D view of the symmetric proposed 3D integrated inductor ............................. 66 Figure (5.10)

Inductance of the proposed symmetric 3D inductor ....................................... 67

Figure (5.11)

Quality factor of the proposed symmetric 3D inductor .................................. 67

vii

ABBREVIATIONS 3D

Three Dimensional

BW

Bonding Wire

CG

Common Gate

CMOS

Complementary Metal-Oxide-Semiconductor

CS

Common Source

DC

Direct Current

DSP

Digital Signal Processing

FCC

Federal Communications Commission

IC

Integrated Circuit

IIP3

Input Third Order Intercept Point

LNA

Low Noise Amplifier

MOSFET Metal-Oxide-Semiconductor Field Effect Transistor NF

Noise Figure

NoC

Network on-Chip

PA

Power Amplifier

PSD

Power Spectral Density

RF

Radio Frequency

RFIC

Radio Frequency Integrated Circuit

SNR

Signal to Noise Ratio

SoC

System on-Chip

SRF

Self Resonance Frequency

TSMC

Taiwan Semi-Conductor Manufacturing Company

UWB

Ultra Wideband

VCO

Voltage Controlled Oscillator

VNA

Vector Network Analyzer

WAN

Wireless Area Network

viii

1.

INTRODUCTION

Ultra wideband (UWB) communications cover the frequencies from 3.1 GHz to 10.6 GHz. The development of UWB applications depends mainly on the performance of RF transceivers which act as the backbone of UWB systems. Hence, RF transceivers design represents one of the bottlenecks facing these UWB communication systems’ enhancement. The low noise amplifier (LNA) represents one of the most important blocks forming the RF transceiver. This thesis mainly concentrates on the design of CMOS ultra wide band low noise amplifier (CMOS UWB LNA). Design of 3D integrated inductors will also be reviewed. This chapter clarifies the importance of this work.

1.1 Why Analog? In the early 1980s, death of the analog circuits was expected by many experts and scientists. Integrated circuits (IC) technology which provides compact, efficient implementation of the digital signal processing algorithms helped in this prediction. Digital signal processing algorithms became more powerful through the implementation in IC technology. Most of the functions that had been realized in analog circuits are easily performed in digital domain [1]. Today the world is in a deep need of analog systems’ designers. In spite of the fact that digital systems became so advanced through digital signal processing advanced topics and IC technology enhancement, the earlier prediction of analog systems death could not be confirmed [1]. Although most of the fundamental functions and processes can be performed in digital domain, analog circuits represent a necessary part in many of today’s complex, high performance systems. Many applications have a considerable need for analog parts to have a complete functionality. The replacement of the analog parts with digital ones seems to be very difficult or impossible. Some of these applications will be mentioned below [1]. Natural signals are mainly analog. These natural occurring signals are represented in analog forms. The change of the natural environment is mainly in analog. All the electronic sensors which measure a lot of quantities are representing their response in analog. For

1

Chapter 1________Chapter 5 Mobile Electrocardiograph

example, most of sensors which can be used to measure natural quantities represent its output in an analog form such as voltages and currents [1]. Most of sensors in modern control systems are operating in analog domain. Mechanical, electrical and optical sensors have outputs represented in analog form. Most of these control systems are implemented by analog circuits. All of the mentioned applications imply the importance of the analog circuits and systems. In addition, Modern digital devices employ some analog parts. High quality microphones pick the sounds from surrounding environment and generate an analog output voltage. Digital video camera photocells produce analog currents which are used to adjust the proper functionality of the camera [1]. Even though all the processing operations will be done in digital domain, amplification in analog domain is needed before the conversion as shown in Figure (1.1). Another point to consider is that noise affects these analog captured signals. To cancel noise and extract the desired pure analog signal, analog circuits are needed. In addition, the design of analog to digital converters requires awareness of analog circuits and analog design challenges. Taking into consideration that the input signal to the analog to digital converters is represented in analog form, many analog processes are needed. These processes include filtering, leveling and adaptation of analog signals [1].

Figure (1.1)

Analog to digital conversion and processing through a DSP core

Digital communication systems cannot function well without integrating with analog parts. In digital systems, long distance transmission of binary represented data is needed. This long distance transmission cannot be achieved without distortion and attenuation. If signals are represented in digital format, the data stream sent through the transmission cables will suffer from strong attenuation and distortion. The attenuation and distortion

2

Introduction

occurring through the transfer process may affect the extraction of the correct data stream sent from the source. But with the aid of analog signals and systems, this digital data can be loaded over a carrier. This carrier is mainly an analog signal having a certain frequency. Analog signals with higher frequencies can travel longer distances. So this long distance data transfer occurs depending on analog systems for signal generation, representation, modulation and transmission. In the receivers, the reverse operations are needed. Filtering, amplification, demodulation and data acquisition are performed [1].

1.2 Why CMOS? In the early 1930s, the idea of metal-oxide-semiconductor field-effect transistors (MOSFETs) was approved. In the early 1960s, after the presentation of the n-type MOS transistors, the MOSFETs idea became well applicable. In the mid of 1960s, the CMOS (complementary MOSFET, the technology which depends on both n-type and p-type MOSFETS) was introduced. Because of the introduction of CMOS, a semiconductor technology revolution was triggered [1]. CMOS devices invaded the digital electronics markets as they only consume power during switching. CMOS devices were desired at this time as they require few devices to implement the most needed functions. The reduction of power dissipation and number of devices represented the most CMOS devices famous advantages over the bipolar and GaAs transistors. It was discovered later that the CMOS devices dimensions can be scaled down. This scaling down reduces the area and the cost of systems implemented in CMOS. In addition, scaling CMOS dimensions down was easier than the scaling of other devices. CMOS technology showed clearly that it helps in saving the cost of fabrication [1]. Several years ago, CMOS technology was used to build analog systems. The integrity between the analog and digital circuits represented by CMOS gave an advantage to this technology. Using CMOS technology, analog and digital circuits could be designed and fabricated on the same chip. This possibility proved that CMOS technology would help in saving a lot of the packaging costs [1]. The down scaling of CMOS technology helps in achieving a high speed of the analog and digital systems. During the last 30 years, the speed of MOSFET devices has been doubled [1]. It was known that bipolar devices were the fastest devices used in analog

3


circuits design. After CMOS speed increase, it became comparable to bipolar devices. Taking into consideration the previous mentioned advantages, CMOS became the most preferable technology for hybrid systems (systems including digital and analog parts) [1]. Nowadays, due to CMOS technology cost effectiveness and compatibility with silicon-based system on-chip (SoC) and network on-chip (NoC) technologies, it can be considered the most prevailing technology for radio frequency integrated circuits (RFICs) implementation [2]. The integration between analog and digital systems, the fast performance which is mainly needed in digital systems, area consumption reduction and cost fabrication savings are the most beneficial properties of CMOS devices.

1.3 Why Ultra wideband (UWB)? The demand for high speed and high data rate wireless communications is increasing. The operation frequency of IEEE 802.11b and 802.11g standards is 2.4 GHz. The data rate of these standards is 11 and 54 Mbps respectively. The data rate limitation of these standards is due to their narrow bands of frequency. Other official standards for wireless communications with wider bands were needed [3]. In February 2002, UWB (IEEE 802.15.3a) frequency range was approved by the Federal Communication Commission (FCC) for commercial use [4]. Ultra wide band (UWB) frequency range extends from 3.1 GHz to 10.6 GHz. UWB is a new wireless technology. It produces the ability of data transmission over a wide spectrum of frequency bands. It also capable of transmitting data in high data rates with very low power. UWB technology has a lot of applications. It may be used for imaging systems. Vehicular and penetrating radars are employing UWB technology. Wireless area networks (WANs), High speed mobile area networks, personnel and asset tracking and automotive (anti-collision) radar are different applications of UWB. Through the use of UWB bandwidth (3.1 GHz to 10.6 GHz), data transmission speed achieves up to 400-500 Mbps. UWB is predicted to replace all the cables communications systems in homes or in offices [5-7].

1.4 Why Low Noise Amplifier? Low noise amplifier (LNA) design represents one of the biggest challenges facing the RF transceivers designers. LNA can be considered one of the most important blocks in the front-end RF receiver. It is the first stage of the RF receiver coming after the receiving

4

Introduction

antenna as shown in Figure (1.2). Low noise amplifier mainly defines the noise figure of the overall receiver. Reception and amplification of the received signal over the ultra wide band represent the main functions of the ultra wide band low noise amplifier [3-6].

Figure (1.2)

Basic RF receiver building blocks

A lot of specifications of the low noise amplifier are needed to be met. Broad band input impedance matching is needed to minimize the return loss and to present a certain impedance, such as 50 Ω, to the signal source. Wide band output impedance matching is desired to maximize the power transferred to the load. LNA should provide enough gain to overcome the noise of the following stages such as mixers. High and flat gain is also strongly desired. LNA should accommodate large signals without distortion [3-8]. The LNA is required to have low noise figure (NF) to increase the overall receiver sensitivity. Low power consumption of the LNA is aimed to maximize the battery life time of portable devices. To reduce the fabrication cost of the RF receiver, LNA with smaller area is preferred [4-8]. All of these properties need to be met in a single design which converts the low noise amplifier design into a very challenging job. Through this thesis, different proposed LNA designs will be discussed.

1.5 Why 3D integrated inductor? Nowadays, because of the rapidly growing demands in wireless communication products and devices, high performance and low cost on-chip radio-frequency (RF) devices are needed [9]. Low cost, low supply voltage, low power consumption, low noise, high and flat gain are needed to be achieved through the implementation of wireless communication devices. Most of these demands cannot be achieved without the employment of RF inductors [10].

5


RF inductors can be considered a key component among radio frequency integrated circuits’ (RFICs) devices. They have a wide use in the implementation of filters, voltage controlled oscillators (VCOs), power amplifiers (PAs), low noise amplifiers (LNAs) and different impedance matching networks [11]. Due to this great need of inductors in implementing the radio frequency communication systems, the interest in monolithic spiral inductors is increasing rapidly [12]. Development of monolithic integrated inductors will lead to the superior enhancement in RFICs integrity [11]. In this work, a 3D inductor design method involving multi-layer metals in implementing these inductors will be described.

1.6 Thesis Organization Through this thesis, two different designs of UWB LNA and the design of 3D integrated inductors will be described. This thesis is organized as follow; chapter 2 will investigate the two port network fundamentals. Chapter 3 will present the recent implementations of CMOS UWB LNA. The proposed UWB LNAs design and results will be reviewed in chapter 4. 3D integrated inductors design and results will be shown in chapter 5. Finally, the conclusions and suggested future work will be presented in chapter 6.

6

2.

TWO PORT NETWORK

In analog circuits design, it is very useful to describe circuit blocks as two port networks. This chapter will introduce the two port network representation and properties. First of all a brief description of two port networks will be given. Next, the scattering matrix and its physical meaning will be reviewed. The last section will illustrate some important definitions related to RF circuit design such as gain, noise representation and stability.

2.1 Two Port Network Representations Two port networks are mainly represented as shown in Figure (2.1). The circuit is represented as a black box. This black box (two port network) has four different terminals. Each port has two terminals forming the two ports (port 1 and port 2).. The relation between voltages and currents of the two port network can be expressed by the matrices of Z-parameters and Y-parameters. Equations (2.1) and (2.2) state this relationship. Zparameters and Y-parameters are known as the impedance and admittance matrices.

Figure (2.1)

Two port network representation

𝑉1 𝑍 = 11 𝑉2 𝑍21 𝐼1 𝑌 = 11 𝐼2 𝑌21

𝑍12 𝑍22 𝑌12 𝑌22

𝐼1 𝐼2

(2.1)

𝑉1 𝑉2

(2.2)

Although these relations can describe the two port network, Z and Y matrices are not widely used for RF circuits’ representation. As illustrated by equations (2.1) and (2.2), for

7

Chapter 2_________Chapter 5 Mobile Electrocardiograph

the measurement of the parameters, shorting and opening of the ports are necessary. There is no doubt that ports shorting and opening methods can affect the RF circuit performance. For this reason, better representation and explanation of the RF circuits can be achieved through their scattering matrix (S-parameters) representations [13].

2.2 The Scattering Matrix Due to the difficulty of using Z and Y matrices in representing the two port network operating in high frequency, the scattering matrix depending on the ideas of incident, reflected and transmitted signals can be employed. The two port network explained depending on the definitions of S-parameters is shown in Figure (2.2). The relations between the incident and reflected signals are given by equation (2.3).

Figure (2.2)

Two port network representation using the scattering matrix

𝑏1 S = 11 𝑆21 𝑏2

𝑆12 𝑆22

𝑎1 𝑎2

(2.3)

S11, S12, S21 and S22 are the scattering parameters measured between port 1 and port 2. S11 expresses the ratio of the reflected signal to the incident one in port 1 while port 2 is matched to the load. S22 is equal to the ratio between reflected and incident waves on port 2 while port 1 is matched to the source impedance. S21 measures the portion of the transmitted signal from port 1 to port 2 while port 2 is well terminated. S12 gives the ratio of the transmitted signal from port 2 to port 1 to the incident signal at port 2. S11 and S22 are named input and output self reflection coefficients respectively. S21 is known as forward reflection coefficient and can be considered a type of the two port network gain. S12 is the reverse transmission coefficient. If port 1 and port 2 are matched in

8

Two Port Network

order to the source and load impedances, the squared vales of the magnitude of S21 and S12 are known as the forward transducer power gain and the reverse transducer power gain correspondingly [6] and [13]. The signals a1 and a2 are the incident signals on port 1 and port 2 respectively. The signals b1 and b2 are reflected signals on port 1 and port 2 respectively. Taking into consideration the signal transmission of this two port network, b1 represents the summation of the reflected part of a1 and the transmitted fraction of a2. The signal b2 represents the summation of the reflected part of a2 and the transmitted fraction of a1. As shown, the scattering matrix states the relation between the incident and reflected signals of the same port. It also relates the transmitted signal from a port to the incident signal on the other one. The S-parameters matrix can be calculated easily using the network analysis technique. Scattering matrix calculation is a straight forward operation. On the other hand S-parameters can be measured using the vector network analyzer (VNA) [13]. To summarize, scattering matrix elements can be decided to be the most proper way to explain the function of any RF circuit. Once the S-parameters of the network are given, the design process can start directly without needing any additional information about the internal components of the network. Also measuring the S-parameters of the network gives a complete description of its functionality. Another important property of these different methods of representation is the possibility of conversion from a group of parameters to another one. For example, if the two port network is represented by measuring Sparameters matrix, its equivalent representation employing Z or Y- parameters can be easily estimated [6] and [14].

2.3 RF Basic Definitions Some of the basic definitions related to the RF design will be presented because of their strong relation to the performance of the RF two port networks. These quantities are also related to the two port network representation matrices such as impedance, admittance and scattering matrices. The first quantity to define is gain. Then noise representation and noise figure will be illustrated. Finally, brief description of stability and its conditions will be given.

9


2.3.1 Gain of Two Port Networks One of the most basic and prevalent RF analog circuits rule in the recently implemented RF systems is amplification. The following discussion of the amplification and gain will be based mainly on the S-parameters representation of the two port network. This section will start with basic definition of RF analog circuits gain. There are several different definitions of two port network gain. Analog circuits designers mainly use voltage gain. On the other hand, microwave and RF designers prefer to express gain in its power gain form [14]. Transducer, available and associated power gains are the main three different categories of the power gain of two port network. Transducer gain may be more important than other gain values due to its meaningful gain metric. It gives a general description of the power gain of the circuit. Other formulas can be thought to be special cases of transducer power gain formula [14]. Different power gains definitions will also be illustrated then transducer power gain will be defined. A wider gain definition is the general power gain (G). The power gain is the ratio of the power dissipated in the load (PL) to the power delivered to the input port of the two port network (Pin), (G= PL/Pin). This power gain definition depends on the load termination while there is no dependence on the source impedance [13-15]. The second power gain definition is known as the available power gain. It estimates the ratio of the power available at the output port of the two port network (the output power) to the power available at the input port of the two port network (the input power) which is given by (GAV= PAVL/PAVS). This gain expression takes into consideration the source impedance with no consideration of the load impedance [13-15]. Transducer power gain GT is known as the ratio between the effectively delivered power to the load (PL) and the power available (PAV) from the source. GT is given by equation (2.4).that can be expanded to equation (2.5). This power gain expression obviously depends on the two terminations of the two port network (the source and load impedances) [13-15]. Transducer power gain is less than the general power gain. It is also less than the available power gain [13-15].

10

Two Port Network

Consider an arbitrary two port network represented by its S-parameters connected to a source and load impedances ZS and ZL respectively. The representation of the two port network facing general source and load impedances is shown in Figure (2.3).

Figure (2.3)

Two port network with its load and source terminations

ZS is the source impedance, ZL is the load impedance, Γin is the input reflection coefficient, Γs is the source reflection coefficient, Γout is the output reflection coefficient and ΓL is the load reflection coefficient.

𝑃

𝐺𝑇 = 𝑃 𝐿

(2.4)

𝐴𝑉

𝐺𝑇 =

1− Γ s 2 . 1−Γ s Γ in 2

1− Γ L 2

2

S21 .

1−Γ L Γ out 2

(2.5)

Input and output reflection coefficients can be defined by equations (2.6) and (2.7) respectively while load and source reflection coefficients are given by equations (2.8) and (2.9) provided that the input and output impedance of the two port network is equal to Z0.

𝛤𝑖𝑛 = 𝑆11 + 𝛤𝑜𝑢𝑡 = 𝑆22 + 𝛤𝐿 = 𝛤𝑠 =

𝑆12 𝑆21 𝛤𝐿 1−𝑆22 𝛤𝐿 𝑆12 𝑆21 𝛤𝑠 1−𝑆11 𝛤𝑠

𝑍L −𝑍0 Z L +𝑍0 𝑍s −𝑍0 Z s +𝑍0

11

(2.6) (2.7) (2.8) (2.9)


If the input port is matched to the source (Zs =Z0), the circuit will have a zero source reflection coefficient (Γs =0). A similar state can be considered for the output port, if the load is matched to the output port of the two port network (ZL =Z0), the load reflection coefficient will be zero (ΓL =0). Hence, it can be stated from equation (2.6) that (Γin =S11). In a similar approach equation (2.7) states that (Γout =S22). In this case, the resulting transducer gain can be given by equation (2.10). Equation (2.10) confirms the claim that the transducer power gain is equal to the squared value of the forward reflection coefficient. In case the RF analog circuit is matched to the load, equation (2.10) implies that the forward reflection coefficient value describes accurately the voltage gain of the circuit [13-15].

𝐺𝑇 = S21

2

(2.10)

It can be noted that the matching state (source and load are conjugate matched to the two port network) is the only state where the three different power gains become equal. A special case of the transducer power gain is the unilateral transducer power gain. It is the gain of the unilateral circuits. The circuit is said to be unilateral when it has a transmission or signal propagation in one direction only [13]. In other words, the unilateral two port network has a high forward reflection coefficient and zero reverse reflection coefficient (S12 =0 or its value can be neglected). In this case, equation (2.6) is converted to (Γin =S11). Equation (2.7) can be converted to (Γout =S22). (From equation (2.5) the unilateral transducer gain is given by equation (2.11).

𝐺𝑇𝑈 =

1− Γ s 2 . 1−Γ s S 11 2

2

𝑆21 .

1− Γ L 2 1−Γ L S 22 2

(2.11)

The unilateral transducer power gain turns to the same value of all equivalent power gains in the case of load and source impedance matching. Further description of two port network gain can be found in [13]. 2.3.2 Noise of Two Port Networks Noise mainly decreases the minimum signal level that the circuit can detect with acceptable quality. Noise can be defined to be everything except the desired signal. Noise

12

Two Port Network

is an important factor defining the RF systems and circuits. Noise affects power dissipation, speed and linearity of RF circuits. Noise performance of RF systems is an important metric. Noise statistical properties are well studied in [1] and [6]. Representation of noise sources is given in Figure (2.4) [1]. The normal procedure to quantify the effect of noise on an analog circuit has two different steps. The first step is to set the input signal equal to zero value. The second step is to measure the noise affecting the circuit at the output port. In this case the noise affecting the output terminal is known by the intrinsic noise. This noise is completely generated internally by the internal two port network components. Nowadays RFICs’ designers cannot predict precisely the devices properties. In another way, due to the freedom to choose device dimensions in IC realization, it became difficult to predict accurately devices contribution into noise factor of complete systems [1].

Figure (2.4)

Noise sources representation in two port network

Through this section, noise analysis and representation in two port networks will be reviewed. Methods of conversion from noisy two port network to noiseless two port network will be introduced. The noise factor and noise figure are used to describe the network noise performance. The value of noise factor is equal to the ratio between signal to noise ratio at the input port (SNRin) and the signal to noise ratio at the output port (SNRout) as equation (2.12) illustrates. The noise factor expressed in dB is named noise figure (NF) as given by equation (2.13) [14].

𝐹=

𝑆𝑁𝑅 𝑖𝑛 𝑆𝑁𝑅 𝑜𝑢𝑡

13

=

𝑃𝑛𝑜𝑢𝑡 𝐺𝑃 𝑃𝑛𝑖𝑛

(2.12)


NF= 10 log (F)

(2.13)

Pnout is the output noise power. Pnin is the noise power at the input port and GP is the power gain of the two port network. As stated by equation (2.12), the noise factor is equal to the ratio of the total output noise power to the output noise power due to the input noise power. The noise factor is a measure of the amount of noise added by the two port network itself. An ideal noiseless circuit contributes no noise due to its internal integrants whose noise factor is unity (F=1) and noise figure is equal to zero (NF=0 dB). Noisy and noiseless two port networks are shown in Figures (2.5) and (2.6) respectively, where Vs is a noisy signal source. Zs is source output impedance.

Figure (2.5)

Figure (2.6)

Noisy two port network representation

Noiseless two port network representation

The current and voltage sources represented by their squared values are representing the noise of the noisy two port network. It can be said that these sources are the input referred noise sources. This conversion can be done through two different methods of calculation, input shorting and opening. The noise factor of cascaded stages is an important quantity to consider specially while trying to design a low noise amplifier. For the cascaded RF system shown in Figure (2.7), the system noise factor can be obtained using equation (2.14) [16].

14

Two Port Network

𝐹 = 𝐹1 +

𝐹2 −1 𝐺1

+

𝐹3 −1 𝐺1 𝐺2

+ ……+

𝐹𝑛 −1 𝐺1 𝐺2 ….𝐺𝑛 −1

(2.14)

F is the total noise factor of the system represented by a two port network. Fn, Gn are the noise factor and gain of the nth stage respectively.

Figure (2.7)

Two port network including cascaded stages

Equation (2.14) indicates that the noise factor of the multi stages system depends mainly on the noise factor of the first stage. Equation (2.14) clarifies the importance of low noise amplifiers. Attention should be paid to the low noise amplifier design as it contributes defining the noise performance of the RF transceivers. The LNA can be considered a multi stage system. The first stage of the LNA circuit, known as the input stage, must have an optimized noise performance which leads to noise factor reduction. In addition, the gain of stages forming the two port network system is representing an important factor. The more the gain of proceeding stages, the lower the noise factor of the whole system (two port network). Noise temperature is another figure of merit used to represent noise properties of two port networks. It is another quantity measuring the noise factor [6]. Noise temperature defines the amplifier’s noise contribution as an increase in temperature required for the source resistance to stand for all the output noise [6]. Equation (2.15) governs the relation between the noise factor and noise temperature where TN is noise temperature and Tref (290o K) is the reference temperature.

𝐹 =1+

15

𝑇𝑁 𝑇𝑟𝑒𝑓

(2.15)


A noiseless system represented in two port network form should have a noise factor of 1 and a 0 dB noise figure. Corresponding to this ideality of systems, the ideal system should have a 0o K of TN. Noise Temperature is particularly useful for description of the performance of cascaded amplifiers. Noise Temperature is also used in systems having noise factors quite close to one (whose noise figures are near 0 dB). Even though noise temperature has a better description of noise performance in the previously mentioned cases, noise figure merit expresses a more popular used value for systems noise performance measurement [6]. 2.3.3 Stability of Two Port Networks Two port networks stability (RF systems stability) represents an important issue to discuss due to its effect on systems functionality. Stability problems may cause system functionality inversion or change, such as amplifiers operating as oscillators. Conditions which are necessary for a system to become stable will be given. The stability of any two port networks, especially amplifiers, depends on their input and output reflection coefficients (Γin and Γout.). Because of Γin and Γout dependence on ΓS and ΓL, the stability depends basically on the source and load terminations or their used matching circuits. Instability in RF systems leads to oscillation. Having a negative real part in input or output ports impedance causes the two port network to oscillate. This is indicated mathematically by having the absolute value of Γin or Γout larger than unity. There are two different types of stability:Unconditional stability: the circuit is said to be unconditionally stable if magnitude of the input and output reflection coefficients are less than unity (|Γin | < 1 and | Γout.| < 1) for all passive source and load impedances (|ΓS | < 1 and | ΓL | < 1). Recalling this condition, we can state that the system will be unconditionally stable if the two port network has ( |S11| < 1 and | S22| < 1) [13]. Conditional stability: the circuit is considered conditionally stable if its input and output reflection coefficients exceed the value of one (|Γin | > 1 and | Γout.| > 1) for a certain range of source and load passive impedances [13]

16

Two Port Network

Stability is frequency dependent. Stability depends on source and load impedances which are generally frequency dependent values [13]. Hence, it is possible for a two port network to be stable in its operating range of frequency. But it is possible to be unstable over another range of frequencies. The major condition for two port networks to become unconditionally stable besides having smaller than unity input and output reflection coefficients is having no poles in the right half complex frequency plane representing the scattering matrix elements value. Different tests and formulas can be used for the identification of the unconditional stability conditions. One of the simplest tests to check these unconditional stability conditions is the K-Δ test. It implies that the system will be unconditionally stable if the KΔ conditions illustrated by equations (2.16) and (2.17) are satisfied simultaneously [13].

𝐾=

1−|𝑆11 |2 −|𝑆22 |2 + ∆ 2 2|𝑆12 𝑆21 |

>1

∆ = S11 S22 − S12 S21 < 1

(2.16) (2.17)

The K-Δ mentioned conditions are necessary and sufficient for unconditional stability of any two port network. They can be easily evaluated. If the two port network’s Sparameters and reflection coefficients don’t satisfy the K-Δ conditions of unconditional stability, the devices is not unconditionally stable. Although the K-Δ values can indicate the status of the system being unconditionally stable or not, they cannot be used for a comparison of different systems stability. Due to having two different irrelative parameters, stability degree judgment through the K-Δ test has a considered difficulty. So another stability test value is given by the µ factor test [13]. The µ factor test combines S-parameters in a single test generating only a single parameter, µ. The µ condition is give by equation (2.18) and Δ is given by equation (2.17)

µ=

1−|𝑆11 |2 𝑆22 −∆ 𝑆 ∗ 11 +|𝑆12 𝑆21 |

17

>1

(2.18)


If µ is larger than unity, the two port network is unconditionally stable. The more important information to mention here is the ability of stability comparison with the use of µ factor test. Higher value of µ indicates a better stability of RF systems. A complete derivation of the µ factor relation is given in [13]. In addition, the stability circles can be used to determine the values of ΓS and ΓL for which the two port network become conditionally stable. Stability circles give an illustration of the terminations that maintain the design stable. The output stability circles for |S11|1 are shown in Figure(2.8). The input stability circles can be drawn in the same manner. The center and radius of the input and output stability circles are given by equations (2.19) and (2.20). More discussion and explanations can be found in [13].

Figure (2.8)

Output stability circles for a conditional stable circuit (a) |S11|1 [13] ∗

𝐶𝐿 =

𝑆22 −∆𝑆11 2

𝑆22 − ∆ ∗

𝐶𝑠 =

𝑆11 −∆𝑆22 2

𝑆11 − ∆

∗ 2

𝑎𝑛𝑑 𝑅𝐿 =

∗ 2

𝑎𝑛𝑑 𝑅𝑠 =

𝑆12 𝑆21 2

𝑆22 − ∆ 𝑆12 𝑆21 2

𝑆11 − ∆

2

(2.19)

2

(2.20)

Through this chapter, two port networks representation is discussed briefly. Different parameters implying two port network properties were studied well. Then fundamental technical terms relative to RF systems design were defined.

18

3.

RECENT IMPLEMENTATIONS OF UWB LNA Several ultra-wideband low noise amplifier (UWB LNA) topologies were proposed

over the past few years. Each UWB LNA implementation has several advantages and disadvantages. Depending on the topology and the design methodology of the LNA, these advantages and disadvantages can be defined and discussed. Different specifications and targets are intended to be accomplished through the LNA structure design. The LNA is required to be stable over the operating frequency band. It needs to have a high and flat power gain. It is desired to have a low flattened noise figure (NF). Good match of the input and the output ports to signal source and load respectively is needed. In addition, high linearity and reduction of consumed DC power are desired. In this chapter, different known configurations suggested for the implementation of LNAs will be discussed. Cascaded amplifier, shunt resistive feedback based amplifiers (global and local feedback techniques) and shunt resistive feedback using active inductor will be reviewed.

3.1 Cascaded Amplifiers Cascaded amplifier is formed generally from different cascade connected stages. The common configuration of the cascaded amplifier is a common source stage with source degeneration followed by a common gate stage. Different stages are used for the implementation of the ultra-wideband low noise amplifier (UWB LNA) in which each stage has its own role and functionality in achieving the desired specifications of the design. The amplifier must meet several stringent requirements, such as broad-band matching, sufficient gain, low noise figure (NF), low power consumption and small die area [3]. 3.1.1 Circuit Description As shown in Figure (3.1), this cascaded amplifier consists of three cascade connected stages. The first stage is a common gate (CG) input stage. It is mainly employed for input impedance match to decrease the input return loss. The CG stage also provides noise matching. The second stage is a cascode stage which provides the amplifier with sufficient gain to suppress the noise contributed by the following stages of the RF transceiver [3].

19


The third stage provides output impedance matching to decrease the output return loss. The third cascaded stage is implemented by a source follower (common drain) topology. This common drain topology is biased by an independent current source.

Figure (3.1)

Schematic circuit of a cascaded amplifier [3]

3.1.2 Circuit Analysis and Discussion The input common gate stage is used to achieve a good power and noise match. The degeneration inductor (Ls1) is used to achieve good input impedance match [3]. The second cascode stage provides high frequency gain and determines the 3-dB bandwidth of the UWB LNA. Better isolation is achieved through the cascode transistor (M3). The cascode transistor is chosen smaller to have less parasitic capacitance [3].

20

Recent Implementations of UWB LNA

A series peaking inductor (LD2) resonates with the total parasitic capacitance (CD3) at the drain of the cascode stage (M3) around 10 GHz. For narrow band low noise amplifiers, the inductors quality factor (Q) should be as high as possible to achieve a high gain. However, the quality factor of the series peaking inductor (LD2) is kept low to flatten the gain of the whole LNA. Hence, an extra resistor (RD2) is added is series with the inductor to reduce the quality factor. This quality factor reduction can be accomplished by reducing the inner radius of the inductor (LD2) and increase the number of turns [3]. The simple source follower output buffer helps in achieving good output power match. With the optimization of the output stage bias current and parameters, enhancement of the output match can be obtained. The output port is matched to the amplifier load which is the input impedance of a mixer. The cascaded low noise amplifier configuration has a wide bandwidth. It has a high power gain and can achieve a good input and output impedance matching. The power gain flatness over the operating bandwidth is achieved through the control of the series peaking inductor (LD2) quality factor. Unfortunately, this design suffers from the increase of DC power consumption. It consumes large area which increases fabrication cost. The cascaded UWB LNA given in [3] is implemented in 0.18 µm CMOS technology. This UWB LNA has a measured power gain of 11.2-12.4 dB and a noise figure of 4.4-6.5 dB over the operating bandwidth (0.4 GHz-10 GHz). The input and output impedance matching is less than -10 dB over this band of frequency. The IIP3 is -6 dBm at 6 GHz. The cascaded UWB LNA consumes 12 mW of power from a 1.8 V supply [3]. Complete analysis and verification of the used techniques are given in [3].

3.2 Shunt Resistive Feedback Amplifier The shunt resistive feedback structure can be considered one of the most used topologies to implement an ultra-wideband low noise amplifier due to its superior broadband characteristics [8]. The shunt resistive feedback is mainly used to enhance the stability factor and to reduce the amplifier gain sensitivity [8]. There are two different types of shunt resistive feedback techniques. The first technique is the local shunt resistive feedback. Local feedback is accomplished by having a feedback path between the output and the input of the same stage. The second shunt

21


resistive feedback technique is the global shunt resistive feedback technique, achieved by a feedback path between the output of the second stage or the third stage and the input of the first stage. Figures (3.2) and (3.3) show the schematics of the LNAs with local and global feedback techniques respectively. The next subsection will discuss the circuit description of both designs. 3.2.1 Circuit Description The UWB LNA shown in Figure (3.2) consists of three stages. The first stage is the cascode amplifier with shunt resistive feedback over the common source input stage. This first cascode stage is followed by an inter stage. The inter stage is implemented by a series resonant LC circuit. The final stage is the cascaded common source stage. The last stage uses a series inductive peaking technique.

Figure (3.2)

Low noise amplifier uses a local shunt resistive feedback technique [8]

22


An UWB LNA uses a global shunt resistive feedback technique is shown in Figure (3.3). The first stage is based on the shunt resistive feedback topology. The Lload and Lg are forming an inductive shunt and series peaking respectively [17]. The second stage (M3 and M4, M3 is connected as a source follower while M4 is connected as a common source amplifier) is used for a wide output matching. The connection of the second stage to the input stage in that way aims to noise cancellation which is given in [17].

Figure (3.3)

Low noise amplifier uses global resistive feedback technique [17]

3.2.2 Circuit Analysis and Discussion For the schematic circuit shown in Figure (3.2), a source inductive degeneration technique is used to match the input port to a 50 Ω source impedance. The shunt resistive

23


feedback technique is used to achieve a good input impedance matching over the operating bandwidth. The source degeneration inductor is realized by bonding wires (BW). Input matching is fulfilled using two LC resonant sections. A series resonant circuit consists of L1 and C1 is the first one. The second series resonant circuit is formed by L2 and C2. The resonance frequencies of these resonant circuits are located within the desired band of frequency to have a good input match. The feedback resistor (R1) can be optimized so that good input match, low NF and high broadband gain can be achieved simultaneously. The choice of feedback resistor determines the operating bandwidth. A low value of the feedback resistor increases the operating bandwidth but decreases the gain and degrades the noise performance [8]. The cascode stage employing shunt resistive feedback technique increases the reverse isolation of the amplifier. The middle stage consists of L3 connected to C3 forming a series resonant circuit. This series resonant circuit is beneficial for gain enhancement at high frequencies [8]. The last stage is common source topology with shunt inductive peaking L4. Shunt inductive peaking is used to achieve high and flat gain at higher frequency. Shunt resistive feedback technique implemented by R3 extends the bandwidth and flatten the overall gain of the amplifier [8]. The noise performance of the amplifier given in [8] is defined by the losses of the input network, the feedback resistor and the noise of the first stage (input stage, M1). The input network losses are caused by the reduction of the quality factor of the spiral inductors. Optimization of these inductors was done to achieve higher quality factor with the desired inductance value [8]. Shunt resistive feedback UWB LNAs accomplish good stability performance. The feedback technique contributes well in achieving a high flattened gain. Optimization of the feedback path helps in widening the input impedance matching bandwidth [8]. One of the most known disadvantages of the shunt resistive feedback technique is the noise insertion. The feedback path inserts additive noise to the input port causing noise

24


performance degradation. Shunt resistive feedback topologies of UWB LNAs suffer from high power consumption. This UWB LNA design described in [8] has a 15 dB flat gain and a NF less than 4.4 dB over the operating band of frequency (3 GHz-10.6 GHz). The input return loss of this design is less than -7 dB. The measured IIP3 is 2.5 dBm at the center frequency. This UWB LNA consumes about 21.5 mW of power from a 1.8V DC power supply. Complete analysis and verification of the used techniques through this design are given in [8].

3.3 Shunt Resistive Feedback Amplifier Using Active inductor. Nowadays, an increased attention is paid for the area reduction of the integrated circuits. The area reduction aims mainly to minimize the fabrication costs. In order to reduce area, bulky passive components such as inductors can be implemented using active components. In this section a shunt resistive feedback low noise amplifier employing an active inductor will be presented. As active inductors can be implemented by few transistors, a large die area can be saved in comparison to the passive on-chip inductors. Active inductors can have a wide and adjustable range of inductances with a large and tunable quality factor values. In addition, the high self resonance frequency (SRF) of the active inductor represent an important advantage while on-chip inductors have parasitic capacitances which cause coupling between the inductor and the substrate forces these inductors to have a low self resonance frequency [18]. 3.3.1 Circuit Description Figure (3.4) shows the schematic circuit of a shunt resistive feedback amplifier employing an active inductor. The schematic of the active inductor is given in Figure (3.5). Looking from the coupling capacitor (Cc) side, the equivalent circuit of the circuit shown in Figure (3.5) has an equivalent inductive impedance as explained in [18]. As shown in Figure (3.4), the active inductor is connected to the drain of transistor M3. A passive onchip spiral inductor is used in the first stage as a degeneration inductor for input matching. Shunt resistive feedback is used to widen the impedance matching bandwidth [18].

25


Figure (3.4)

Shunt resistive feedback amplifier using active inductor [18]

The first cascode amplifier stage employs parallel resistive feedback path (R1) to expand the bandwidth of input impedance matching. The second amplification stage employs parallel resistive feedback technique. This use of shunt resistive feedback technique aims to achieve a broadband impedance matching at the output terminal and to increase the stability of the amplifier.

26


Figure (3.5)

Active circuit represents an active inductor [18]

3.3.2 Circuit Analysis and Discussion The input stage represented by M1 is biased through the feedback path resistance (R1) No ac coupling capacitor is added in this path. The output stage uses parallel resistive feedback implemented by R2 to bias the output stage (M3) through the current reuse technique. The ability of shunt feedback technique to bias the amplification stages decreases the complexity of UWB LNA design process. As usual resistive feedback technique is used for better input and output impedance matching. It is also used for flattening of the overall gain. Shunt resistive feedback increases the design stability. The use of resistive feedback in biasing contributes in integrated circuit area reduction. Unfortunately, the employment of parallel resistive feedback causes noise performance degradation [18]. This shunt resistive UWB LNA using active inductor achieves good input and output impedance matching with high and flattened gain over the frequency band of operation (1

27


GHz-5 GHz). The design also achieves good linearity and unconditional stability. Good re. DC power consumption is increase due to the use of active inductor. This CMOS UWB LNA has a gain of 12.5~13 dB with a NF of 3.5 dB over the range of 1-5 GHz. The input return loss is less than -8 dB. The IIP3 measured at 3 GHz is -1 dBm. This LNA has an area of 0.16 mm2. The LNA given in [18] consumes a power of 14.4 mW from a 1.8V supply. Complete analysis and verification of the used techniques through this design are given in [18]. Through this chapter, the most popular configurations of the low noise amplifier were surveyed. It was noted that different techniques should be involved in the implementation of UW LNAs to achieve a good specifications. Each used technique has several advantages and disadvantages. Optimization of each technique is needed to accomplish a high performance UWB LNA.

28

4.

CMOS UWB LNAs DESIGN

LNA design has a lot of specifications which are desired to be met. These specifications include having a low and flat noise figure. LNA is desired to have high flattened power gain. In addition, LNA should have good input and output impedance matching over the operation band of frequency. It is also desired for LNA to have good reverse isolation with acceptable linearity [18]. For narrow band low noise amplifier design, common gate (CG) and common source (CS) topologies can be employed. These topologies are the most well known configurations for narrow band LNA design. Most of the desired properties of the low noise amplifier can be met through the use of common gate topology as it has a good wideband impedance matching. The CG amplifier can be considered a unidirectional amplifier as it has high reverse isolation. The sensitivity of the RF system can be enhanced through the use of common gate low noise amplifier due to its good linearity. The CG configuration has also a good noise performance. Unfortunately, single stage common gate LNA cannot support high and flattened gain [8] and [19]. This chapter introduces two different proposed designs for low noise amplifier. The first one has an operating range of frequency extends from 3.1 GHz to 10.6 GHz. It is implemented using the current reuse cascaded amplifier based on common source topology. The second proposed design has a wider bandwidth starting from 2 GHz to 16 GHz. This low noise amplifier is proposed through the use of current reuse cascaded amplifier core followed by a common gate output buffering stage. The proposed LNAs specifications are high and flat gain, very low noise figure, low DC power consumption, good input and output impedance matching over each band of frequency, high reverse isolation and good linearity.

4.1 A 3.1-10.6 GHz UWB LNA This low noise amplifier is designed to operate over the UWB range of frequency (3.110.6 GHz). Excellent specifications of this designed UWB LNA amplifier were achieved. This proposed UWB LNA achieves a gain of 16.9 ± 1.6 dB. It has a noise figure (NF) less than 2.1 dB over the range of frequency (3.1-10.6 GHz). It has a good input and output impedance matching, good isolation and linearity over this band of frequency. This

29


proposed UWB LNA consumes 14.9 mW of power from a 1.8V supply. The complete design procedure will be discussed later. The achieved results will be shown besides the design methodology. This proposed UWB LNA is designed and simulated in TSMC 0.18 µm CMOS technology. 4.1.1 A 3.1-10.6 GHz UWB LNA Circuit Description. Figure (4.1) shows the circuit that describes the first proposed UWB LNA which is implemented by the current reuse cascaded amplifier. As shown in Figure (4.1), the circuit receives the RF signal through the input port (Vin).and sends it out through the output port (Vout). Vdd

Ld2 RG2 Rd2 Vout

Lg2 M2 C1 Ld1

Vin

C2

Rfb

Cfb

M1 Lg1 RG1 Ls1 VG1

Figure (4.1)

Schematic of the proposed UWB LNA

30

CMOS UWB LNAs Design

The received signal is passed to the first stage (input stage) through the inductive peaking technique (Lg1). The first stage amplifies the received signal and forwards it to the second amplification stage through the capacitive coupling (C1). Passing by the inductive gate peaking of the second stage (Lg2), the signal reaches the final stage. This stage amplifies the signal using the shunt peaking technique at the output (Ld2 and Rd2). Then the signal is sent out to the load (next stage) through the output port (Vout). 4.1.2 A 3.1-10.6 UWB LNA Simulation Results and Discussion This UWB LNA achieved good specifications through the employment of three different techniques. The first technique is the source inductive degeneration technique. The use of shunt resistive negative feedback technique contributes in acquiring these properties. The third employed design enhancing method is the usage of inductive-resistive shunt peaking at the output of the proposed amplifier. The simulation results of the first proposed LNA design will be shown with a brief description. Input and output matching results will be introduced. Gain and noise figure (NF) will be given. Finally, linearity, stability conditions and DC consumed power of the design will be mentioned. Good analysis of each technique and its effect on the design of radio frequency integrated circuits will be given later. 4.1.2.1 Input Impedance Matching Good input impedance matching was achieved using inductive source degeneration technique. Inductive peaking technique of the input stage helps in defining the matching bandwidth and the matching center frequency. The input return loss simulation results are shown in Figure (4.2) which indicates that S11 < -10 dB over (3.1-10.6 GHz) band of frequency. This indicates the match of the proposed UWB LNA to the radio frequency signal receiving antenna. It is matched to 50 Ω output impedance which is considered the output impedance of the receiving antenna. 4.1.2.2 Power Gain High power gain was achieved through this design. The current reuse cascaded amplifier is known with the ability to have a high gain. In addition, the shunt peaking technique at the output of the amplifier enhances the gain. It helps increasing the gain of the amplifier so that the proposed UWB LNA can achieve a gain of 16.8± 1.5 dB.

31


Figure (4.2)

Simulation results of input return loss

Figure (4.3)

Simulation results of S21

32


Flattening of the gain was achieved with the shunt resistive feedback technique. This high gain simulation results are shown in Figure (4.3). It indicates that the forward transmission coefficient (S21) has a range of 18.3 ~ 15.3 dB over the desired band of frequency. 4.1.2.3 Noise Figure (NF) The proposed UWB LNA noise figure (NF) simulation results are shown in Figure (4.4). It indicates that the noise figure is less than 2.1 dB over the operating band of frequency. The noise figure reduction can be considered a very good achievement as it implies the good performance of the proposed UWB LNA.

Figure (4.4)

Noise figure simulation results

4.1.2.4 Output Impedance Matching The UWB LNA achieves good wide output impedance match. Figure (4.5) shows the simulation results of the output return loss. It illustrates that the output return loss (S22) is less than -11.2 dB over the UWB range of frequency.

33


This good matching was achieved with the help of the shunt peaking technique used. In addition, the optimization of the second cascaded stage contributes in achieving this match state. Figure (4.5) illustrates the good match state of the proposed low noise amplifier to its load which is the next RF stage. The designed UWB LNA is matched to a 50 Ω load which is supposed to be the input impedance of the following stage (mixer).

Figure (4.5)

Simulation results of output return loss

4.1.2.5 Reverse Isolation The proposed UWB LNA can be considered a unidirectional amplifier as its reverse reflection coefficient (S12) is less than -26 dB as shown in Figure (4.6). 4.1.2.6 Linearity, DC Power consumption and stability The input referred third order intercept point (IIP3) is calculated to be -2.5 dBm at mid frequency (7 GHz).

34


Figure (4.6)

Figure (4.7)

Simulation results of S12

Simulation results of Mu factor

35


The proposed amplifier consumes 14.9 mW of power from a 1.8V power source. This reduction of the DC power consumption is achieved through the employment of the current reusing technique. The proposed UWB LNA is unconditionally stable. Figure (4.7) shows the µ stability factor of the amplifier indicating the unconditional stability of the proposed LNA.

4.2

A 2-16 UWB LNA Design

In this section, the design methodology of the second proposed UWB LNA will be presented. A comparison between the pre-layout and post-layout simulation results will be held. The extension of the bandwidth where the low noise amplifier can be used is generally desired. For the proposed LNA, it was desired to have an operating range of frequency wider than that of the bandwidth of the UWB technology. It is known that the wider the amplifier bandwidth, the more the difficulties the designer face. The second proposed UWB LNA has an operating bandwidth starting from 2 GHz to 16 GHz. This extension of bandwidth aims mainly to have a multi-technology low noise amplifier. This wide band low noise amplifier can be employed by Wi-Fi devices (routers, repeaters and others). These Wi-Fi devices depend on the IEEE 802.11 standard. This standard has three different operating frequencies which are 2.4 GHz, 3.6 GHz and 5.0 GHz. In addition, this proposed UWB LNA can be used for the implementation of IEEE 802.15 standard devices such as Bluetooth and ZigBee which have an operating frequency of 2.4 GHz. One of the most important applications in which this proposed UWB LNA can be used is the Wi-Max technology. Wi-Max technology is implemented upon the IEEE 802.16 standard. This standard has a bandwidth starts from 2 GHz and ends at 11 GHz. Nowadays, Wi-Max technology has a lot of applications. In the near future, it is expected that Wi-Max will be able to replace all its similar technologies and standards. The last desired bandwidth to include is the Ku band.. The employed band for applications operating in the Ku band range of frequency starts from 10.7 GHz to 14.5 GHz. This 2-16 GHz UWB LNA is suitable for the implementation of the Ku band

36


applications. Satellite receivers and radars are the most known applications using this Ku band range of frequency. This 2-16 GHz proposed LNA is implemented by two different cascaded stages. The first stage is formed from two cascaded stages. They are configured based on a common source (CS) topology of CMOS amplifiers. These cascaded stages use the current reuse technique. This current reuse cascaded core is followed by a common gate (CG) buffer. This second proposed UWB LNA has a gain of 11.5 ± 0.85 dB and a NF less than 2.82 dB over a bandwidth of 2-16 GHz. Good input and output impedance matching, good isolation and linearity are achieved over the operating frequency band. The second proposed UWB LNA consumes 18.14 mW of power from a 1.8V supply. The current reuse core consumes about 10.6 mW of power. The output buffering stage (CG) consumes about 7.5 mW of power. This proposed UWB LNA is designed, simulated and implemented in TSMC 0.18 µm CMOS technology. 4.2.1 A 2-16 GHz UWB LNA Circuit Description The schematic of the proposed UWB LNA is shown in Figure (4.8) which illustrates that the RF signal is received through the input port (Vin). The RF signal is forward to the first amplifying stage passing through the input impedance matching circuit. This matching circuit depends on the inductive degeneration and inductive peaking techniques. After passing through the gate inductor Lg1 and the degeneration inductor Ls1, the received signal is amplified by the input stage. After amplification, the received signal is passed to the gate of the second stage through the capacitive-inductive coupling formed by capacitor C1 and inductor Lg2. Finally, the amplified signal is sent out to output buffer. Then the signal is forwarded to the load connected to the output port (Vout) through the series load matching circuit with its resistive termination formed by Cout , Lout and Rout respectively.

37


Vdd

Rd3 Cout

Lout Vout

Ld2 VG3

RG2

M3 C3

Rout

Lg2 M2 Ls3

C1 Ld1

Vin

Cfb

C2

Rfb M1

Lg1 RG1 Ls1 VG1

Figure (4.8)

Schematic of the proposed UWB LNA

4.2.2 A 2-16 GHz UWB LNA Simulation Results and Discussion An UWB LNA employing a current reuse cascaded amplifier based on common source stages followed by a common gate stage was presented. The proposed LNA achieves many advantages due to this configuration. The proposed LNA specifications are high and flat gain, very low noise figure, good input and output impedance matching, high reverse isolation and good linearity. Recently, current reuse cascaded amplifier has been presented in literature as a suitable configuration for LNA implementation because of its low DC power consumption, high and flat gain , low NF and high reverse isolation [4]. The current reuse circuit is followed

38


by a CG stage used as a buffer to improve the output impedance matching and flatten the LNA gain. This UWB LNA achieved good specifications using several different techniques. The first technique is the source inductive degeneration technique. The use of weak shunt capacitive-resistive negative feedback technique helps in acquiring these properties. Inductive gain peaking is the third employed performance enhancement technique. The use of a series LC resonant circuit at the output matches the proposed LNA to its load. The resistive termination at the output expands the load -to- the proposed UWB LNA matching bandwidth. 4.2.2.1 Input Impedance Matching To match the input impedance of the LNA to the source output impedance over the desired bandwidth, wideband impedance matching techniques can be used [8]. A traditional impedance matching technique uses a source degeneration inductor topology as shown in Figure (4.9). The input port of the circuit is required to be matched to a desired resistance of value Rs at a certain resonance frequency ωo. The bandwidth of this matching technique depends on the quality factor of the source inductor Ls. The gate inductor Lg helps defining this resonance frequency where the input impedance of the circuit is given by equation (4.1). This method is also called the series resonant input technique for input impedance matching [4].

𝑍𝑖𝑛

1 = 𝑗𝜔𝐿𝑠 + + 𝜔 𝑇 𝐿𝑠 𝑗𝜔𝐶𝑔𝑠 1

𝑍𝑖𝑛 = 𝑗𝜔𝐿𝑠 + 𝑗𝜔 𝐶 + 𝑅𝑠 𝑔𝑠

(4.1)

Zin is the input impedance of the circuit, ωT = gm/ Cgs , ωT is the current-gain cut off frequency, gm and Cgs are the trans-conductance and the gate-source capacitance of the input stage (M1) respectively. Vs is the RF signal source whose output impedance is Rs. At the resonance frequency given by equation (4.2), the imaginary part of the input impedance will be cancelled. The real part controlled by the value of Ls will be equal to the value of the pure real source output impedance (Rs.).

39


𝜔o =

1

(4.2)

𝐿𝑠 𝐶𝑔𝑠

Taking into consideration the inductive gate peaking technique and its effect on the matching circuit, the input impedance (Zins) is given by equation (4.3).

𝑍𝑖𝑛𝑠

1 = 𝑗(𝜔𝐿𝑠 + 𝜔𝐿𝑔 ) + + 𝜔 𝑇 𝐿𝑠 𝑗𝜔𝐶𝑔𝑠 1

𝑍𝑖𝑛𝑠 = 𝑗[𝜔 𝐿𝑠 + 𝐿𝑔 − 𝜔 𝐶 ] + 𝑅𝑠 𝑔𝑠

(4.3)

M1 Rs

Lg

Vs

Zins

Ls

Zin Figure (4.9)

Schematic of the inductive source degeneration technique

The input impedance real part will be equal to the signal source output impedance at the resonance frequency. The resonance frequency in this case is given by equation (4.4).

𝜔o =

1 (𝐿𝑠 +L g )𝐶𝑔𝑠

(4.4)

The selection of the values of the inductances involved in the calculation of equation (4.4) will determine the center frequency of source to input port matching [20].

40


In addition, the resistive shunt feedback configuration will be used as it contributes in achieving superior broadband characteristics. In this proposed UWB LNA design, wideband input impedance matching is achieved by using shunt capacitive-resistive feedback technique. The feedback path contributes by its miller portion in widening the matching bandwidth. The shunt resistive feedback technique defines the quality factor of the resonant circuit. The source degeneration matching technique is a suitable technique for a good controllable adjusted impedance matching. The input series resonant impedance matching performance can be optimized through the optimization of the inductances of Ls1, Lg1 and the resistance of the feedback path RFB.

Figure (4.10) Simulation results for input return loss In other words, the definition of the resonance frequency of this matching technique is dependent on the inductance values of Ls1, Lg1 and the bandwidth of the matching resonant circuit depends on the strength of the parallel resistive feedback technique. The simulation results of the input return loss S11 are shown in Figure (4.10) which illustrates the good input impedance match of the proposed UWB LNA. It has a center matching frequency of

41


7 GHz which represents a point near the middle point of the operating bandwidth of the proposed UWB LNA. As shown in Figure (4.10), the input series resonant matching circuit has an input return loss less than -8.3 dB (S11 < -8.3 dB) over the range of 2-16 GHz. 4.2.2.2 Power Gain To achieve a high gain, gate peaking technique can be used. The gate peaking technique also has a considerable role in gain flattening [21].

To enhance the high

frequency gain of the second stage of the current reuse core, a gain-peaking technique is suggested which helps in achieving a high and flat gain. In addition to the contribution of shunt capacitive-resistive feedback technique in the stabilization of the amplifier, the parallel capacitive-resistive feedback technique participates in gain flatness. The common gate buffer stage also contributes in gain flatness. The UWB LNA achieves a power gain (S21) of 10.65 ~ 12.3 dB over 2 GHz-16 GHz band of frequency as shown in Figure (4.11).This high and flattened gain is achieved through the current reuse cascaded core buffered by the common gate stage.

Figure (4.11) Simulation results of S21

42


The “transit” or “cut-off” frequency, ωT, is a measure of the intrinsic speed of a transistor, and is defined as the frequency where the current gain of the transistor falls to 1 [22]. The current gain cut-off frequency is known as ωT1 = gm1/ Cgs1 and ωT2 = gm2/ Cgs2. It is clear that these values depend on the trans-conductance (gm) and gate-source capacitance (Cgs) of the amplification stages. The control of the unity current-gain cut off frequency contributed in achieving a smoothed gain [22]. 4.2.2.3 Noise Figure (NF) Noise reduction and flatness are desired to be accomplished while introducing a new idea for the implementation of UWB LNA. The reduction of noise figure is achieved with the use of resistive feedback technique. Resistive negative feedback is a technique usually used for desensitization of a circuit. The shunt resistive feedback technique helps also in making the gain and input impedance less sensitive to parasitic components, temperature, and process variations [6]. Resistive feedback technique affects the noise figure of the LNA [17]. It is claimed that there is a common problem associated with the use of the resistive feedback techniques in UWB systems implementation. This claim states that the use of resistive feedback in LNAs injects thermal noise to the input side through the feedback loop. This leads to a considerable degradation of the noise performance and hence degrades the noise figure (NF) [6]. The proposed CMOS UWB LNA overcomes this problem of noise figure degradation by the implementation of a weak resistive feedback. The optimization of the amplification stages formed by (M1, M2 and M3) helps in optimizing the flatness of the noise figure over the operating bandwidth. For UWB applications, it is required to have a low flattened noise figure in consistent to a high and flat gain. Traditional narrow band methods for low noise design are not suitable for wideband design. It is known that the first stage of cascaded matched blocks has the main contribution to the total noise figure [16]. We can conclude that to reduce the noise figure of a cascaded amplifier, a reduction of the first stage noise figure is needed. The value of the noise figure (NF) can be optimized through the optimization of the factors

43


that affect that NF. An equivalent circuit of the first stage which is dominant for noise factor calculation is shown in Figure (4.12) [2]. An approximate analysis of the noise figure (NF=10 log10 F) of this topology is given in [2] in which F is the noise factor of the UWB LNA. The noise factor F can be given by:

𝑅𝑔 + 𝑅𝑙𝑔 + 𝑅𝑠𝑠 + 𝑅𝑙𝑠 𝛿𝛼𝜔2 𝐶𝑔𝑠1 2 𝑅𝑆 𝐹 =1+ + 𝑅𝑆 5𝑔𝑀1 𝑅𝐹𝐵 ( 𝐿𝑔1 + 𝐿𝑠1 𝐶𝑔𝑠1 )2 𝜔𝑜,𝑟𝑓𝑏𝑛 2 + . 𝑆 +𝑠 𝑅𝑆 (𝑔𝑀1 𝑅𝐹𝐵 − 1)2 𝑄𝑟𝑓𝑏𝑛

+

2

𝛾 𝑔𝑀1 𝑅𝐹𝐵 + 𝑅𝑆

. 𝑆 +𝑠 𝐹 =1+

𝜔 𝑜,𝑑𝑛

+ 𝜔𝑜,𝑑𝑛

𝑄𝑑𝑛

𝑅𝑔 +𝑅𝑙𝑔 +𝑅𝑠𝑠 +𝑅𝑙𝑠 𝑅𝑆

+ 𝜔𝑜,𝑟𝑓𝑏𝑛 2

𝐿𝑔1 + 𝐿𝑠1 𝐶𝑔𝑠1

∝ 𝑅𝑆 𝑔𝑀1 𝑅𝐹𝐵 − 1 2

2

2

2

2

2

+ 𝑓𝑔𝑛 + 𝑓𝑟𝑓𝑏𝑛 + 𝑓𝑑𝑛

(4.5) (4.6)

Where

𝜔𝑜,𝑟𝑓𝑏𝑛 = 𝑄𝑟𝑓𝑏𝑛 =

1+𝑔𝑀 1 𝑅𝑠 (𝐿𝑔1 +𝐿𝑠1 )𝐶𝑔𝑠1

1 𝑅𝑠 + 𝜔 𝑇1 𝐿𝑠1

𝜔𝑜,𝑟𝑓𝑏𝑛 =

44

.

1+𝑔𝑀 1 𝑅𝑠 𝐿𝑔1 +𝐿𝑠1 𝐶𝑔𝑠1 1

𝐿𝑔1 +𝐿𝑠1 𝐶𝑔𝑠1

(4.7) (4.8) (4.9)


𝑄𝑟𝑓𝑏𝑛 =

1 (𝑅𝑠 ||𝑅𝐹𝐵 )+ 𝜔 𝑇1 𝐿𝑠1

.

(𝐿𝑔1 +𝐿𝑠1 ) 𝐶𝑔𝑠 1

(4.10)

fgn, fdn and frfbn represent the corresponding noise factor contributions of gate noise, drain noise and feedback resistor noise respectively in the total noise factor of the LNA (F). α, δ and γ are constants equal to 0.85, 4.1 and 2.21 respectively. It is noted that to reduce the noise figure, the designer should implement Ls1 and Lg1 with high quality factors (Q). From equation (4.5), it is clear that the noise factor is inversely proportional to the feedback resistor RFB. In other words, the noise factor is dependent on the strength of the employed shunt resistive feedback technique. Strong resistive feedback increases the noise figure so the reduction of the strength of the resistive feedback decreases the noise figure.

Figure (4.12) Equivalent circuit of the first stage of the proposed UWB LNA used for noise factor calculation [2]

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From equation (4.5), it is clear that the noise factor is also inversely proportional to the trans-conductance of the first input stage (gM1). This indicates that the noise figure is reduced with the increase of the drain current of the first stage of the amplifier. This reduced noise figure shown in Figure (4.13) is mainly accomplished through the control of these two parameters. The noise figure of the designed CMOS UWB LNA which ranges from 2.14 dB ~ 2.82 dB is achieved over the 2-16 GHz range of frequency.

Figure (4.13) Simulation results for noise figure (NF) 4.2.2.4 Output Impedance Matching A series resonant circuit consisting of the capacitor Cout and the inductor Lout connected the output of the common gate buffer is playing the role of the output impedance matching circuit. The output port is matched to 50 Ohms load which is considered the input impedance of the next stage (mixer).

46


The resistive termination formed by the resistor Rout decreases the quality factor of this output resonant circuit. This reduction of the quality factor of the series resonance circuit extends the output impedance matching bandwidth. As shown in Figure (4.14), the output return loss is less than -8 dB (S22 < -8 dB) over the operating bandwidth.

Figure (4.14) Simulation results of output return loss 4.2.2.5 Reverse Isolation In RF receivers, unilateral designs are desired to prevent signal reflection from the output to the input. In the same manner, unilateral UWB LNA is preferable to prevent power reflection from the output side to the input side (save the source of the signal and prevent system destroying). Common gate structure has a good isolation behavior. These good isolation features of the common gate buffer contribute a lot to the isolation of our proposed UWB LNA. The LNA reverse isolation factor over this bandwidth (2-16 GHz) is

47


less than -28.7 dB. The simulation results for the reverse isolation factor (S12) are shown in Figure (4.15).

Figure (4.15) Simulation results of reverse isolation factor 4.2.2.6 Linearity, DC Power Consumption and Stability The input referred third order intercept point (IIP3) is calculated to be -7 dBm at mid frequency (9 GHz). The proposed amplifier consumes 18.14 mW of power from a 1.8V DC power supply. This reduction of the DC power consumption is achieved through the employment of the current reusing technique. 10.6 mW of this power is consumed by the current reuse cascaded structure of the amplifier. The common gate output buffering stage consumes 7.5 mW of power.

48


The proposed UWB LNA is unconditionally stable. Figure (4.16) shows the µ stability factor of the amplifier. It indicates the unconditional stability of the proposed CMOS UWB LNA.

Figure (4.16) Simulation results of Mu stability factor 4.2.2.7 Layout Optimization of the UWB LNA is done while drawing the design layout. The proposed UWB LNA layout is shown in Figure (4.17). The UWB LNA occupies an area of 0.84 mm2. Figure (4.17) indicates that passive RF integrated inductors occupy most of the layout area. A comparison between the pre-layout and post-layout results is held. The post-layout and pre-layout simulation results of the input return loss (S11) are shown in Figure (4.18).

49


Figure (4.17) Layout of proposed CMOS UWB LNA

Figure (4.18) Post and Pre-Layout simulation results of input return loss

50


Power gain (S21) simulation results of the post-layout and pre-layout circuits are shown in Figure (4.19). Small degradation of the gain is expected however the proposed UWB LNA still has high and flat gain.

Figure (4.19) Post and Pre-Layout simulation results of proposed UWB LNA gain Noise figure (NF) simulation results of the post and pre-layout UWB LNA circuits are shown in Figure (4.20). Good noise performance is acheived. The output return loss (S22) simulation results of post and pre-layout LNA circuits are shown in Figure (4.21). The series output matching circuit matches well the load to the proposed design.

51


Figure (4.20) Post and Pre-Layout simulation results of noise figure (NF)

Figure (4.21) Post and Pre-Layout simulation results of output return loss

52


4.3 Comparison Table I shows a summary of the designed UWB LNAs performance in comparison to other recently published UWB LNAs implemented in 0.18 µm CMOS technology. TABLE I.

PROPOSED UWB LNAS PERFORMANCE SUMMERY AND COMPARISSON TO RECENTLY PUBLISHED UWB LNA.

Reference

BW (GHz)

Gain (dB)

NF(dB)

S11 (dB)

S22 (dB)

IIP3 (dBm)

Power Consumption (mW)

3.1~10.6

16.7±1.5

< 2.1