Code-Disjoint Circuits for Parity Codes - Semantic Scholar

Code-Disjoint Circuits for Parity Codes

Hendrik Hartje1)

Egor S. Sogomonyan2)

Michael Gossel1)

1) University of Potsdam, Institute of Computer Sciences Fault Tolerant Computing Group 14415 Potsdam, Germany 2) Institute of Control Sciences Russian Academy of Sciences 11 78 06 Moscow, Russia

Keywords

concerning the design of code-disjoint circuits and of the redesign of given combinational circuits into codedisjoint circuits. Recently a code-disjoint ALU has been investigated in [2, 8]. For random logic, a general method for the redesign of a given combinational circuit into a codedisjoint circuit for parity codes was proposed in [6]. It was assumed in [6] that the original circuit can be described as a truth table. However, circuits are very often given as a net-list of gates and, because of their size, cannot be represented as a truth table. In this paper we show how a combinational circuit with parity encoded outputs, which is given as a netlist of gates, can be transformed into two dierent types of code-disjoint circuits which are called single output and double output code-disjoint circuit. A new method for a joint design of the functional circuit, the output parity and the input parity is proposed. Carefully selected internal nodes of the functional circuit are utilized to reduce the necessary area overhead for the design of input and output parities. The fault coverage of internal faults of the functional circuit is higher than for ordinary parity prediction. In addition to the internal faults, all input errors with an odd number of erroneous bits are detected. For a serial connection of code-disjoint circuits only the outputs of the last circuit have to be checked by an XOR-tree of its outputs. If the circuits with parity encoded outputs are not code-disjoint, the outputs of every circuit have to be checked by a corresponding XOR-tree. Thus, it is no surprise that the average area over-

Code-disjoint circuits, Online Test, Parity code.

Abstract In this paper it is shown how a circuit, given as a netlist of gates, can be transformed into two dierent types of code-disjoint circuits. A new method for a joint design of the functional circuit, the output parity and the input parity is proposed. Carefully selected internal nodes of the functional circuit are utilized to reduce the necessary area overhead for the design of input and output parities.

1 Introduction The design of self-testing and self-checking circuits is of growing interest now. The outputs of the monitored circuit are elements of an error detecting code; for instance, a parity code or a Berger code [4, 5, 9, 10, 12{14, 17]. The encoded outputs of the self-testing or self-checking circuit are monitored by a (self-testing) code-checker. Internal faults of the monitored circuit or the checker can be detected by this method. To also detect faults at the input lines, code-disjoint circuits have to be used [13]. Both the inputs and the outputs of a code-disjoint circuit are encoded [3]. As long as no error occurs input codewords are mapped onto output code-words and noncode inputs are mapped onto non-code outputs by a code-disjoint circuit. Thus, faults of the input lines resulting in non-code input words can be also detected. But until now, very few results are known 1

head for the implementation of a serial connection of code-disjoint circuits is even smaller than for a serial connection of the corresponding non code-disjoint circuits. The paper is structured as follows: In chapter 2 the general structure of code-disjoint circuits for parity codes is described. A new synthesis method for codedisjoint circuits is introduced in chapter 3. The proposed techniques have been applied to some MCNC benchmark circuits. The experimental results are given in chapter 4. Chapter 5 contains some conclusions.

tional outputs is the check bit generator in the general design of a self-checking checker, as proposed in [1]. If a circuit C is a serial connection of some subcircuits C1 ; : : : ; Ck with parity encoded outputs as shown in Fig. 2, the outputs of every subcircuit Cj , j = 1; : : : ; k, have to be checked. Thus, for every subcircuit the output of the XOR-tree of its functional outputs has to be compared with the corresponding parity output by use of an equality checker or a tworail checker. (The dierence to a serial connection of code-disjoint circuits will be discussed later). In [6] for random logic, a general method for the transformation of a combinational circuit C into a code-disjoint circuit Ccd was proposed. To obtain the code-disjoint circuit Ccd from the original circuit C with parity-encoded outputs, a parity bit xm+1 = P (x) = x1 


 xm is added to the m functional inputs x1 ; : : : ; xm of C . The correct inputs are then elements of a parity code. One of the inputs xj ; j 2 f1; : : :; m + 1g is directly connected to an additional circuit output yn+1 , and the binary variable xj of the functions fi (x1 ; : : : ; xj ; : : : ; xm ); i = 1; : : : ; n, is replaced by x1 


 xj?1  xj+1 


 xm+1 . The modi ed circuit Ccd implements for i = 1; : : : ; n

2 Code-disjoint circuits In this paper we consider a combinational circuit C with m inputs x1 ; : : : ; xm and n + 1 parity encoded outputs y1 ; : : : ; yn+1 . The n functional outputs y1 ; : : : ; yn implement the n-tuple of the m-ary Boolean functions yi (x) = fi (x); i = 1; : : : ; n with x = x1 ; : : : ; xm . The parity P (y) of the functional outputs y1 ; : : : ; yn is implemented by the (n + 1)-th output yn+1 of C ,

yn+1 = P (y) =

n M i=1

x1 x2

yi = Fi (x1 ; : : : ; xj?1 ; xj+1 ; : : : ; xm+1 ) = fi (x1 ; : : : ; xj?1 ; (x1 


 xj?1  xj+1 


 xm+1 ); xj+1 ; : : : ; xm ); yn+1 = xj ;

fi (x): y1 y2

:::

C

yn+2 =

:::

P (y)

i=1

yi :

x1

yn

xm

n+1 M

yn+1 = y1 


 yn P (y)

Figure 1: Circuit with parity encoded outputs

xj xm xm+1

y1

Ccd

yn+1 yn+2

yn yn0 +1

Figure 3: General structure of a code-disjoint circuit

The parity P (y) and the functional outputs of C can be jointly or separately implemented [7, 16]. The original circuit C with parity encoded outputs is shown in Fig. 1. To check the functional correctness of the circuit in Fig. 1, the output of the XOR-tree of the functional outputs y1 ; : : : ; yn is compared with the parity output yn+1 . The XOR-tree of the func-

The general structure of the code-disjoint circuit

Ccd is shown in Fig. 3. The functions Fi , i = 1; : : : ; n, depend on the parity bit xm+1 instead of the input xj . For small functions, the truth tables of the functions Fi can easily be obtained from the truth tables of

2

x1 x2 : : : C1 : : : xm P1 (y)

: : : C2 : : :

: : : Ck : : :

P2 (y)

Pk (y)

y1 y2 yn

r1 r2

(self-checking) equality checker Figure 2: Serial connection of circuits with parity encoded outputs the corresponding functions fi and thus, for small circuits the synthesis of code-disjoint circuits is no serious problem. The output yn+1 directly outputs the input xj . The output yn+2 implements the parity of the outputs y1 ; : : : ; yn and yn+1 = xj . The outputs yn+1 and yn+2 are added modulo 2 to form the parity yn0 +1 of the functional outputs. It is proved in [6], that the transformed circuit Ccd is code-disjoint. For j 6= m + 1 all the outputs y1 ; : : : ; yn+1 have to be redesigned. If the circuit is large this may be considered as a disadvantage or even impossible. Let us consider now the case j = m + 1. Since the Boolean functions fi (x1 ; : : : ; xm ), i = 1; : : : ; n, which are implemented by the original circuit C , do not depend on xm+1 , we have for the code-disjoint circuit Ccd yi = Fi (x1 ; : : : ; xm ) = fi (x1 ; : : : ; xm ); i = 1 : : : n; yn+1 = xm+1

yn+2 =

n M i=1

x1 x2

Ccd

yn

xm xm+1

P (x) P (y)

yn+2

P (y) yn0 +1

yn+1

Figure 4: Single output code-disjoint circuit

x1 x2

fi (x1 ; : : : ; xm )  (x1 


 xm )

Ccd

y1 y2

0

= P (y)  P (x) n M

fi (x1 ; : : : ; xm ) i=1 and P (x) = x1 


 xm :

with P (y) =

y1 y2

xm

The functional output bits of the original circuit C and the functional bits of the code-disjoint circuit Ccd are identical. Only the parity bit P (y) of the original circuit C has to be modi ed into P (y)  P (x) and the input parity xm+1 has to be added modulo 2 to P (y)  P (x). The corresponding code-disjoint circuit is shown in Fig. 4. The circuit of Fig. 4 is called a single output codedisjoint circuit. The input parity P (x) and the out-

xm+1

yn

P (y) P (x)

yn0 +2 yn00+2 yn+1

Figure 5: Double output code-disjoint circuit

3

x1 x2

The direct implementation of C , P (y) and the parity of the inputs x1 ; : : : ; xm can be jointly optimized by an available synthesis tool as SIS [15]. As the experiments show, a joint optimization of the functional circuit C and the modulo 2 sum of the output parity P (y) and the input parity P (x) results in a considerable reduction of the area overhead if the number of inputs is suciently small to represent the circuitry during the optimization process by a two level representation (collapsing). If a two level representation cannot be achieved internal nodes with a large linear part should be utilized as proposed later in this chapter. If a single output code-disjoint circuit Ccd is a serial connection of some code-disjoint subcircuits Ccd1 ; : : : ; Ccdk , as shown in Fig. 7, only the outputs k have to be checked by a of the last subcircuit Ccd code checker or an XOR-tree. In the case of a direct implementation of the code-disjoint circuit Ccd , additional XOR-trees of the inputs of the code-disjoint j , j = 1; : : : ; k , have to be implesubcircuits Ccd mented. These additional XOR-trees of the inputs replace the additional XOR-trees of the parity encoded outputs of the not code-disjoint subcircuits C i , i = 1; : : : ; k ?1, with parity encoded outputs in Fig. 2. No additional equality checker as in Fig. 2 is needed. In addition to the faults detected by the not codedisjoint circuit C of Fig. 2, the code-disjoint circuit Ccd of Fig. 7 also detects all odd-bit errors at the 1 ; : : : ; Ck . input lines of its subcircuits Ccd cd Now we discuss the synthesis of a double output code-disjoint circuit. Two additional outputs yn0 +2 and yn00+2 implementing both the functions P (x) and P (y) are added to the functional circuit. The functional circuit C , the output parity P (y) and the input parity P (x) are jointly implemented. An odd number of errors at the input of C will be detected by an erroneous input parity P (x). Since P (x) and C are jointly implemented some internal faults of the functional circuit C which are not detectable by an erroneous output parity P (y) can now be detected by an erroneous input parity P (x). Thus, in comparison to ordinary parity prediction, the fault coverage even for internal faults may increase. A serial connection of double output code-disjoint circuits is represented in Fig. 8. For every serially connected double output code-disjoint circuit Ccdj the output parity P j?1 (y) of the preceding circuit Ccdj?1 is compared with the input parity P j (x) of the circuit Ccdj . The comparison detects

y1 y2

C

xm

yn

P (y)

P (y)

yn+2

yn0 +1

P (x) xm+1

yn+1

Figure 6: Direct implementation of a code-disjoint circuit put parity P (y) are added modulo 2 to form the additional single output yn+2 . If both the output parity P (y) and the input parity P (x) are implemented as the additional outputs yn0 +2 and yn00+2 the corresponding circuit is called a double output code-disjoint circuit. A double output codedisjoint circuit is shown in Fig. 5.

3 Synthesis method for code-disjoint circuits In this chapter we discuss synthesis methods for the design of code-disjoint circuits and their serial connections. Single output and double output codedisjoint circuits are considered. We demonstrate how internal gates of the functional circuit can be utilized to reduce the necessary area overhead for the implementation of the input parity and to improve the fault coverage for internal faults. Fig. 4 shows the proposed single output codedisjoint circuit. As already pointed out only one additional output yn+2 is added to the n functional outputs y1 ; : : : ; yn . The output yn+2 implements P (y)  P (x). For the output yn0 +1 = yn+2  xm+1 we then obtain yn0 +1 = P (y). To optimize the area overhead P (y), P (x) and C are jointly implemented. A direct implementation of the single output codedisjoint circuit of Fig. 4 is represented in Fig. 6. The inputs x1 ; : : : ; xm are XOR-ed and added modulo 2 to the output parity P (y) of C .

0

0

0

4

x11 x12

x21 x22

Ccd1

xk1 xk2

Ccd2

Ccdk

x1m

x2m

xkm

P 1 (y) P 1(x) 1 xm+1

P 2 (y) P 2 (x) 2 xm+1

P k (y) P k (x) k xm+1

r2

r1

Figure 7: Serial connection of single output code-disjoint circuits 1. errors of the input lines of Ccdj with an odd num- is reduced by replacing one of the XOR-gates by an AND-gate. As a further advantage all internal faults ber of erroneous bits, of the functional circuit resulting in an error at line 2. internal faults of the circuit Ccdj?1 which are de- f1 in Fig. 9 are always detected as an erroneous input tectable by an erroneous output parity P j?1 (y), parity. The circuit in Fig. 9 is totally self-checking. 3. internal faults of the circuit Ccdj which are de- Now we consider possibilities for the implementation of single output or double output code-disjoint tectable by an erroneous input parity P j (x). circuits more in detail. As self-checking comparator we propose to use the As already mentioned, for small circuits, i.e., for self-checking comparator with a single periodic out- circuits for which a two-level representation can be put as proposed in [11]. Only two input patterns are achieved by the synthesis tool SIS, a joint implemenneeded to detect all internal single stuck at faults of tation of the parity prediction function P (y) and the this comparator. XOR-tree P (x) results in a signi cant improvement The circuitry of Fig. 8 detects faults with a shorter of the area overhead. delay than the circuitry of Fig. 7. Multiple faults are To reduce the necessary area overhead for larger also detected. The outputs P i (y) and P i?1 (x) can circuits as well, i.e., circuits for which a two-level repbe used for the diagnosis of an erroneous component. resentation cannot be obtained, we now show how to Now we illustrate the joint design of the functional utilize selected output lines of internal gates of the circuit, the input parity and the output parity by the functional circuit and the parity prediction function example of Fig. 9. The circuit of Fig. 9 is a double P (y) to reduce the area overhead for the synthesis of output code-disjoint circuit. the XOR-tree of the inputs. We rely on the fact that The gates 1 through 7 implement the functional every Boolean function h(x1 ; : : : ; xk ) can be uniquely outputs represented as a modulo-2 sum of a linear function lh and a non linear function nlh , y1 = x4 f(x2 _ x3 )x1 _ x1 (x2 _ x3 )g h(x1 ; : : : ; xk ) = lh (x1 ; : : : ; xk )  nlh(x1 ; : : : ; xk ) and with y2 = x1 (x2 _ x3 ) _ x4 x1 : lh (x1 ; : : : ; xk ) = ch0  ch1 x1 


 chkxk : For the implementation of the output parity P (y) = h h y1  y2 only the three additional gates 8, 9 and 10 are The coecients c0 ; : : : ; ck 2 f0; 1g of the linear function can easily be determined by needed. The input parity de ned as P (x) = x1 x2 x3 x4 ch0 = h(0; 0; : : :; 0); is realized by use of the additional XOR-gates 12 and ch1 = h(0; 0; : : :; 0)  h(1; 0; : : : ; 0); 13 and the AND-gate 11. ch2 = h(0; 0; : : :; 0)  h(0; 1; : : : ; 0); Thus, the area overhead necessary for a direct im::: plementation of the input parity x1  x2  x3  x4 chk = h(0; 0; : : :; 0)  h(0; 0; : : : ; 1): 0

0

0

5

x1

Ccd1

Ccd2

0

Ccdk

0

0

xm xm+1

P 1 (y)

P 1 (x)

P 2 (x)

P 2 (y)

P k (y)

P k (x)

r1 r2

(self-checking) comparator Figure 8: Serial connection of double output code-disjoint circuits

x1

1

x2 x3

3

2

6

4

f1

y1

5

7

y2

10

P (y) = y1  y2

x4 8 9

11

x5

12

13

P (x) = x1  x2  x3  x4

Figure 9: Example circuit For the nonlinear function nlh we obtain nlh = h(x1 ; : : : ; xk )  ch0  ch1 x1 


 chk xk : The functions lh and nlh are the linear and the nonlinear part of the Reed-Muller expansion or Shegalkin polynomial of the Boolean function h. We assign to the Boolean function h(x1 ; : : : ; xk ) ? h
h the vector vh , vh = c1 ; : : : ; ck , of the coecients of the corresponding linear function lh . The Boolean

function h(x1 ; : : : ; xk ) linearly depends on xi , if the ith component chi of vh equals 1. The number of variables Nlin(h) which the Boolean function h(x1 ; : : : ; xk ) linearly depends on is equal to the number N1(vh ) of 1s in vh and can be expressed as

Nlin(h) = N1 (vh ) = 6

k X i=1

chi :

For a gate g of the circuit P (y) we denote the 5. Determine the set Ilin of all inputs which are Boolean function implemented at the output of g by linear dependent with respect to the modulo-2 added marked gates Ilin = fxj j vlin;j = 1g. g(x) = g(x1 ; : : : ; xm ). We represent g(x) as 6. For g 2 G0 compute the modulo-2 sum nlG of g(x1 ; : : : ; xm ) = lg (x1 ; : : : ; xm )  nlg (x1 ; : : : ; xm ) the nonlinear functions nlg (x1 ; : : : ; xm ), M with nlG = nlg (x1 ; : : : ; xm ) 0

0

g2G

lg (x1 ; : : : ; xm ) = cg0  cg1 x1 


 cgm xm :

0

and optimize nlG (x). If we have cgi = 1, i 2 f1; : : :; mg, g(x) linearly 7. Form an XOR-tree of g 2 G0 , xj 2 X nIlin and depends on xi . nlG . This XOR-tree computes P (x). Candidates of gates which can be used in the resyn- 8. Determine P (x)  P (y)  xm+1 . thesis process of the code-disjoint circuit are gates Step 8 nishes the algorithm. with output functions which are linearly dependent on at least three input variables. Let G3lin be the set 4 Experimental Results of these gates, 0

0

G3lin = fg j Nlin(g)  3g :

The proposed method has been applied to some MCNC benchmark circuits. The results are shown in Table 1 and Table 2. Table 1 shows the area overhead for the dierent types of code-disjoint circuits. All circuits are optimized with the optimization script script.rugged from the synthesis tool SIS. The area of the functional circuits is given in column 1. Column 2 shows the area and the area overhead in percent for the circuit with the output parity P (y) added. The functional circuit and the output parity are jointly implemented [6, 7, 16]. The next two columns 3 and 4 show the area overhead for the corresponding single output and double output code-disjoint circuits. For the double output codedisjoint circuits the average area overhead is 28 percent. For the single output code-disjoint circuits the corresponding value is only 21 %. The circuits in column 3 and 4 are synthesized by use of the proposed algorithm. Internal nodes of the functional circuit are utilized to optimize the area overhead. To demonstrate the eectiveness of the proposed method the direct implementation of code-disjoint circuits was also investigated. For single output and double output code-disjoint circuits the obtained results are presented in columns 5 and 6 respectively. The optimized average area overhead is 40 % and 34 %. Thus the utilization of the internal nodes results in a reduction of the area overhead of about 20 % or 6 % of the area of the original circuits. In Table 2 the fault coverage for the two types of code-disjoint circuits is reported. In the rst column the fault coverage for the single output code-disjoint circuits is shown. On the average the fault coverage

For all the gates g 2 G3lin the linear function lg consists of at least three XOR-ed input variables. Let g 2 G3lin . By using the available synthesis tool we then determine the necessary area a(nlg ) for the implementation of the corresponding nonlinear function nlg (x) of g(x). The area a(nlg ) has to be compared with the necessary area a((Nlin ?2)XOR) for the implementation of a tree of (Nlin ? 2) XORgates. Now we describe the proposed synthesis algorithm. 1. Determine the set G3lin. 2. For each g 2 G3lin determine the area a(nlg ) necessary for the implementation of nlg . 3. Compare a(nlg ) with a((Nlin ? 2)  XOR). If a(nlg ) < a((Nlin ? 2)  XOR) mark the gate g. Denote the set of marked gates by Gm . 4. Choose a subset G0  Gm of marked gates such that the modulo-2-sum of the outputs of the gates from G0 linearly depends on a maximal number of input variables. This is done in the following steps: 4.1 Choose a gate g 2 Gm that linearly depends on a maximal number of input variables (N1 (vg ) maximal). Put vlin := vg ; G0 := fgg. 4.2 Choose a gate g~ 2 Gm nG0 such that the number of 1s in the modulo-2-sum of vlin and vg~ is maximal (N1 (vlin  vg~ ) maximal). If N1 (vlin  vg~ ) > N1 (vlin ) and if a(nlg~) < a((N1 (vlin  vg~ ) ? N1 (vlin ) ? 2)  XOR) put vlin := vlin  vg~ and G0 := G0 [ fg~g. Continue with 4.2 until N1 (vlin  vg~ )  N1 (vlin ). 7

Name 5xp1 9sym rd53 rd73 rd84 sao2 z4ml Average

1 2 orig. circuit circuit plus P (y) 193 257 296 308 69 85 207 184 159 170 194 224 73 94

% 33.2 4.1 23.2 -11.1 6.9 15.5 28.8 14.4

single outp. 308 298 70 141 163 250 135

3

% 59.6 0.7 1.4 -31.9 2.5 28.9 84.9 20.9

4 double outp. 307 304 78 206 184 262 124

% 59.1 2.7 13.0 -0.5 15.7 35.1 69.9 27.9

5 sing. o. XOR 291 258 91 237 211 308 148

6 doub. o. XOR 50.8 270 -12.8 237 31.9 78 14.5 207 32.7 201 58.8 323 102.7 153 39.8 %

% 39.9 -19.9 13.0 0.0 26.4 66.5 110.0 33.7

Table 1: Area overhead for code-disjoint circuits Name

single output double output double output double output P (x)  P (y) only P (x) only P (y) P (x) and P (y) 5xp1 97.1 14.2 86.8 100 9sym 100 12.0 89.3 100 rd53 93.5 25.6 85.1 100 rd73 91.3 14.3 91.8 100 rd83 98.8 17.8 82.8 92.6 sao2 98.7 20.0 82.4 99.5 z4ml 93.5 48.7 56.0 100 Average 96.1 21.8 82.0 98.9 Table 2: Fault coverage for code-disjoint circuits

P (y) are realized at the two additional outputs of the

is 96.1 %. The remaining three columns show the fault coverage for the double output code-disjoint circuits. The fault coverage is calculated separately for the outputs P (x) and P (y) and for both outputs together. The average fault coverage for both outputs is 98.9 % and for more than half of the circuits 100 % fault coverage is achieved.

double output code-disjoint circuit. Errors of an odd number of inputs and on the average 22% of the internal faults are detected at the output for P (x). About 82% of the internal faults are detected at the output for the output parity P (y). Some faults are detected simultaneously at the outputs for P (x) and P (y). If both outputs are monitored 99% of the internal faults are detected on the average. In many cases the fault coverage is 100%. The necessary area overhead for the implementation of both P (x) and P (y) is 28% of the functional circuit. For a double output code-disjoint circuit the input parity P (x) and the original parity bit xm+1 are a checker for the detection of input errors and for the internal faults of the preceding circuit in a serial connection of code-disjoint circuits. The output for P (x)  P (y) of a single output code-disjoint circuit only propagates errors to the next circuit. In a serial connection of double output codedisjoint circuits the double outputs of the corresponding circuit are monitored by an equality checker. Also

5 Conclusion In this paper two dierent implementations of a codedisjoint combinational circuit are proposed: single output and double output code-disjoint circuits. The modulo 2 sum of the input parity P (x) and the output parity P (y) is realized at the additional output of the single output code-disjoint circuit. At this output errors of an odd number of inputs and internal faults of the functional circuit and the gates implementing the input and output parities are detected. At the average 96% of the internal faults are detected. The necessary area overhead is 21% of the original circuit. Both the input parity P (x) and the output parity 8

multiple faults are detected. In a serial connection of Trans. on Computer Aided Design, pages 878{ single output code-disjoint circuits only one parity 887, June 1993. checker at the outputs of the last circuit is needed. It is demonstrated how internal nodes with larger [10] B.W. Johnson. Design and Analysis of Fault Tolerant Systems. Addison Wesley, Reading, MA, linear parts can be utilized to reduce the necessary 1990. area overhead. The optimal combination of single output and dou- [11] S. Kundu, E.S. Sogomonyan, M. Gossel, and ble output code-disjoint circuits for complex systems S. Tarnick. Self-checking comparator with one is an interesting problem for further investigations. periodic output. IEEE Transactions on Computers, 45(3):379{380, March 1996.

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