Code Transformations for Embedded Multimedia Applications: Impact on Power and Performance Nikos D. Zervas
Kostas Masselos
C. E. Goutis
University of Patras
University of Patras
University of Patras
Dep. of Electrical & Computer Engineering, Rio 26500, Greece Tel.: (+) 30 61 997324 E-mail:
[email protected]
Dep. of Electrical & Computer Engineering, Rio 26500, Greece Tel.: (+) 30 61 997324 E-mail:
[email protected]
Dep. of Electrical & Computer Engineering, Rio 26500, Greece Tel.: (+) 30 61 997324 E-mail:
[email protected]
ABSTRACT
video processing applications are described in [4-10].
A number of code transformations for embedded multimedia applications is presented in this paper and their impact on both system power and performance is evaluated. In terms of power the transformations move the accesses from the large background memories to small buffers that can be kept foreground. This leads to reduction of the memory related power consumption that forms the dominant part of the total power budget of such systems. The transformations also affect the code size and the system’s performance which is usually the overriding issue in embedded systems. The impact of the transformations to the performance is analyzed in detail. The code parameters related to the performance of the system and the way they are affected by the transformations are identified. This allows for the development of a systematic methodology for the application of code transformations that achieve an optimal balance between power and performance.
There are two general approaches for the implementation of multimedia systems. The first is to use custom hardware dedicated processors. This solution leads to smaller area and power consumption however it lacks flexibility since only a specific algorithm can be executed by the system. The second solution is to use a number of instruction set processors. This solution requires increased area and power in comparison to the first solution however it offers increased flexibility and allows implementation of multiple algorithms by the same hardware. Mixed hardware/software architectures can also be used.
Keywords Embedded, Multimedia, Code Transformations, Power, Performance.
1. Introduction Image and video coding rapidly became an integral part of information exchange. The number of computer systems incorporating multimedia capabilities for displaying and manipulating image and video data is continuously increased. The rapid advances in multi-media and wireless technologies made possible the realization of sophisticated portable multimedia applications such as portable video phones, portable multimedia terminals and portable video cameras. Real time image and video processing are required in such applications. Low power consumption is of great importance in such systems to allow for extended battery life. Low power portable multimedia systems are described in [1-2]. Portability is by no means the only reason for low power consumption [3]. Low power consumption is of utmost importance in nonportable applications as well. For this reason there is great need for power optimization strategies especially in the high levels where the most significant savings can be achieved [3]. Power exploration and optimization strategies for image and
In multimedia applications, memory related power consumption forms the major part of the total power budget of a system [7-8]. A systematic methodology for the reduction of memory power consumption has been proposed in [7-8]. This methodology includes the application of loop and data flow transformations. However it mainly targets custom hardware architectures and the impact of the transformations on the performance of an implementation based on instruction set processors is not addressed. In this paper a number of code transformations is presented. The effect of the transformations on three basic parameters of embedded multimedia systems namely power, performance and code size is illustrated. The way in which these transformations affect power and performance is analyzed. As test vehicles four well-known motion estimation algorithms are used. The aim of the research under consideration is to develop a methodology for the effective application of code transformations in order to achieve the optimal balance between power consumption and performance. The rest of the paper is organized as follows: In section 2 a brief description of the motion estimation algorithms is given. In section 3 the applied transformations are described in detail. In section 4 the way in which the transformations affect the power consumption and the performance is described. Finally in section 5 some conclusions are offered.
2. Motion estimation algorithms Four typical [11] motion estimation algorithms were used as test vehicles, namely full search, three level hierarchical search (hierarchical), parallel hierarchical one dimensional search (phods) and two dimensional three step logarithmic search (log). Simulations using the luminance component of QCIF frames were carried out. The dimension of the luminance component of a QCIF frame is 144x176 (N×M). The reference window was selected to include 15×15 ((2p+1)×(2p+1) and p=7) candidate matching blocks. Blocks of 16x16 (B×B) pixels were considered. The general structure of the above algorithms is described in figure 1.
for(x=0;x
