Comments on Existing 1/f Noise Models: Spice, HSPICE and BSIM3v3 for MOSFETs in Circuit Simulators J. Rhayem, R. Gillon, M. Tack Alcatel Microelectronics, Westerring 15, 9700 Oudenaarde, Belgium
[email protected]
M. Valenza, A. Hoffmann, A. Eya'a Mvongbote, D. Rigaud Université Montpellier II (CEMII), 34095 Montpellier Cedex 5, France
[email protected]
Abstract Three standard 1/f noise models for MOSFETs are actually implemented in software packages: SPICE, HSPICE and recently BSIM3v3 noise model. The aim of this contribution is to show the limitation for each of these implementations by comparing noise simulations to noise measurement data. We demonstrated that 1/f noise model implemented in SPICE and HSPICE can not predict correctly noise in all operating regimes which limit their usefulness for design purposes. We show that BSIM3v3 shows the best fitting with experimental noise results in all operating regimes.
1. Introduction Flicker noise is an important phenomenon that needs to be accounted for in the design of analog circuits. Moreover 1/f noise level and behaviour are crucial to reach a successful design deck for RF applications. Therefore, for analog simulation, accurate noise models are required in order to predict its impact on circuit behaviour. They must be valid in all operating regimes and agree with physical models. Ideally, a single model, based on physical principles, should describe the low frequency noise in both n-type and p-type MOSFETs and in all accessible drain and gate biases. Three main models are presently available in software packages: SPICE, HSPICE and BSIM3v3 noise model. The aim of this paper is to answer the question of: which model predicts the bias-dependency of the noise power level correctly? In other words: analog circuit designers will rely on which one among these three available models? For the first time, a clear comparison between noise simulation with all three models and noise data measured on nMOS and pMOS from a commercial 025um CMOS technology is presented in this paper. We demonstrate that BSIM3v3 noise model is actually offering the best fit to noise data in all operating regimes.
2. SPICE, HSPICE and BSIM3v3 noise models: description and implementation: Analog circuit designers can choose between three noise models implemented in circuit simulator by setting the correct flags corresponding to each model. In this section we present the empirical noise expressions for each model a/ there are two basic SPICE noise model equations for the drain current of CMOS transistors. One model is [1, 2] S iD (f ) =
KF I AF D f EF C ox L2eff
(1)
where SiD(f) is the drain noise current spectral density, ID is the drain current, KF is the flicker noise coefficient, AF is the flicker noise exponent, EF is the flicker noise frequency coefficient and Leff is the electrical gate length. The other SPICE model which is implemented in some circuit simulators such as SPECTRE (TM) from CADENCE is given by [3] S iD (f ) =
KF I AF D
(2) f EF C ox Weff L eff where Weff is the electrical gate width. By comparing Eq (1) with Eq (2), it is obvious that the geometry dependence between these two models is different if the same AF value is used. The flicker noise exponent AF typically falls in the range of 0.5 to 2. EF can be from 0.8 to 1.2 depending on the technology. b/ HSPICE [4] introduces another flicker noise model with the drain noise current spectral density proportional to gm2
SiD (f ) =
KF g 2m
(3) C ox Weff L eff f EF It is important to point out that in the different SPICE and HSPICE models, KF may have significantly different values and units.
c/ A unified noise model in BSIM3v3 has been proposed [5,6,7] to describe 1/f noise of n-and p-type MOSFET in all operating regimes. The subthreshold 1/f noise is described in BSIM by NOIA: k T NOIA (4) Swi (f ) = I2 D qWeff Leff N *2 γ f with N* = ηC ox
kT . γ is the attenuation coefficient q2
of the electron wave function in the insulator (γ=108 cm-1 for Si-SiO2 interface) and η is related to the subthreshold swing η =
q 1 S. kT 2.3
For VGS>VTH+0.1 (abovethreshold) qkTµ eff I D 1 N + N* + SiD (f ) = NOIA * Ln 0 NL + N * γ L2eff C ox f
NOIB(N 0 − N L ) + kT∆L clm I 2D
(
1 NOIC N 02 − N 2L 2
) +
(5)
NOIA + NOIB * NL + NOIC * NL2
qf EF L2eff Weff γ
(N L + N* )2
∆Lclm refers to channel length modulation: if VDSVTH. This last behaviour is not reflecting noise data, one will never measure a decrease in noise when VGS increases. Nevertheless, following conclusions of ref[16, 17], we can introduce for noise simulation with HSPICE a subcircuit including two access resistances RS and RD. These resistances present 1/f excess noise sources
10-20
10-18
10-20
10-22
10-22
10-24 1
2
VGS (V)
3
Figure 1. Drain current spectral density (at 1Hz) versus gate bias for the nMOS having 10µm/0.24µm. VDS=50mV. Symbols denote noise measurements (▲). Continuous line ( ) is BSIM3v3 noise model and dashed line ( ------- ) is HSPICE noise model. Noise measurements were compared to HSPICE and BSIM3v3 noise models for p-type of MOSFETs in Figure 2. BSIM3v3 noise parameters are: NOIA=1.8 1020 V-1m-3, N*=1.4 1015 m-2, NOIB=7 104 V-1 and NOIC=1 10-12 V-1m. HSPICE noise parameters are: KF=1.5 10-25 and EF=1.2. 10-19
10-24 0
1
2
VGS (V)
3
Figure 3. Drain current spectral density (at 1Hz) versus gate bias for the nMOS having 10µm/0.24µm. VDS=50mV. Symbols denote noise measurements (▲), dashed line ( ------- ) is HSPICE noise model using subcircuit.
SiD(f) (A2/Hz)
0
SiD(f) (A2/Hz)
10-16
10-19
10-21
10-23
10-21
10-25
10-23
10-27 0
-1
-2
-3
VGS (V) 10-25
10-27 0
-1
-2
VGS(V)
-3
Figure 2. Drain current spectral density (at 1Hz) versus gate bias for the pMOS having 10µm/0.5µm. VDS=-50mV. Symbols denote measurements (▲).Continuous line () is BSIM3v3 noise model and dashed line (-------) is HSPICE noise model.
Figure 4. Drain current spectral density (at 1Hz) versus gate bias for the pMOS having 10µm/0.5µm. VDS=-50mV. Symbols denote measurements (▲), dashed line ( ------- ) is HSPICE noise model using subcircuit.
In these cases for n MOSFETs, we obtain good agreement between simulated and experimental data, whereas for p MOSFETs simulation does not fit experimental data. This fact confirms the theoretical
SiD(f) (A2/Hz)
comparison made in the previous session between HSPICE noise formula and physics-based 1/f noise model for p MOSFETs. In figures 4 and 5, noise spectral density measurements have been compared to BSIM3v3 and HSPICE simulated data in the saturation regime ( VDS =1.5V) for n MOS and p MOS, respectively. The same set of noise parameters has been used to simulate noise in this regime. In the saturation and at high VGS, there is no decrease in HSPICE noise simulation since typically the gm curve shows no degradation at high VGS in the saturated region. These figures confirm that the HSPICE model is not accurate when carrier mobility fluctuations occur, i.e. for p-MOSFETs . BSIM3v3 noise model fits noise data in this regime. 10-14
10-16
10-18
10-20
10-22
10-24
0
1
2
VGS (V)
3
SiD (f) (A2/Hz)
Figure 5. Drain current spectral density (at 1Hz) versus gate bias for the nMOS having 10µm/0.24µm. VDS=1.5V. Symbols denote noise measurements (▲). Continuous line ( ) is BSIM3v3 noise model and dashed line ( ------- ) is HSPICE noise model. 10-15 10-17 10-19 10-21 10-23 10-25 10-27 10-29 0
-1
-2
VGS (V)
-3
Figure 6. Drain current spectral density (at 1Hz) versus gate bias for the pMOS having 10µm/0.5µm. VDS=-1.5V. Symbols denote measurements (▲). Continuous line ( ) is BSIM3v3 noise model and dashed line ( ------- ) is HSPICE noise model.
5. Conclusion The limitations of available noise models in commercial CAD tool have been presented based on a comparison to noise data. The SPICE noise model is not accurate to follow noise behaviour and level in all operating regimes whatever the device type. The
HSPICE noise model cannot predict noise for p-type MOSFETs. For n-type, where ∆N model is applied, this model is suitable if a subcircuit including access resistances and their associated excess noise sources. The BSIM3v3 noise model, comparing to these previous models, is offering the best fit to noise data in all operating regimes.
6. Acknowledgement This work was supported by MEDEA T554 CMOS RF project from the EU and the IWT COMRAD project from the Flemish community.
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