port statement. The second part of the VHDL-AMS code is self-explicit. The device behavior is defined in an architecture named symmetric (130 lines of code.
This paper deals with the compact modeling of several emerging technologies: first, the double-gate MOSFET (DG MOSFET), and second, the carbon nanotube field-effect transistor (CNTFET). For CNTFETs, we propose two compact models, the first one with a classical behavior (like MOSFET), and the second one with an ambipolar behavior (Schottky-barrier CNTFET). All the models have been compared with numerical simulations and then implemented in VHDL-AMS.
carbon nanotube-based transistors (CNTFETs) are regarded as an important contending device to replace silicon transistors [AAMW03]. These new technologies and devices require the creation of accurate compact models, suited to the circuit design and easily translatable into a hardware description language (HDL) such as VHDL-AMS This paper is organized as follows. In Section 2, we present an explicit model for the symmetric DG MOSFET that is simple, inherently continuous and computationally efficient. By introducing useful normalizations as in the EKV MOSFET model, we have derived simple and clear relationships which are really helpful for the circuit designer [SKP+ 05]. In Section 3, we propose two compact models for CNTFETs, the first one with a conventional behavior (i.e. a MOSFET behavior), and the second one with an ambipolar behavior. The former is based on a existing model developed at Purdue University [RMR04]. Unfortunately, in its present form, this model is not appropriate for circuit simulation. In this paper, we propose an efficient compact model for the designer, with a range of validity clearly defined. The second model is devoted to compact modeling of the CNTFET with an ambipolar behavior (n- or p-type depending of the gate voltage value). This characteristic is quite different from a classic behavior, namely a MOSFET behavior. To our best knowledge, this compact model is the first analytical ambipolar model for CNTFET introduced in the literature. It is a behavioral compact model that simulates in a realistic way the ambipolar characteristic observed with Schottky-Barrier (SB) CNTFETs.
1
2
Compact Modeling of Emerging Technologies with VHDL-AMS F. Pr´egaldiny, C. Lallement, B. Diagne InESS / ENSPS Parc d’innovation, BP 10413 67412 Illkirch Cedex, France J.-M. Sallese, F. Krummenacher IMM-EPFL CH-1015, Lausanne, Switzerland
Abstract
Introduction
Since the introduction of transistors, continuous reduction of electronic circuit size and power dissipation have been the ongoing theme in electronics industry. The well-known “Moore’s law” represents this evolution. However as the feature size becomes smaller, scaling the silicon MOSFET becomes increasingly harder. This increasing challenge is often attributed to: 1) quantum mechanical tunneling of carriers through the thin gate oxide; 2) quantum mechanical tunneling of carriers from source to drain and from drain to body; 3) control of the density and location of dopant atoms in the channel and source/drain region to provide high on/off current ratio. There are many solutions proposed to circumvent these limitations. Some solutions include modifications on the existing structures and technologies in hopes of extending their scalability. The DG MOSFET is recognized as one of the most promising candidates for future very large scale integrated (VLSI) circuits [FDN+ 01, itr]. In DG MOSFETs, short-channel immunity can be achieved with an ideal subthreshold swing (60 mV/dec). Other solutions involve using new materials and technologies to replace the existing silicon MOSFETs. Among them, new device structures as
2.1
Double-Gate MOSFET A compact model dedicated to the design
For the past decade, a significant research effort in this field has led to the development of physical models for the DG MOSFET [GF02, Tau00, FGC+ 04]. These models are of major interest for the design of the device itself but less useful for circuit simulation since they rely on very complicated formulations. Among the proposed models, Taur’s model [TLWL04] is one of the best candidates for building a compact model. An exact solution for both charges and current has been proposed and successfully validated. However, such a model, in its current form, is not really suited for circuit simulation because it does not provide solutions to model the transcapacitances when the drain-to-source voltage is not zero. Furthermore this model requires an iterative procedure to compute the mobile charge density, which is generally considered to be time consuming. The main assumptions of our new model are the following: the body (i.e. the silicon layer) is undoped or lightly doped, the mobility is constant along the channel and both quantum effects and polydepletion effect
are neglected. The last assumption is valid for sili- Integrating (3) from source to drain yields con layer thicknesses down to at least 20 nm. For q α · qm md 2 thinner layers, quantum effects start to play a role 2 · ln 1 − (4) i = −q + 2 · q + m m α 2 [GF02, FGC+ 04], but might actually be considered as qms a correction to the classical derivation. The schematic diagram of the DG MOSFET considered in this work Finally, the drain current ID is obtained after denormalization of (4) as outlined in [PKD+ 06]. is shown in Fig. 1. To conclude this brief description of the model, it VG should be said that in addition to the static part, a more complete compact model should include the dyt namic part, i.e. the transconductances and the whole Gate ox set of transcapacitances. The derivation of the dynamic model is not within the scope of this paper and the Source Drain VS VD t si reader is referred to references [SP00, PKS+ 06] for full L (n+) (n+) details. However, let us emphasize that the VHDLAMS code of our model includes both static and dyGate t ox namic models [PKD+ 06]. VG
2.2
Figure 1: Schematic of the DG MOSFET structure. Using the normalization of charges, potentials and current proposed in [SKP+ 05] leads to an important relationship between charge densities and potentials, given by Cox1 vg∗ − vch − vto = 4 · qg + ln qg + ln 1 + qg · (1) Csi where vg∗ is the effective gate voltage (= vg − ∆φi with ∆φi the work function difference between the gate electrode and intrinsic silicon), vch is the electron quasiFermi potential, vto is the threshold voltage, qg is the charge density per unit surface of each gate, Cox1 is the gate oxide capacitance per unit surface of each gate and Csi is the silicon layer capacitance per unit surface. Such a normalization represents an efficient tool for the analog designer because it is done taking into account the design methodologies requirements [EKV95]. However, (1) needs to be solved numerically and this is not desirable for circuit simulation (it requires at least several iterations). To overcome this drawback, we have developed a new methodology to compute without any iteration the mobile charge density as an explicit function of bias voltages (vg and vd or vs ) [PKD+ 06] qg = f (vg , vch ) with vch = vs or vd
(2)
Without entering into details, the numerical inversion of (1) can be performed using a reduced set of precomputed parameters that depend only on the so-called “form factor” α (= Cox1 /Csi ). Let us emphasize that our algorithm of numerical inversion fully preserves the physics of (1), and therefore its validity is technologyindependent [PKD+ 06]. Then, noting that the mobile charge density is twice the gate charge density (qm = −2 qg ) and assuming that the drift-diffusion transport model is valid, the normalized drain current i can be expressed as Z vd i=− qm · dvch (3) vs
VHDL-AMS implementation
VHDL-AMS [vhd99] is a HDL language which supports the modeling and the simulation of analog and mixed-signal systems. It supports the description of continuous-time behavior. For compact modeling, the most interesting feature of the language is that it provides a notation for describing Differential Algebraic Equations (DAEs) in a fairly general way [PLV05]. The == operator and the way the quantities (bound to terminals or free) are declared allow the designer to write equations in either implicit or explicit format. VHDL-AMS supports the description of networks as conservative-law networks (Kirchhoff’s networks) and signal-flow networks (inputs with infinite impedance, outputs with zero impedance). As such, it supports the description and the simulation of multi-discipline systems at these two levels of abstraction. Conservativelaw relationships assume the existence of two classes of specialized quantities, namely across quantities that represent an effort (e.g., a voltage for electrical systems), and through quantities that represent a flow (e.g., a current for electrical systems). Listing 1 presents the entity part of the VHDL-AMS code for the DG MOSFET model. The code first contains references to libraries needed to parse the model (lines 1–3). For the model end-user (circuit designer), the most important part of the model is the interface, contained in what is called an entity in VHDL-AMS (lines 4–11). (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11)
library ieee; library disciplines; use disciplines.electromagnetic_system.all; use work.all; entity dg_mosfet is generic(W :real:= 1.0e-6; -- Gate width [m] L :real:= 1.0e-6; -- Gate length [m] tox1 :real:= 2.0e-9; -- Gate oxide thick. [m] tsi :real:= 25.0e-9; -- Si film thick. [m] mu0 :real:= 0.1); -- Low-field mob. [m^2/Vs] port (terminal g1,g2,d,s :electrical); end;
Listing. 1. Interface of the DG MOSFET VHDL-AMS model: the entity.
The model interface includes the specification of generic parameters (lines 5–9) and interface ports (line 10). The generic statement allows the designer to define its own values for the model parameters. Typically, geometrical W and L transistor parameters are defined as generic. The dg_mosfet entity contains four terminals (g1, g2, d and s stand for the top gate, bottom gate,drain and source terminal, respectively), all of electrical type. All the terminals are part of a port statement. The second part of the VHDL-AMS code is self-explicit. The device behavior is defined in an architecture named symmetric (130 lines of code [PKD+ 06]).
2.3
|Normalized transcapa.| (-)
1.0 L = 300 nm tsi = 10 nm
0.8
Cgg
Vds = 0 V Vds = 0.5 V
Cgg
0.6 Csg,Cdg 0.4 Csg 0.2
Cdg
0.0 0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
Gate voltage, Vgs (V)
Figure 3: Comparison between the C–V curves obtained by the explicit model (lines) and 2D simulations (markers).
Results and discussion
To conclude this section, we present the results obtained with the VHDL-AMS simulations of the DG MOSFET model. Fig. 2 illustrates the computation of the drain current ID at VDS = 50 mV and 1 V. The VHDL-AMS simulation gives evidence for the good numerical behavior of the model in all regions of operation. In particular, the phenomena of volume inversion (i.e. the weak-inversion region) is well described. Fig. 3 shows a common set of normalized transcapacitances (with respect to COX = 2W LCox1 ) versus the gate voltage. An important point is that all transcapacitances are continuous between all operating regions without using any fitting parameter, which makes our explicit model numerically robust as well as close to physics. It appears that the model predictions are accurate and fit the 2D simulations in all cases, namely at VDS = 0 and VDS 6= 0. The slight deviation in the subthreshold region results from the increasing influence of the overlap capacitance as the channel length decreases. For devices with L > 1 µm, the overlap capacitance is negligible. A further development of the model will include the extrinsic capacitances.
3
CNTFETs
ID (A) in log. scale
ID (A) in linear scale
Carbon nanotubes (CNTs) are currently considered as promising building blocks of a future nanoelectronic technology. CNTs are hollow cylinders composed of one or more concentric layers of carbon atoms in a honeycomb lattice arrangement. Single-walled nanotubes (SWCNTs) typically have a diameter of 1–2 nm and a length up to several micrometers. The large aspect ratio makes the nanotubes nearly ideal one-dimensional (1-D) objects, and as such the SWCNTs are expected to have all the unique properties predicted for these low-dimensional structures [AAMW03]. In addition, depending on the detailed arrangement of the carbon atoms the SWCNTs can be metallic or semiconducting. Two types of semiconducting CNTs are being extensively studied. One of these devices is a tunneling device, shown in Fig. 4(a). It works on the principle of direct tunneling through a Schottky barrier at the source-channel (and drain-channel) junction. The barrier width is modulated by the application of gate voltage and thus the transconductance of the device is dependent on the gate voltage. To overcome -3 10 2 these handicaps associated with the SB CNTFETs, µ0 = 0.1m /(V.s) -4 10 there have been attempts to develop CNTFETs which -3 tsi = 25nm 1.5x10 -5 tox = 2nm 10 would behave like normal MOSFETs [Fig. 4(b)]. In VDS=50mV -6 W/L = 1 VDS=1V 10 this MOSFET-like device, the ungated portion (source -7 10 and drain regions) is heavily doped and the CNTFET 1.0 -8 operates on the principle of barrier-height modulation 10 VDS=1V -9 by application of the gate potential. In this case, the 10 -10 on-current is limited by the amount of charge that can 10 Exact model [TLWL04] 0.5 -11 be induced in the channel by the gate. It is obvious VHDL-AMS simul. V =50mV 10 DS -12 that the MOSFET-like device will give a higher on10 -13 current and, hence, would define the upper limit of 10 0.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 performance. Gate voltage, VGS (V) Transport through short nanotubes has been shown to be free of significant acoustic and optical phonon Figure 2: Comparison between the results extracted scattering and thus is essentially ballistic at both high from a VHDL-AMS simulation and the exact model and low voltage limits. In the following, we consider (dots, cf. [TLWL04]) for the drain current ID vs. VGS MOSFET-like mode of operation, and assume ballistic of a symmetrical DG MOSFET. transport.
The theory of CNT transistors is still primitive and the technology is still nascent. However, evaluation of such high-performance transistors in digital circuits is absolutely essential to drive the device design and understand the bottlenecks in multi-gigahertz processor design. However, from the circuit designer’s point of view, circuit simulation and evaluation using CNTFETs is challenging because most of the developed models are numerical, involving self-consistent equations which circuit solvers like SPICE are not able to handle.
3.1
MOSFET-like CNTFET
First, we present a compact model for CNTFETs with a classical behavior. This compact model is based on a CNTFET model developed at Purdue University [RMR04]. To our best knowledge, this is the first compact model (i.e., fully dedicated to circuit simulation) of CNTFET available in the literature. It is a surface potential-based SPICE compatible model that enables to simulate CNTs with ballistic behavior. It has been incorporated in HSPICE but is not well-suited for circuit simulation due to some convergence issues. In this paper, we propose a modified model with fundamental improvements solving the convergence problems of the original model. The new model is applicable to a wide range of CNTFETs with diameters between 1 to 3 nm and for all chiralities as long as they are semiconducting. The model uses suitable approximations necessary for developing any quasi-analytical, circuit-compatible compact model (see Fig. 5). Quasi-static characteristics (I-V ) have been modeled and validated against numerical models, with an excellent agreement. The computional procedure to evaluate the drain current ID and the total channel charge QCN T is illustrated in Fig. 6. The main quantities used in the model are the surface potential ψS (or control potential) and the specific voltage ξS(D) that depends on the surface potential, the subbands energy level ∆p and the source (drain) Fermi level µS(D) . The conduction band minima for the first subband is set to half the nanotube bandgap ∆1 with ∆1 ≃ 0.45/diam (in eV). The physical
Drain RD
CGD Gate
ID VFB
CGS
CGD CGS RD RS VFB ID
gate-drain capacitance gate-source capacitance drain resistance source resistance flatband voltage drain current
RS Source Figure 5: Schematic of the CNTFET compact model. diam, VFB, TYP, p (only for test purpose)
Precomputed parameters: α, ∆VFB
VG, VD, VS Subband minima ∆p Eq. (7)
Control potential: ψS
Source/Drain Fermi level: µS, µD
Specific voltage: ξS, ξD ξS/D = (ψS-∆p-µS/D) / (kB.T) Eq. (8)
Eq. (10)
Drain current: ID
Channel charge: QCNT Capacitances: CGS, CGD
Figure 6: Structure of the CNTFET compact model. parameter diam is the nanotube diameter (in nm); it is one of the only three intrinsic parameters of our model, with the flatband voltage VF B and the TYP parameter (= +1/ − 1 for n- or p-type device). Let us emphasize the number of subbands p has been added as an input parameter only for test purpose [PLK06]. Determination of the surface potential An important step in the model development is to relate the control potential with the gate bias voltage (see Fig. 6). The knowledge of ψS is useful to calculate the specific voltage ξ. This allows us to determine the drain current and the total charge. In [RMR04], the following approximation has been proposed 0 for VGS < ∆1 , (5) VGS − ψS = α · (VGS − ∆1 ) for VGS > ∆1 . where the parameter α is given by
(a)
(b)
2 α = α0 + α1 · VDS + α2 · VDS
(6)
where α0 , α1 and α2 are dependent on both CNTFET Figure 4: Different types of CNTFETs: (a) Schottky- diameter and gate oxide thickness [PLK06]. Eq. (5) is barrier (SB) CNTFET with ambipolar behavior, and correct to model the relationship between the gate volt(b) MOSFET-like CNTFET with classic behavior. age and the surface potential, but is not well-suited for
0
10
30
n/N0 (in log. scale)
(8) where p is the number of subbands, kB and h are the constants of Boltzmann and Planck, respectively.
Eq. (10) is unfortunately not appropriate for circuit simulation because its derivatives are not continuous (Fig. 8). So, the different capacitances determined with (10) would not be correct to elaborate the CNTFET dynamic model. In addition, this would lead to numerical problems during simulation and wrong results.
10
20 10
10
Quantum-Capacitance Derivation With the knowledge of charge and surface potential as functions of gate bias, the gate input capacitance CG can be computed in terms of the device parameters and terminal voltages. The gate-input capacitance is given by ∂QCN T ∂VGS
⇒ CG =
∂QCN T ∂ψS · ∂ψS ∂VGS
where the parameters A and B are dependent on the energy level ∆.
VDS = 0V VDS = 0.5V VDS = 0V VDS = 0.5V
dψS/dVGS
1.0
[RMR04] [RMR04] [Our model] [Our model]
0.9
0.8
0.7
0.12
0.13
0.14
0.15
0.16
0.17
0.18
Gate voltage, VGS (V)
Figure 7: Derivative of surface potential ψS vs. VGS .
-4
-6
∆ = 0.15 eV [RMR04] ∆ = 0.35 eV [RMR04] ∆ = 0.15 eV [our model] ∆ = 0.35 eV [our model]
-8
-20
-10
0
ξ
10
20
10
0
30
(a) n/N o vs. ξ as a function of the energy level ∆.
(9)
The total charge QCN T can be split up into QS and QD and, hence, the total gate capacitance can also be split up into CGS and CGD (see Fig. 5). To elaborate an efficient expression of CG for a compact model, it is important to first have a closed-form expression of QCN T (ψS ) and continuous derivatives of (9) as well. As it is not possible to obtain a closed-form relationship for the quantum-charge in the channel, an empirical solution (fit) has been proposed in [RMR04]. Noting that the number of carrier n increases almost linearly as ξ increases and falls off exponentially as ξ becomes negative, the following relationship has been derived N0 · A · exp ξ for ξ < 0, n= (10) N0 · (B · ξ + A) for ξ > 0.
1.1
10
4
∆ = 0.15 eV [RMR04] ∆ = 0.35 eV [RMR04] ∆ = 0.15 eV [our model] ∆ = 0.35 eV [our model]
3
d(n/N0)/dξ
CG =
-2
n/N0 (in linear scale)
a compact model (problem of discontinuity, as shown in Fig. 7). Therefore, we propose an equivalent solution, given by (7), but with an excellent behavior of the derivative (see Fig. 7) q 2 α(VGS − ∆1 ) + [α(VGS − ∆1 )] + 4ǫ2 ψS = VGS − 2 (7) where ǫ = 5 · 10−4 is a smoothing parameter. Then, the total drain current ID is obtained as 4 q kB T X [ln(1 + exp ξS ) − ln(1 + exp ξD )] ID = h p
2
1
0 -4
-2
0
2
4
ξ (b)
d(n/N o) vs. ξ as a function of the energy level ∆. dξ
Figure 8: Improvement of the numerical behavior. In order to solve the numerical problems, we have elaborated a new equation for n, similar to the interpolation function of the EKV MOSFET model [EKV95]. This new expression and its derivatives are continuous [Figs. 8(a) and 8(b)] and more appropriate for circuit simulation, especially in dynamic operation. Fig. 8 shows a comparison between (10) and our continuous equation. Let us note that the greatest difference can be observed around zero, where actually the former overestimates the quantum-charge (see Fig. 4 in [RMR04]). Fig. 9 shows the drain current of a 1.4 nm diameter CNTFET with Cox = 3.8 pF/cm as a function of gate voltage. The dots correspond to the numerical solutions performed with the FETToy simulator [nan] whereas the lines correspond to our analytical compact
100 100
4.0
7 6 5
Diameter = 1 nm Cox = 3.8 pF/cm VDS = 20 mV
3 2
60 10 7 6 5
40
4
VDS = 40 mV VDS = 1 V
3 2
3.5
ID (µA)
80
ID (µA) in linear scale
ID (µA) in log. scale
4
3.0
2.5
p=1 p=2
2.0
20 1.5
1 0.0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.1
0.2
0.8
Gate voltage, VGS (V)
Figure 9: Comparison between the results extracted from VHDL-AMS and numerical simulations (lines and dots, respectively) for the drain current of a MOSFETlike CNTFET (p=1, diam=1.4, TYP=+1, VFB=0).
3.2
(1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11)
library ieee; library disciplines; use disciplines.electromagnetic_system.all; use work.all; entity CNTFET is generic(diam : real := 1.4; --diameter [nm] TYP : real := 1.0; --n/p-CNTFET (+1/-1) VFB : real := 0.0; --flatband voltage p : positive := 1; --subbands number Rseries : real := 50.0e3); --RS+RD [ohm] port(terminal g,d,s : electrical); end;
Listing 2. Interface of the CNTFET VHDL-AMS model: the entity.
Let us note that the number of subbands p has been defined as a generic parameter only for test purpose [PLK06]. The parameters α0 , α1 and α2 [see (6)] are determined in a precomputed module, with the help of one equation for each of them. For all details about the computation of the parameters α, the reader is referred to [PLK06].
0.5
0.6
0.7
0.8
Diameter = 2 nm Cox = 3.8 pF/cm VDS = 20 mV
5
4
3
VHDL-AMS implementation
First, we have calibrated the model of Purdue with respect to numerical simulations [GLD02, nan]. The best fits were obtained with p = 1 (i.e. one subband) which is coherent because the FETToy simulator only accounts for the lowest subband. So, at the beginning, we fixed p = 1 in our model in order to validate it with respect to the numerical simulations. Then, if we consider CNTFETs with diameters ranging from 1 to 3 nm, and with a power supply lower than 1 V, we can set p = 5 to accurately describe all cases [PLK06]. The whole VHDL-AMS code of the model requires about 90 lines. Only three intrinsic parameters are necessary: diam, TYP (+1 for n-type, -1 for p-type) and VF B (lines 5–7 in Listing 2).
0.4
6
ID (µA)
model. A good agreement is found, which supports the validity of our approach.
0.3
Gate voltage, VGS (V)
p=1 p=2
2
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
Gate voltage, VGS (V)
Figure 10: VHDL-AMS simulations of ID vs. VGS at low drain bias. To conclude this section, Fig. 10 shows two VHDLAMS simulations performed for different values of the parameters diam and p, in order to show the effect of the nanotube diameter on the number of subbands p to be accounted for. This behavior may be useful to create novel multiple-valued logic design [RR05].
3.3
Ambipolar CNTFET
We present, for the first time to our best knowledge, a behavioral compact model that allows to describe the ambipolar characteristic of SB CNTFETs. This model is built using the new model of CNTFET previously presented; an additional part has been added to the original model [PLK06]. The entity (VHDL-AMS) corresponding to this new model is the same as the classical CNTFET model one. The very particular ID –VGS characteristic of the ambipolar CNTFET is illustrated in Fig. 11. It should be noted that this behavior is quite similar to the numerical simulation results recently published in [KMA05] and [GDL04]. This ambipolar characteristic should allow circuit designers to devise new architectures using that specific behavior [SBBK06]. Our compact model may be of help to this issue.
-4
10
[FGC+ 04]
J.G. Fossum, L. Ge, M-H. Chiang, V.P. Trivedi, M.M. Chowdhury, L. Mathew, G.O. Workman, and B-Y. Nguyen. A process/physics-based compact model for nonclassical CMOS device and circuit design. Solid-State Electron., 48:919–926, 2004.
[GDL04]
J. Guo, S. Datta, and M. Lundstrom. A numerical study of scaling issues for schottky-barrier carbon nanotube transistors. IEEE Trans. Electron Devices, 51(2):172–177, 2004.
[GF02]
L. Ge and J.G. Fossum. Analytical modeling of quantization and volume invesion in thin Si-film double-gate MOSFETs. IEEE Trans. Electron Devices, 49(2):287–294, 2002.
[GLD02]
J. Guo, M. Lundstrom, and S. Datta. Performance projections for ballistic carbon nanotube field-effect transistors. App. Phys. Letters, 80(17):3192–3194, 2002.
-5
ID (A)
10
-6
10
-7
10
VDS = 0.2V VDS = 0.4V VDS = 0.6V VDS = 0.8V
-8
10
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
Gate voltage, VGS (V)
Figure 11: VHDL-AMS simulation of the drain current as a function of gate voltage for the ambipolar SB CNTFET (p=1, diam=1.4, TYP=+1, VFB=0).
4
Conclusion
In this paper, different VHDL-AMS models for emerging technologies have been proposed. The DG MOSFET model is still under development, it will be completed with the modeling of additional effects such [itr] as quantum effects, extrinsic capacitances, in order to simulate accurately ultra short-channels DG MOSFETs. The second part of the paper dealt with the compact modeling of the CNTFET with VHDL-AMS. Two CNTFET compact models have been presented, [KMA05] the first one for carbon nanotubes with a classical behavior (like MOSFET), and the second one for devices with an ambipolar behavior. Although CNTFET technology is still nascent, these compact models developed in VHDL-AMS are useful tools to help the designers to devise new architectures. [nan]
Acknowledgment + This work was partially funded by the French Min- [PKD 06] istry of Research under Nanosys (“Programme ACI Nanosciences”).
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