Comparing Master-Slave Topologies for Time Signal Propagation Jos´e Roberto C. Piqueira† Escola Polit´ecnica da Universidade de S˜ao Paulo Avenida Prof. Luciano Gualberto, travessa 3, n. 158, 05508-900, S˜ao Paulo, SP, Brasil Phone: (55)(11) 3091-5647
[email protected] †
Abstract Since phase-locked loops (PLLs) were conceived by Bellescize in 1932, their presence has become almost mandatory in any telecommunication device or network, for being the essential element to recover frequency and phase information. Several models and implementation architectures appeared, following the strong electronic and computation evolution that occurs daily. Here, by using simulation techniques, one-way master-slave network architectures are studied concerning synchronization performance between nodes geographically separated
KEYWORDS: Equilibrium, master-slave, perturbation, simulation, synchronization, time signal.
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Introduction
Phase and frequency synchronization problems are present in electronic engineering since the first coherent modulation systems were developed, with the phase-locked loop implemented by using discrete components, performing the important function of detecting the time basis coming from a remote point [de Bellescize, 1932]. When the television systems were conceived, vertical and horizontal signalsmust had been synchronized by a periodic pulse, a function implemented by using the PLL architecture [Wendt and Fredendall, 1943]. For the development of color television, PLL were essential for synchronizing color beams [Richman, 1954]. Essentially, all of these PLL systems were a closed loop composed of a phasedetector (PD), a filter (F) and a voltage-controlled oscillator (VCO), as shown in Fig. 1. The PD compares the phase of the input signal, vi (t), coming from a remote point, with the phase of the local (VCO) oscillation, vo (t), producing an error signal that is filtered and controls the phase of the VCO signal. Around 1965, the first PLL integrated circuits appeared, with all parts implemented with analogical components; however, with very low cost due to the wide range of their application [Best, 2007]. The digitalization of the PLL functions started in 1970 with the PD implemented by an exclusive or (X-OR) or charge pump circuit, presenting good performance [Gardner, 2005]. These developments were simultaneous with the digitalization of the telecommunication networks, in which all of the standard solutions are supposed to 1
Figure 1: PLL block diagram have synchronized time signals exchanged between the nodes [Bregni, 1998, Lindsey et. al, 1985]. With the development of the integrated services, the tendency to the digitalization of all network devices became mandatory, and the PLL, in spite of following the same Bellescize architecture, improved the manner of processing signals, originating the digital PLL (DPLL) circuits and converting the VCO function into digital [Bregni, 1998, Gardner, 2005, Meyr and Ascheid, 1990]. As a consequence of the strong development of integrated circuits and digital filtering [Xiu et. al, 2004], the entire PLL started to be implemented by using flexible architectures, with adequate signal processing functions digitally implemented, generating the all-digital PLL (ADPLL) circuits, which is an important component of the new generation of wireless devices [Staszewski and Balsara, 2015]. This evolution allowed software implemented PLLs [Best, 2007, Xiu et. al, 2004], with connected PLL nodes starting to share the same electronic device. Consequently, to satisfy the rapid internal signal processing, fast synchronization processes are needed to guarantee precise time basis at the several electronic levels: chips, circuits, systems and large distributed networks. Therefore, largely studied synchronization architectures [Best, 2007], with implementations present in almost all telecommunication networks or devices [Bregni, 1998, Leonov et. all, 2015b], demand to be restudied to permit adequation analysis in each case, mainly due to the role played by nonlinearities and perturbations in the context of low level signal propagation. Here, several synchronization architectures are studied with all PLL nodes following the model presented in Fig. 1, i.e., considering that a phase-detector compares the phases of two periodic signals, one coming from the exterior, with θi being the phase of vi (t), and the other, from an internal oscillator, with θo being the phase of vo (t), with the output vd (t) = vi (t) · vo (t). As shown in [Best, 2007, Gardner, 2005], if these inputs are in quadrature, the PD output vd (t) is proportion to this output is proportional to the phase error φ = θi − θo with the addition of a double-frequency term. The filter is supposed to eliminated the double-frequency term, generating the signal vc (t) that controls the VCO phase, according to: θ˙o = K0 · vc (t). In this study, two definitions of synchronous state are presented: phase synchronization and frequency synchronization, considering the main case of
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interest for electrical circuits applications. Definition 1. A phase-locked loop with an architecture shown in Fig. 1 is in a phase synchronous state, for a time interval (t1 , t2 ), if its phase error φ = θi − θo = 0, ∀t ∈ (t1 , t2 ). Definition 2. A phase-locked loop with an architecture shown in Fig. 1 is in a frequency synchronous state, for a time interval (t1 , t2 ), if its frequncy error φ˙ = θ˙i − θ˙o = 0, ∀t ∈ (t1 , t2 ). In the next section, a single node second order PLL is adjusted, and the several cases of synchronization and non synchronization are described and simulated. Then, a single chain master-slave architecture [Cidecyian & Lindsey, 1987, Lindsey et. al, 1985], with three slave nodes is simulated, showing the several possible behaviors of the time basis propagation. To give some comparison ideas, a single star master slave architecture [Cidecyian & Lindsey, 1987, Lindsey et. al, 1985] is studied and its advantages are discussed. A section of conclusions summarizes the main ideas.
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Single node simulations
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Adjusting the node
All the simulations conducted here use the PLL block from the “Communications Systems Toolbox”, built in the MatLab-Simulink version R2015a [Hanselman and Littlefield, 1996] because it follows exactly the mathematical model described here and in [Piqueira, 1987], the work that originated the whole authors work in the area [Piqueira et. al, 2005, Piqueira and Monteiro, 2006, Piqueira and Caligares, 2006]. To work normalized results, the PLL block was adjusted with the parameters: • P Dgain = 1; • F iltertransf erf unction =
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• V COcentralf requency = 2 · π rad/s; • V COinitialphase = 0; • V COgain = 1. The input signal was adjusted with frequency 2 · π rad/s with initial phase equal to zero. The simulation result was the mathematically expected [Piqueira, 1987] i.e., the phase synchronization between the input signal and the VCO output, as the Lissajous figure (Fig. 2) shows, with the input signal in the x-axis and the VCO output in the y-axis. The obtained circle indicates the phase synchronization between the two signals.
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Figure 2: Adjusting the PLL single node
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By using the formerly adjusted PLL block, the single-node behavior was studied, considering a phase step. Two different simulations were conducted: for steps equal π/12(Fig. 3a) and π/2 (Fig. 3b).
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Figure 3: Phase step in a single-node PLL As the second-order PLL is insensitive to phase steps [Best, 2007, Gardner, 2005, Piqueira, 1987], the Lissajous figures result in circles, indicating phase synchronization, with a transitory interval provoked by the step start that occurred for t = 5s.
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Considering that the time constant of the filter is µ1 = 2s, if the ramp inclination Ω < 2, in spite of not having phase synchronization [Piqueira, 1987], the node captures the frequency synchronization with constant phase error, as Fig. 4a shows for Ω = 1, with the Lissajous figure being an ellipse with inclined axis. Increasing the ramp inclination (Ω = 1.5), the transient interval increases, but the ellipse, in spite of being smaller, continues to be clearly the attractor (Fig. 4b). For this point on, a small increase in the ramp inclination (Ω = 1.6) almost
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destroys the attractor (Fig. 4c). 1 0.8
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Figure 4: Phase ramp in a single-node PLL For Ω ≥ 2, the frequency synchronization disappears. Consequently, when designing a network with phase ramp input, the whole PLL gain (K0 ) must be greater the the ramp derivative.
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Single-chain master-slave
Considering the adjusted components of the former section, a four node single chain master-slave architecture was implemented. The master node was considered the master node and three PLLs operated as slave nodes. As the PLL inputs and outputs must be in quadrature, 0.25s transport delays must be considered between two adjacent nodes.
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Adjusting the network
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To test if the network was assembled in the correct way and the transport delays well chosen, a simulation without perturbation was performed. The results comparing the node outputs with the master output are shown in Fig. 5, for the three slaves. In the three cases, the Lissajous figures are circles, indicating phase synchronization.
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Figure 5: Master-slave unperturbed single-chain time basis comparisons
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Phase step perturbation
Considering the single-chain master-slave network formerly implemented, a π/12 step perturbation was introduced into the master phase in t = 5s, to study the effect of its propagation. The results are shown in Fig. 6, indicating a transient de-synchronization tending to a phase synchronization represented by an attractor circle. 1 0.8
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Figure 6: Master-slave single-chain time basis perturbed by a π/12 phase step However, observing Fig. 6 it can be conclude that the farer the slave node is from the master, the longer is the transient de-synchronization. This phenomenon is responsible for a strong limitation in the clock signal precision for long chains [Cidecyian & Lindsey, 1987, Lindsey et. al, 1985]. Larger step perturbations increases the evidence of this transient inadequacy, as Fig. 7 shows, for π/2-step in t = 5s. 1 0.8
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Figure 7: Master-slave single-chain time basis perturbed by a π/2 phase step
3.3
Phase ramp perturbations
Considering that the time constants of the filters are µ1 = 2s, only ramp inclinations Ω < 2, in spite of not allow phase synchronization [Piqueira, 1987], can result in frequency synchronization, as Fig. 8 shows for Ω = 1 ramp. It can be observed that, before the frequency synchronization capture, a large non synchronized transient interval appears and, consequently, applications demanding short time responses and clock precision can not use this type of architecture if a ramp perturbation is expected. Moreover, increasing the 6
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Figure 8: Master-slave single-chain time basis perturbed by Ω = 1 phase ramp
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ramp inclination, even bellow the limit, this phenomenon occurs, as Fig. 9 shows for Ω = 1, 5.
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Figure 9: Master-slave single-chain time basis perturbed by Ω = 1.5 phase ramp
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[Piqueira and Monteiro, 2006] J. R. C. Piqueira & L. H. A. Monteiro, “All-pole phase-locked loops: calculating lock-in range by using Evan’s root-locus”, International Journal of Control, 79(7), pp. 822-829, 2006. [Piqueira and Caligares, 2006] J. R. C. Piqueira & A. Z. Caligares, “Doublefrequency jitter in chain master-slave clock distribution networks: Comparing topologies”, Journal of Communications and Networks, 8(1), pp. 8-12, 2006. [Richman, 1954] D. Richman, “Color-Carrier Reference Phase Synchronization Accuracy in NTSC Color Television”, Proceedings of the IRE, 42, pp. 106133, 1954. [Staszewski and Balsara, 2015] R. B. Staszewski & P. T. Balsara, “PhaseDomain All-Digital Phase-Locked Loop”, IEEE Transactions on Circuits and Systems II: Express Briefs , 52(3), pp.159-163, 2005. [Wendt and Fredendall, 1943] K.R. Wendt & G.L. Fredendall, “Automatic Frequency and Phase Control of Synchronization in Television Receivers”, Proceedings of the IRE, 31(1), pp. 7-15, 1943. [Xiu et. al, 2004] L. Xiu, W. Li, J. Meiners & R. Padakanti, “A Novel AllDigital PLL With Software Adaptive Filter”, IEEE Journal of Solid-State Circuits, 39(3), pp. 476-483, 2004.
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