OSA/OFC/NFOEC 2011
OThQ1.pdf OThQ1.pdf
Optical I/O for Chip-to-Chip Interconnects on CMOS Platform Peter L.D. Chang, Edris M. Mohammed, Bruce A. Block, Miriam R. Reshotko and Ian A. Young Components Research, Technology and Manufacturing Group, Intel 2501 NW 229th Avenue, Hillsboro, Oregon 97124 Email:
[email protected]
Abstract: Optical devices on a CMOS die and package for terabit computing are discussed. 200Gbps transmission is accomplished with a 1x10 VCSEL array. CMOS backend compatible modulators and photodetectors are demonstrated at 40Gbps for on-die integration. OCIS codes: (200.4650) Optical interconnects; (130.6622) Subsystem integration and techniques; (250.5300) Photonic integrated circuits; (250.2080) Polymer active devices; (230.4110) Modulators; (230.5160) Photodetectors.
1. Introduction 100PetaFlop HPC systems will require CPU and chip-to-chip I/O bandwidths in the range of 1Terabit/s or more [1,2]. Such a high bandwidth can only be provided by a high data rate per channel together with a large number of channels operating at low power. High speed electrical I/O devices have been demonstrated with differential signaling. However, power consumption increases with higher data rate and longer distance [2]. In contrast, optical I/O offers low crosstalk and nearly constant power consumption for interconnects
