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attends the IEC 62.132-2 (for radiated EM noise), IEC 61.0004-17 and IEC 61.0004-29 (for .... configure the FPGAs, download software for the ARM7 processor .... [7] “IEC 62132-2, Ed. 1: Integrated Circuits – Measurement of. Electromagnetic ...
Configurable Platform for IC Combined Tests of Total-Ionizing Dose Radiation and Electromagnetic Immunity Juliano Benfica1, Letícia Bolzani Poehls1, Fabian Vargas1, José Lipovetzky2, Ariel Lutenberg2, Sebastián E. García2, Edmundo Gatti3, Fernando Hernandez4, Ney L. V. Calazans5 Electrical Engineering Dept., Catholic University – PUCRS, Porto Alegre, Brazil. [email protected] Facultad de Ingeniería, Universidad de Buenos Aires, Buenos Aires, Argentina. {jlipove, alutenb, sgarcia}@fi.uba.ar 3 Instituto Nacional de Tecnología Industrial – INTI, Buenos Aires, Argentina. 4 Universidad ORT, Montevideo, Uruguay. 5 Faculty of Informatics, Catholic University – PUCRS, Porto Alegre, Brazil. 1

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Abstract - The roadmap for standardization of electromagnetic (EM) immunity measurement methods has reached a high degree of success with the IEC 62.132 proposal. The same understanding can be taken from the MIL-STD-883H for total ionizing dose (TID) radiation. However, no effort has been performed to measure the behavior of electronics operating under the combined effects of both, EM noise and TID radiation. For secure embedded systems and systems-on-chip (SoC) devoted to critical applications, these combined-effect measurements are mandatory. In this paper, we present a configurable platform devoted for combined tests of EM immunity and TID radiation measurements of prototype embedded systems. The platform attends the IEC 62.132-2 (for radiated EM noise), IEC 61.0004-17 and IEC 61.0004-29 (for conducted EM disturbance) and 1019.8 method for TID Test Procedure of MIL-STD-883H. Keywords – Safety system-on-chip, Electromagnetic interference, Total-ionizing dose radiation, Pre-certification testing platform.

I. INTRODUCTION With the widespread use of wireless technology-based embedded systems, the environment in which electronic systems have to operate is becoming increasingly hostile. As consequence of technology scaling, IC’s supply voltage is continuously decreasing, reaching less than 1 volt for the IC core and less than 2 volts for the periphery and I/O pads. This scenario reduces noise margins and increases circuit susceptibility to electromagnetic (EM) noise [1,2]. This exposes the circuit to transient faults and reduces system reliability [3,4]. Furthermore, for critical applications such as military, aerospace or biomedical, reliability assurance to total ionizing dose (TID) radiation is always at a premium being a key-issue for the success of such products in the market. TID effects on CMOS integrated circuits are caused primarily by the trapping of positive charge in oxide regions. For deep-submicron circuits, the main TID effect is the increase of leakage currents and change in current-voltage characteristics of the devices.

Both effects are due to the trapping of charge in shallow trench insulators [5,6]. The variation in electrical characteristics of the devices will lead to variations in parameters of the circuits, e. g. in noise margin or propagation delay. For very high doses, a functional failure of the circuit is observed [5]. Up the present, these concerns have been treated as independent events, where engineers certificate electronic systems to electromagnetic interference (EMI) or TID radiation, or eventually to both of them, but never taking into account the combined effects one phenomenon may take over the other. For instance, assume that a given part of an embedded system (hardware or software) for space application is certified by a set of EMI tests according to specific standards. After a given period of time operating on the field, who can ensure that this part will still perform properly according to the same set of EMI standards, considering that a certain level of TID has been cumulated over the system? The reverse is also questionable: who can ensure that this part will operate properly in a given radiation environment under exposure of high noise levels of EM interference, if the part was certificated independently for EMI and radiation? In this paper, we present a configurable platform suitable for combined tests of EMI and radiation measurements of prototype embedded systems. The platform was built-up in such a way to attend the most representative international standards for measurements on integrated circuits and embedded systems having in mind EMI: IEC 62.132-2 (for radiated noise), IEC 61.0004-17 and IEC 61.0004-29 (for conducted noise) and TID: 1019.8 method for TID Test Procedure of MIL-STD-883H. The remainder of this paper is organized as follows: Section 2 describes the platform, including the hardware and the programming interface used to configure the boards and monitor the system under test. Section 3 briefly describes the international standards for which the platform was designed in

compliance with. Finally, conclusions of the work.

Section

4

summarizes

the

II. THE PLATFORM The hardware part of the platform is based on two specific complementary boards. The first one is a 8-layer board, seen in Figure 1a and 1b, devoted to EM immunity tests. More precisely, two types of EM immunity tests are performed: a)

Radiated noise immunity test, which is carried out in a Gigahertz Transverse Electromagnetic Cell (GTEM Cell) according to the IEC 62.132-2 Std [7];

b)

Conducted noise immunity test, following the IEC Stds. 61.000-4-17 (for ripple on power supply lines) [8] and IEC 61.000-4-29 (for voltage dips, voltage variations and short interruptions on the DC port of electronic systems) [9].

The second board is a 6-layer board (Figure 1c and 1d) dedicated to the 1019.8 method for TID Test Procedure of MIL-STD-883H. Figure 1 presents details of these two boards. In both boards, the most important component is the Xilinx Virtex 4 FPGA, part number XC4VFX12-10SF363, used to map the system-on-chip (SoC) under test.

to generate and individually inject any type of noise on the core, periphery and pad rings of FPGA 0 and/or FPGA1. The program executed by the ARM7 processor is responsible for generating noise according to the following IEC standards: 61.000-4-17 and 61.000-4-29, whose details will be given in the next section.

FPGA VIRTEX 4 (DUT1)

FPGA VIRTEX 4 (DUT0)

Radiated EM immunity test: The board side seen in Figure 1a is called the “test side”, while the other side is said the “glue-logic side”. During a radiated EM immunity test session, this board is placed inside a shielding (metallic) box with an opening upwards where the test side is exposed to radiation, while the glue-logic side is protected inside the shielding box against the EM radiation. By doing so, it is possible to ensure that only the SoC prototyped into the two FPGAs on the test side will be struggled by radiated EM noise, while the remaining logic required for test control such as test vectors generator and compressor, clock generators, reference data for FPGA configuration, board voltage regulators, logic responsible for test monitoring and external environment communicationsupport ICs and connectors (optical fiber, serial RS232, Ethernet connectors) will be protected inside the shielding box. Conducted EM immunity test: The EM immunity test board can also perform conducted EM immunity measurements on the SoC prototyped in the two FPGAs seen in the test side. With this purpose, it was implemented in the glue logic side of this board a conducted VDD noise generator. This noise generator is composed of the ARM7 (LPC2378) processor, SRAM memories, six operational amplifiers and six 12-bit digital-to-analog converters (DAC’s), as seen in the bottom right side of the board in Figure 1b. Based on this infrastructure, the ARM7 processor executes a code that controls the VDD voltage provided to FPGA0 and FPGA1. More precisely, the processor sends a 12-bit digital signal to the DACs, which are connected to the inputs of the operational amplifiers. The outputs of the operational amplifiers are connected to the V DD input ports of FPGA0 and FPGA1. By doing so, it is possible

(a) RS232 connectors Optic fiber connectors

FLASH for FPGA configuration ZigBee Module Footprint FPGA (Test Controller)

SRAM’s

FLASH for data/code

FLASH

Configuration FLASH

Configuration FLASH

SRAM’s

FLASH for data/code

SRAM’s

Board voltage regulators

SDRAM’s

SRAM’s

Operational Amplifiers SDRAM’s

Dual Port SRAM

SRAM’s

DAC’s

ARM7

Voltage regulators for DUT1

Voltage regulators for DUT0

ETHERNET connector

(b)

IEC 61.000-4-Compliant On-Board Noise Generator

FPGA during the session, to provide power-supply to the FPGA under test and to communicate with the test host (PC) computer placed remotely. Fig. 2 summarizes such scenario.

Gamma Cell

Test Control Board (Fig. 1d)

Test Host Computer

Board and FPGA to be tested (Fig. 1c)

RS232 and power supply Cable (power bus and signals), approx. 2 meters

FPGA VIRTEX 4 – DUT0

Figure 2. Configuration for TID radiation test

(c) Optic fiber connectors

SRAM’s

Connectors to couple Boards 1c and 1d

Configuration FLASH

It should be noted that the FPGAs seen in Figure 1a and Figure 1c are the same. The FPGA is mounted on these boards by means of a socket and an adaptor, as depicted in Fig. 3. The socket is soldered on board, whereas the adaptor is soldered on the ball-grid array (BGA) FPGA. In order to perform TID test, the FPGA is placed on board as shown in Figure 1c. Once the test session is accomplished, the FPGA is removed from this board and settled on the socket of the board of Figure 1a, in order to proceed with EM immunity tests. The radiated FPGA can be placed in any FPGA0 or FPGA1 socket. The other socket is used to place a non-irradiated FPGA to be used as gold reference during the EM immunity test sessions. By doing so, the combined test can be performed on both directions, from the TID radiation to the EM immunity test and vice-versa. FPGA

Adaptor

Socket

(d) Figure 1. Hardware parts of the platform. 8-layer board for EM immunity tests: (a) Top; (b) Bottom; 6-layer board for TID tests: (c) Top; (d) Bottom

Figure 3. Mounting the FPGA on boards for EM and TID immunity tests

It is worth noting that based on this infrastructure it is possible to perform not only individual immunity tests for radiated EM or conducted EM, but also combine both experiments into a single test session. For many critical embedded systems, this combined-test scenario may be the most realistic possible condition to “mimic” the harsh environments where they will operate. In the best of our knowledge, this is the first time that this kind of platform is reported.

To conclude about the description of the platform hardware part, it is worth addressing a few words about the distribution of signals and power over the several layers of these boards. According to IEC recommendations for designing test boards, the layer functionality of these boards is as shown in Figure 4. High-sensitivity, high-frequency signals are carried on inner layers, which are involved by power (Gnd and VDD) planes (preferably placing the Gnd plane outer than the VDD one). It should be noted that VDD and Gnd are parallel planes to construct a “natural” decoupling capacitor for the sensitive signals flowing in the board inner layers. Finally, note also that there is a Gnd plane along with the test side of the board. This plane is connected with the Gnd line of the GTEM cell, so that to avoid floating nodes (and so, unwanted currents flowing between the GTEM cell and the system under test. These currents, in addition to eventually damage board electronics, would mask experimental results.

TID radiation immunity test: The board for TID radiation test seen in Figure 1c and 1d is in fact two separate boards that are joined by connectors on their back side. The board of Figure 1c is the one that goes inside the vacuum chamber of the Gamma cell described in the next section. The board seen in Figure 1d contains the glue logic necessary to control the test, to monitor in real-time the

The “X” parameter in this table assumes the same function as the one in Table I. There is also an on-board temperature sensor that can be read by the ARM7 processor in real-time. Figure 5 presents the platform screen used to configure the noise waveform parameters before injecting it into the VDD pin of FPGAs 0 and 1. TABLE II. PREFERRED RANGE OF TEST LEVELS AND DURATIONS FOR RIPPLE ON THE VDD INPUT POWER PORT (IEC 61.000-4-17) (a)

Figure 4. Layer distribution for: (a) EM immunity board, and (b) TID immunity board

The software part of the platform was developed for Windows operating systems. From this software, the user can configure the FPGAs, download software for the ARM7 processor, monitor the system during EM or TID immunity tests and configure noise to be injected into the FPGAs VDD input ports. Basically, any kind of noise waveform can be generated onboard and applied not only to the FPGAs, but also to SRAMs, SDRAMs, Flash or any combination of these ICs. The platform is configured to generate noise on VDD according to the IEC Stds. 61.000-4-17 (ripple on VDD power rail) and 61.000-4-29 (voltage dips, voltage transients and short interruptions) and 61.000-4-17 (ripple on VDD power rail). See Table I for details. The frequency by which noise can be injected in FPGA’s VDD pins can rang from 1 Hz to 120 KHz, with a duty cycle that can vary from 10 to 90%. The noise amplitude can vary from 0 to 100% having as reference the nominal VDD. Table I summarizes the preferred voltage test levels and durations for voltage dips for the standard IEC 61.000-4-29. “X” represents an open value and shall be selected by the product committee [9] to be as representative as possible of the circuit operating conditions. One or more of the test levels and durations specified in this table may be chosen to certificate the product. It is worth noting that for modern nanotechnologies, with VDD equal to or lower than 1 volt, voltage dips of less than 10% (i.e., X=10%) should be assumed. In nanocircuits, on-chip IR-drop and ground bounce may create supply voltage fluctuations which become one of the most important concerns of IC designers. TABLE I. PREFERRED RANGE OF TEST LEVELS AND DURATIONS FOR VOLTAGE DIPS ON THE VDD INPUT POWER PORT (IEC 61.000-4-29) Test Type Voltage Dips

Test Type

Level

Percentage of the nominal DC voltage

Ripple

1 2 3 4 X

2 5 10 15 X

(b)

Test Level (%) 40, 70 or X

Duration (s) 0.01 0.03 0.1 0.3 1 X

Table II summarizes the preferred voltage test levels and durations for ripple noise on d.c. input power port for immunity tests according to the standard IEC 61.000-4-17 [8].

Figure 5. Programming interface of the platform: screenshot of the configuration environment to perform tests according to the IEC standards 61.000-4-17 and 61.000-4-29

III. TEST ENVIRONMENT, PROCEDURES AND STANDARDS Gamma irradiations are applied following the standardized 1019.8 method for TID Test Procedure of the MIL-STD-883H [10]. The radiation source used for the experiments is the Gamma cell shown in Fig. 6, which allows a simultaneous and uniform irradiation of four Virtex-4 (XC4VFX12-10SF363) FPGAs to 60Co source when they are placed in the sample holder. Irradiations are made at room temperature at a dose rate of 0.75 rads/s. Silver Chromate dosimeters are used to measure the total ionizing dose [11]. To evaluate how TID affects embedded system EM immunity, several FPGAs can be irradiated to a wide span of doses. Several works reported that FPGAs fabricated in deep-submicron CMOS processes can withstand TID levels of a few hundreds of krads [5,12,13,14].

Before gamma irradiation, electrical performance tests have to be made on the FPGAs to verify their functionality. During gamma irradiation, the FPGAs are mounted on the board seen in Section 2 (Figure 1c and 1d), while functioning as close as possible to the operating conditions. Figure 7 summarizes the steps to be accomplished. Silver-Chromate dosimeters Around the test fixture, there are 4 boards for EM immunity tests (Fig. 1c, 1d)

The radiated EM immunity tests are performed in a GTEM cell at the Instituto Nacional de Tecnología Industrial (INTI), from Buenos Aires, Argentina. Test conditions are ruled by (but not limited to) the IEC Standard 62.132-2 such as: a) EM field range: from 10 to 220 volts/meter; b) Radiated signal frequency range: [150KHz - 3GHz] (extended IEC 62.132-2); c) Signal modulation format: AM/FM 80%. Figure 8 illustrates the environment for radiated EM immunity tests: the board of Figure 1a and 1b is fixed into the shielding box, inside the GTEM cell. EM test equipments (signal generator, amplifier, EM field monitor and control)

Sample Holder

GTEM Cell

Gamma Cell

Cable connecting the signal amplifier output to the antenna inside the GTEM Cell Test Host Computer

Figure 6. Radiation source used for gamma irradiations at the Centro Atómico Ezeiza, from the Comisión Nacional de Energía Atómica, Argentina.

Board for EM immunity tests (Fig. 1a, 1b). Testside placed outwards the box Shielding box (inside the GTEM Cell)

Figure 8. Environment for radiated EM immunity measurements at the Instituto Nacional de Tecnología Industrial (INTI).

Figure 7. Flux diagram for combined TID + EM immunity tests

Depending on the purpose of the test, radiated and conducted EM immunity measurements are immediately carried out using the board described in Figure 1a, 1b. Alternatively, test engineers may prefer apply worst-case bias conditions to the FPGAs during a given period of time for post irradiation anneal [10] before performing EM immunity measurements. In the latter case, it is worth remarking that special care has to be taken to ensure that all the samples will hold similar anneal times between the end of the TID irradiation and the beginning of the EM immunity tests. This will ensure that the different EM test results observed in the different FPGAs will be due to TID level and not due to different anneal times. In the sequence, the obtained results are compared to the EM test results of a non-irradiated FPGA.

IV. CONCLUSIONS We presented a configurable standard platform for combined tests of electromagnetic (EM) immunity and totalionizing dose (TID) radiation of prototype embedded systems. The platform attends the IEC 62.132-2 (for radiated EM noise), IEC 61.0004-17 and IEC 61.0004-29 (for conducted EM disturbance) and 1019.8 method for TID Test Procedure of MIL-STD-883H. The hardware part of the platform is composed of two boards: the first one was designed for EM (radiated and conducted noise) measurements, while the second board was designed having in mind the TID procedure. The software part is based on a powerful interface used by the designer to configure both boards by one side, and to monitor online the system under test, by the other side. The software part is also responsible for formatting measurement results and generating summary fault dependability reports.

ACKNOWLEDGMENT

[7]

This work has been partially funded by CNPq (Science and Technology Foundation, Brazil) under contracts n. 301726/2008-6 and n. 490547/2007-9.

[8]

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“IEC 62132-2, Ed. 1: Integrated Circuits – Measurement of Electromagnetic Immunity, 150KHz to 1GHz – Part 2: Measurement of Radiated Immunity - TEM Cell Method”. This part of IEC 62132 is to be read in conjunction with IEC 62132-1. (www.iec.ch) “IEC Stds. 61.000-4-17: Electromagnetic compatibility (EMC) – Part 417: Testing and measurement techniques – Ripple on d.c. input power port immunity test”, Edition 1.2, 2009-01. (www.iec.ch) “IEC 61.000-4-29: Electromagnetic compatibility (EMC) – Part 4-29: Testing and measurement techniques – Voltage dips, short interruptions and voltage variations on d.c. input power port immunity tests”, First Edition, 2000-01. (www.iec.ch)

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