CONFIGURING MISR-BASED TWO-PATTERN BIST USING ...

CONFIGURING MISR-BASED TWO-PATTERN BIST USING BOOLEAN SATISFIABILITY Ilia Polian

Bernd Becker

Institute of Computer Science, Albert-Ludwigs-University Georges-K¨ohler-Allee 51, Freiburg im Breisgau, Germany email: polian, becker
@informatik.uni-freiburg.de Abstract. Most known two-pattern BIST architectures require prohibitive test application times in order to obtain high delay fault coverage. In an earlier work, a BIST TPG block based on a MISR expanding input vectors into test sequences of length  has been refined such that shorter sequences could be used. By doing so, spectacular reductions of test application time were achieved. However, the procedures for computing input vectors were based on BDD-backed state traversal or extensive simulation, and their run-time requirements were tremendous. In this work, we propose a SAT-based input vector generation method, which leads to test application times that are similar to the earlier method, but with significantly reduced computational effort. For the first time, we present experimental results for larger ISCAS benchmarks, which previous methods could not treat. Furthermore, we discuss the application of our method when the requirement to apply the complete test pair set is relaxed.

1 Introduction At-speed test for delay defects is crucial for ensuring the quality of today’s integrated circuits. However, the throughput of IC’s pins and the cost parameters of high-speed Automatic Test Equipment (ATE) suggest that the conventional testing (storing the test vectors in ATE’s memory and applying it to the IC) should be avoided. Instead, Built-In Self Test (BIST) has emerged as an option for low-cost at-speed test. Sitting on-chip, a BIST Test Pattern Generator (TPG) is manufactured in the same technology as the block-under-test and does not have to deal with IC pins. Hence, test sequences which the TPG generates can be applied at-speed at no extra cost. Often, the testing complexity is distributed between ATE and the BIST block on-chip. The rationale behind at-speed (self-)test is to detect many delay defects. However, just applying a test sequence with device’s nominal speed does not necessarily yield high coverage of such defects, even if the sequence has high stuck-at fault coverage. Regrettably, most BIST architectures are designed for detecting stuck-at faults. They may also detect delay faults incidentally, but they do not guarantee high coverage of these faults. In order to test for a delay fault, two successive test patterns (a test pair) must be applied to the block-under-test (two-pattern testing). In [19], a BIST architecture based on a MultipleInput Signature Analyzer (MISR) with dimension  equal to the number of inputs of the block-under-test was introduced. An Input Vector (IV) is applied to MISR’s input and held constant for   cycles. Consequently, a sequence of length   is generated at MISR’s outputs and applied to the block-under-test. Thereafter, the next IV is applied and the MISR generates a new sequence, and so forth. The IVs are determined in a way that each test pair from a predefined set occurs in at least one of the sequences generated by the MISR. The test pairs can be generated for any fault model requiring two-pattern testing.

dn-2

d1

d0

...

MISR

Block Under Test

Output Response Analyzer

Input Vectors

dn-1

yn-1

yn-2

y1

y0

Figure 1: The BIST architecture and the MISR of dimension

Being a low-cost solution guaranteeing any quality level given by the used set of test pairs, the method from [19] suffers from prohibitive test application times, which are exponential in the number  of inputs of the block-under-test. In [10, 14], we proposed methods allowing to replace  by an arbitrary number of cycles
. Our methods used extensive simulation or BDD-based state traversal. We were able to considerably reduce the test application time, but the run-times of the algorithm were quite high and only smaller ISCAS benchmarks could be treated. In this work, we present a SAT-based procedure for IV generation. It resembles in some sense the way ATPG tools generate test patterns. Furthermore, we examine the effects of relaxing the demand that each test pair be generated. Although the test application time for smaller ISCAS benchmarks is higher than in our previous method, the run-times are now reasonable. We were also able to treat all ISCAS benchmarks for which distributed BIST is sensible (circuits with over 600 inputs should be dealt with using some modification of scan BIST). The rest of this paper is organized as follows: related work is reviewed in the next section. A detailed description of the proposed BIST architecture is given in Section 3. In Section 4, the new method for computing Input Vectors is presented. Experimental results can be found in Section 5. Section 6 concludes the paper.

2 Related Work Applying all possible test pairs to a combinational circuit will test for all delay faults. For a circuit with  inputs, there are      different pairs, and this number of clock cycles is required for applying them (this technique is known as exhaustive testing). Note that an LFSR of dimension  is capable to go only through at most     different states, so a larger LFSR or Cellular Automaton is required [16]. In [5], Chen and Gupta discuss the design of   -dimensional LFSRs suitable for exhaustive testing. The same authors provide some theoretical foundations in [4]. Smith [15] proved that adjacency testing, a technique based on applying all possible test pairs which differ in only one bit position (Single Input Change, SIC), is sufficient for a robust test of all robustly-testable path delay faults). The length of a sequence containing all SIC pairs is  cycles. Wang and Gupta combine in [18] a weighted random pattern generator (WRPG) with a scan shift register (SSR), in order to obtain all SIC pairs in which a vector generated by WRPG occurs. Some improvements and extensions are presented in [7, 8]. Furuya and McCluskey [6] perform some analysis on two-pattern test capabilities of some circuits. Pilarski and Perzy´nska [13] apply the Circular Self Test Path technique to twopattern testing and propose some extensions. Mukherjee et al. [12] present a modification of an LFSR with a shadow register. While ROM-based approaches impose high area overhead and exhaustive and adjacency testing are impractical in most cases due to their test application time, other mentioned approaches are not suited for generating a pre-defined test set. Hence, no fault coverage can be guaranteed without performing fault simulation of the generated sequences. Moreover, it is not known in advance how long the generated sequence should be in order to meet a fault coverage target. This is the reason why we have chosen the structure used by Wurth and Fuchs in [19], as the foundation for further research, including this paper.

3 The BIST Architecture The general BIST architecture is shown in Figure 1 (left). The inputs of the block-undertest are connected to the outputs of a Multiple Input Signature Register (MISR), shown on the right hand side of the same figure. The number  of its inputs, outputs and memory elements (stages) is called dimension of the MISR. Since the stages are directly connected to the outputs, the MISR’s internal state determines its output value. If all inputs of the MISR are held constantly at 0, it behaves like a Linear Feedback Shifting Register (LFSR). The MISR is used for generating the sequences in which the given two-pattern test set is embedded. For a block-under-test with  inputs, a MISR of dimension  is used. For an Input Vector and an internal state
, the MISR will compute its next state according to the following function (defined separately for each bit): 
      

  
      
 

       
    If is held constant at the inputs state
 for
cycles, the  of  the MISR  with  internal      MISR will
,  


 
" , $# 
    run through
 states  !


  !
 %  , till '& 
 . This sequence of states is directly visible on the MISR outputs and applied at-speed to the inputs of the block-under-test. It can be utilized for detecting delay faults by inducing necessary transitions. We say that for
  , an Input Vector/ produces a test pair (*)  !+, "- in
steps if    
. !
 + and  !
 - holds. If the test pair 01 32 confor some tains unspecified values, producing an instance !+, "-  is sufficient:  !
  +5460 and /   
"  -7482 . We restrict our method to
  , because it involves resetting all MISR stages, which is easier to perform to this state than to any other state. As for a LFSR, the feedback stages of a MISR are described by a feedback polynomial, which defines the   ’s in the definition above. We employ MISRs with primitive feedback polynomials taken from [1]. Now, we summarize our test method: 1. 2. 3. 4.

Reset the MISR (set all stages to 0) Apply an Input Vector (IV) to the MISR’s inputs Let the MISR run for
clock cycles If there are further IVs, go to 1, else the test procedure is finished

4 Generation of Input Vectors

The methods for generation of Input Vectors take as inputs the test set 9:(*)  ;(*) =