Control of a Doubly Fed Induction Generator via an ... - IEEE Xplore

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Control of a Doubly Fed Induction Generator via an Indirect Matrix Converter With Changing DC Voltage Rubén Peña, Member, IEEE, Roberto Cárdenas, Senior Member, IEEE, Eduardo Reyes, Jon Clare, Senior Member, IEEE, and Patrick Wheeler, Member, IEEE

Abstract—This paper presents a control strategy for a doubly fed induction generator (DFIG) using an indirect matrix converter, which consists of an input side matrix converter and an output side voltage source converter (VSC). The capability of the input converter to generate different “virtual dc link” voltage levels is exploited. The commutation of the VSI with reduced voltage is illustrated for operating points where the output voltage demand is low without any deterioration of the current control performance. The proposed method leads to a reduction in the commutation losses in the output converter and reduced common– mode voltage. For the input converter, soft switching commutation is obtained by synchronizing the input and output converter pulsewidth-modulation patterns. This modulation strategy is particularly applicable in DFIG applications because the required rotor voltage decreases when the DFIG speed is close to the synchronous speed. The complete control strategy is experimentally validated using a 2-kW rig. Index Terms—AC machines, machine vector control and space vector pulsewidth modulation (PWM), matrix converter (MC).

I. I NTRODUCTION

I

N RECENT years, there has been increasing interest in the application of direct frequency power converters, such as the matrix converter (MC) and the indirect MC (IMC) [1]–[7], in ac drives. These topologies offer an “all silicon solution” for ac–ac conversion, achieving sinusoidal input and output waveforms along with bidirectional power flow, without using the bulky capacitors which are required in the dc link of rectifier–inverterbased converters. The application of an IMC to control the rotor currents of a doubly fed induction generator (DFIG) in a variable speed generation system was reported in [8] and [9]. The IMC has a similar performance to the standard MC in terms of low distortion in the input currents, bidirectional power flow, and the number of devices. The IMC topology is Manuscript received April 20, 2010; revised September 28, 2010 and December 4, 2010; accepted December 17, 2010. Date of publication January 28, 2011; date of current version August 30, 2011. This work was supported in part by Fondecyt Chile under Contract 1095062 and in part by the Industrial Electronics and Mechatronics Millennium Nucleus P04-048-F. R. Peña is with the Department of Electrical Engineering, University of Concepción, 4074580 Concepción, Chile (e-mail: [email protected]). R. Cárdenas is with the Department of Electrical Engineering, University of Chile, 8370451 Santiago, Chile (e-mail: [email protected]). E. Reyes is with the Department of Electrical Engineering, University of Magallanes, Punta Arenas 113-D, Chile (e-mail: [email protected]). J. Clare and P. Wheeler are with the Power Electronics, Machines and Control Group, Faculty of Engineering, University of Nottingham, NG7 2RD Nottingham, U.K. (e-mail: [email protected]; pat. [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TIE.2011.2109334

Fig. 1.

DFIG controlled via IMC.

similar to a conventional ac/dc/dc converter (see Fig. 1) but without requiring capacitors to support the dc link voltage. The topology consists of a three-to-two input MC and a standard voltage source converter (VSC) at the converter output. The existence of a “virtual dc link” between the two stages offers possibilities, such as multidrive operation as well as the use of different pulsewidth-modulation patterns for the input and output converters [2], [3], to reduce losses and/or input current ripple. Moreover, changing the modulation strategy of the input converter can lead to a reduced “virtual dc link” voltage as reported in [10], where the simulation results shown illustrated that the scheme could lead to a decrease in the commutation losses of the output converter. Experimental results showing the performance of the current control scheme when the “virtual dc link” is reduced have been presented in [11] for a resistive–inductive load. In this paper, a control strategy for a DFIG with an IMC connected between the stator and the rotor, as shown in Fig. 1, is presented. The DFIG rotor current control uses a standard vector control technique [12]. Other control methodologies are also feasible [13], [14]. It is known that the rotor voltage needed to control the rotor current becomes smaller when the machine speed is closer to the synchronous speed. Hence, the reduction in the “virtual dc link” voltage strategy [10], when the demanded output voltage is low, is well suited for DFIG control since frequent operation around the synchronous speed is normal. Preliminary results using this strategy are presented in [15]. Therefore, at any given slip speed, a reduced dc voltage is generated by the input converter so that the required rotor voltage is just produced without using overmodulation. The control strategy of the output stage regulates the modulation index in order to maintain the designed dynamic response of the rotor current controllers. The IMC reference input currents are in phase with the converter input phase voltages for operation at close-to-unity input power factor. A complete procedure is presented in this paper to obtain the duty cycles for the input

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PEÑA et al.: CONTROL OF A DFIG VIA AN INDIRECT MATRIX CONVERTER WITH CHANGING DC VOLTAGE

Fig. 2.

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DC voltage. (a) Maximum dc voltage. (b) Reduced dc voltage.

converter at maximum and reduced dc voltage. The strategy is verified experimentally using a laboratory test rig, and transient and steady-state results are presented. It is shown that the reduced dc voltage not only leads to lower losses but also reduces the common-mode voltage (CMV).

Fig. 3. (a) Schematic for the input stage. (b) Sector and vector definitions. TABLE I I NPUT C URRENTS FOR M AXIMUM DC VOLTAGE

II. M ODULATION S TRATEGY FOR THE IMC The objective of the modulation for the input converter is to obtain a “virtual dc link” voltage which is always positive and to obtain good quality input currents with, usually, a unity displacement factor. Fig. 2 shows two of the possible “virtual dc link” voltage waveforms [10]. Usually, the modulation strategy aims for maximum average voltage [see Fig. 2(a)] [2]–[4], commutating between the largest and second largest positive line input voltages. A reduced “virtual dc link” voltage, such as the one shown in Fig. 2(b) [10], can be produced by commutating between the lowest positive and the second lowest input line voltages. The following sections present the modulation strategies which can be used to produce both “virtual dc link” voltages shown in Fig. 2. First, the procedure to obtain the input converter duty cycles to produce maximum dc voltage is presented. This scheme has been well described in the literature [2], [3], but the details are included in this paper because the procedure can be extended to the case where a reduced “virtual dc link” voltage is produced.

Because the zero vectors are not used, the duty cycles need to obey the following relationship: dab + dac = 1

A. Modulation Strategy of the IMC for Maximum DC Voltage

dab + dac =

ia ; idc

dab = −

ib ; idc

dac = −

ic . idc

(1)

idc = ia .

(2)

ic . ia

(3)

The duty cycles are given by dab = −

Fig. 3(a) shows a schematic for the input converter, considering the power devices as ideal bidirectional switches. Fig. 3(b) shows the sector definitions and commutation sequence to obtain the maximum “virtual dc link” voltage. The reference current vector iref in Sector I is also shown in Fig. 3(b). For example, in Sector I, the top switch of phase “a” remains ON, and the bottom switches of phases “b” and “c” are commutated. Table I shows, in one switching interval, the input current in each sector, depending on the switch combination and the dc current idc . The duty cycle subindex indicates the line voltage reflected into the dc bus. For example, dab means that the voltage vab appears as the instantaneous “virtual dc link” voltage, with the top switch of phase “a” being ON and the bottom switch of phase “b” being ON. From Table I, the Sector I duty cycles are

⇒

ib ; ia

dac = −

For the unity displacement factor, the reference input currents are in phase with the phase voltage templates. Considering va = V cos(θ)

⇒ ia = I cos(θ)

vb = V cos(θ − 120◦ )

⇒ ib = I cos(θ − 120◦ )

vc = V cos(θ + 120◦ )

⇒ ic = I cos(θ + 120◦ ).

(4)

The duty cycles, for Sector I, are given by dab = −

ib cos(θ − 120◦ ) sin(30◦ − θ) ⇒ dab = =− ia cos(θ) cos(θ)

dac = −

ic cos(θ + 120◦ ) sin(150◦ − θ) ⇒ dac = . (5) =− ia cos(θ) cos(θ)

The expressions for the duty cycles d1 and d2 in all sectors are summarized in Table II, including the value of the sector

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TABLE II D UTY C YCLE C ALCULATIONS FOR E ACH S ECTOR

Fig. 4. Sectors for input stage modulation with reduced “virtual dc link” voltage. TABLE IV I NPUT C URRENTS FOR R EDUCED “V IRTUAL DC L INK ” VOLTAGE

TABLE III “V IRTUAL DC L INK ” VOLTAGE FOR E ACH S ECTOR

B. Modulation Strategy for Reduced DC Voltage angle of the reference vector θref . From Table II, the duty cycles, as a function of θref , are d1 = d2 =

sin(60◦ − θref ) dγ = sin(60◦ − θref ) + sin θref dγ + dδ sin(60◦

sin θref dδ = − θref ) + sin θref dγ + dδ

(6)

In order to obtain a lower “virtual dc link” voltage [see Fig. 2(b)], the input converter commutates the input voltages with the scheme shown in Fig. 4. There are, again, six sectors where the commutation of different line input voltages can take place. The input currents as a function of the duty cycles and the dc current, for each sector, are shown in Table IV. Considering Table IV, the duty cycles, for Sector I, are dbc − dab =

with dγ = sin(60◦ − θref )

dδ = sin(θref ).

(7)

The average “virtual dc link” voltage in any modulation period is given by vdc = d1 vline−γ + d2 vline−δ =

dγ dδ · vline−γ + · vline−δ . dγ + dδ dγ + dδ

(8)

Table III shows the line voltages in each sector for the corresponding duty cycle. Considering Table III, (7), and (8), the expression for the average “virtual dc link” voltage in Sector I is √ √ Vline 3 Vlinea 3 = (9) vdc = 2 (dγ + dδ ) 2 cos(θref − 30◦ ) where Vline is the peak input line voltage. The maximum output voltage of the input converter is limited to 0.866 Vline [2], [3], [10].

ib ; idc

dab =

ia ; idc

dbc = −

ic . idc

(10)

Also dab +dbc = 1 ⇒ dbc = 1−dab ⇒ ib = (1 − 2dab )idc .

(11)

Using (10) and (11), the dc current is given by ib = (1 − 2dab )idc ⇒ ib = idc − 2dab idc idc = 2ia + ib = ia − ic = iac .

(12)

From (10), the duty cycles for Sector I are dab =

ia ; iac

dbc = −

ic . iac

(13)

To give the unity displacement factor at the converter input, (13) can be written as dab =

ia cos(θ) ⇒ dab = iac cos(θ) − cos(θ + 120◦ )

dbc = −

ic cos(θ + 120◦ ) . (14) ⇒ dbc = − iac cos(θ) − cos(θ + 120◦ )

PEÑA et al.: CONTROL OF A DFIG VIA AN INDIRECT MATRIX CONVERTER WITH CHANGING DC VOLTAGE

TABLE V D UTY C YCLES AND R EFERENCE V ECTOR A NGLE

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TABLE VI “V IRTUAL DC L INK ” VOLTAGE FOR E ACH S ECTOR

Fig. 5. Voltage space vector and reference output voltage vector.

C. Modulation Strategy for the Output Stage

The duty cycles d1 and d2 for all sectors are summarized in Table V, including the reference vector angle θref . The duty cycles in each sector, as a function of θref , are then given by d1 =

dγ cos(θref ) = cos(θref ) + cos(60◦ − θref ) dγ + dδ

For the output stage, a space vector modulation (SVM) scheme is used to impose the reference rotor voltage vr∗ = |Vr∗ |∠θi in the DFIG. Fig. 5 shows the standard space vectors used in a VSI and the reference output vector. For the output stage, the duty cycles dα and dβ for the active vectors are [3], [4] dα = k · sin(60◦ − θi ),

dβ = k · sin(θi )

(19)

(15)

√ where k = 2Vˆr (dγ + dδ )/ 3Vˆin is the modulation index and Vˆr is the fundamental maximum line output voltage for the output stage. Considering the modulation of the input stage, the duty cycles for the active vectors at the output stage are [3], [4]

(16)

dαγ = dγ · dα ; dβγ = dγ · dβ ; dαδ = dδ · dα ; dβδ = dδ · dβ . (20)

The “virtual dc link” voltage in one modulation period is also given by (8). The corresponding line voltages are shown in Table VI. Considering (8), (16), and Table VI, then, for Sector I

The duty cycle for the zero vectors, d0 , and the corresponding values of d0γi d0δi within each modulation period of the input stage are

dδ cos(60◦ − θref ) = d2 = ◦ cos(θref ) + cos(60 − θref ) dγ + dδ with dγ = cos(θref )

dδ = cos(60◦ − θref ).

√ 3 Vlinea (cos(θ) · vab − cos(θ + 120◦ ) · vbc ) vdc = . = dγ + dδ 2 (dγ + dδ ) (17) Using (16) and (17), the average dc voltage is vdc

√ 3 Vlinea Vlinea 1 √ . = = 2 3 cos(θref − 30◦ ) 2 cos(θref − 30◦ )

(18)

The maximum output voltage at the inverting stage is limited to 50% of Vline [10].

d0 = 1 − (dγ + dδ ) · (dα + dβ ) d0γ =

dγ d0 (dγ + dδ )

d0δ =

dδ d0 . (dγ + dδ )

(21)

The standard soft switching operation of the input converter is achieved [2] by synchronizing the commutation of the input MC to the time when zero voltage vectors are applied by the output converter, minimizing the input converter commutation losses (see Fig. 6, where ts is the switching period and tcom is the commutation time of the input converter).

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magnitude of the load phase current. The conduction power losses in the IGBT and diode, considering n samples per period, are given by Pcond−IGBT =

1 vIGBT iIGBT n 1

Pcond−Diode =

1 vDiode iDiode . n 1

n

n

Fig. 6. Switching sequence for soft switching of the input converter.

III. L OSS C ALCULATIONS FOR THE VSI

The total losses are given by

Power losses are evaluated by employing a standard and well-accepted approach [16] which uses simulated waveform data in conjunction with the measured device characteristics from the manufacturer’s data sheet. Following [16], a procedure is presented in this section to evaluate the VSI losses when operating at different “virtual dc link” voltages. In order to assess the VSI losses, it is necessary to know the load current and the voltage in one of the VSI switches together with the switch state and switch loss information contained in the semiconductor data sheet [17]. The insulated-gate bipolar transistor (IGBT) turn-on energy losses Ecom−ON are given by Ecom−ON = (EON−nom +Err−nom )

vcom_ON icom_ON Vnom Inom

(22)

where Vnom and Inom denote the semiconductor nominal voltage and current, respectively; EON−nom is the nominal energy loss in the IGBT turning ON; Err−nom is the recovery energy loss due to the opposite diode; and vcom−ON and icon−ON denote the turn-on IGBT voltage and current, respectively. The turnoff energy loss Ecom−OFF is given by Ecom−OFF = EOFF−nom

vcom_OFF icom_OFF Vnom Inom

(23)

where EON−nom is the nominal energy loss when the device is turned OFF and vcom−OFF and icon−OFF denote the turnoff voltage and current, respectively. The total switching power loss Psw−loss for the period, considering six devices and that the nominal energy loss is in millijoules [17], is given by Psw−loss =

N 6 1 (Ecom−ON + Ecom−OFF )i 1000 T 1

(24)

where N is the number of commutations per output current period and T is the output current period. For the conduction losses, linear approximations of the voltage versus current characteristics for the diode and IGBT are used. The conduction voltage drops in the IGBT and diode are given by vIGBT = aIGBT + bIGBT iIGBT vDiode = aDiode + bDiode iDiode

(26)

(25)

where vIGBT , iIGBT , vDiode , and iDiode denote the voltage and current through the IGBT and diode, respectively, during the ON -state and aIGBT , bIGBT , aD , and bD are obtained from the device data sheet (see the Appendix). The current through either the transistor or the diode is obtained from the direction and

Ptotal−loss = Psw−loss + Pcond−IGBT + Pcond−Diode .

(27)

IV. V ECTOR C ONTROL OF THE DFIG The DFIG machine equations in a d−q synchronous rotating frame are [12] ⎡ ⎤ ⎡ ⎤⎡ ⎤ λds 0 Lm 0 ids Ls 0 Lm ⎥ ⎢ iqs ⎥ Ls ⎢ λqs ⎥ ⎢ 0 (28) ⎣ ⎦=⎣ ⎦⎣ ⎦ λdr Lm 0 Lr 0 idr λqr 0 Lr iqr 0 Lm







d λds Rs 0 ids vds = + vqs iqs 0 Rs dt λqs



0 −ωe λds (29) + ωe 0 λqs







d λdr Rr 0 idr vdr = + vqr iqr 0 Rr dt λqr



0 −ωslip λdr (30) + ωslip 0 λqr p (31) Te = 3 Lm (iqs idr − ids iqr ) 2 where λs = Lm ims is the stator flux; λr is the rotor flux; Ls , Lm , and Lr are the stator, magnetizing, and rotor inductances, respectively; vs and is are the stator voltages and currents; vr and ir are the rotor voltages and currents; Rr and Rs are the rotor and stator resistances; ωe and ωr are the synchronous and rotating angular frequencies, respectively; ωslip = ωe − ωr is the slip frequency; ims is the magnetizing current; Te is the electrical torque; and p is the number of poles. In (28)–(31), the subscripts r and s denote the rotor and stator quantities, respectively. The subscripts d and q denote the direct and quadrature components referred to the synchronous rotating frame. The factor 3 in (31) is due to the scaling used in the transformations, so the voltages and currents in the d–q frame represent the phase rms values in the steady state. Field orientation, for transforming the machine variables, uses the slip angle derived from θslip = θe − θr

(32)

where θr is the rotor position. For the experimental results presented in this paper, a speed encoder has been used. The reference frame is oriented along the stator flux vector. The

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Fig. 8. Laboratory-based experimental setup.

Fig. 7.

Schematic for vector control of the DFIG.

position of the stator flux vector (θe ) is obtained from the stator flux α–β components as θe = tan−1



λβs λαs

.

(33)

The α–β components of the stator flux can be calculated from the stator voltages and currents as

λαs =

For the stator flux orientation, the electrical torque is given by Te = 3

p L2m ims iqr = kt iqr 2 Ls

(36)

where kt = 1.5pL2m ims /Ls is the torque constant. More details on the vector control of DFIGs can be found in [9] and [12].

(vαs − Rs iαs )dt V. E XPERIMENTAL S ETUP

λβs =

The magnitude and position of the reference rotor vector voltage are given by   2 ∗ )2 + v ∗ |vr | = (vαr βr  ∗ v βr θ = tan−1 . (35) ∗ vαr

(vβs − Rs iβs )dt.

(34)

In the experimental implementation of (34), a bandpass filter (BPF) is used as a modified integrator to block the dc component of the measured voltages and currents. The BPF is designed with cutoff frequencies of 0.1 and 1 Hz. Therefore, because v s and is are 50-Hz signals, the performance deterioration from the integral action is negligible. The control schematic for the DFIG is shown in Fig. 7, and proportional–integral current controllers are used to regulate the reference rotor currents in the d–q frame. Compensation terms are added to the output of the current controllers to simplify the design procedure. The outputs of the controllers generate the corresponding reference rotor voltage for the machine. An SVM algorithm is used to impose the reference rotor voltages in the output stage. In Fig. 7, E is the converter dc voltage, σ = 1 − L2m /Ls Lr is the total leakage coefficient, the superscript “∗” denotes a demand current, and the subscripts α–β denote the quantities referred to the stationary stator frame. The blocks labeled e−jθslip and ejθslip represent the transformations from α–β to d–q coordinates and vice versa.

The proposed strategy has been tested using the experimental system shown in Fig. 8. A four-pole DFIG driven mechanically by an ac drive is used. The DFIG is rated at 2 kW with a stator voltage of 140 V. Unless otherwise stated, the stator voltage is fixed at 140 V for the tests. A DSP board, based on the TMS320C6713 processor, is used as the control platform. Several tasks are implemented in the DSP, including the vector control strategy, the control of the ac drive, and the calculation of the switching times for the input and output converter stages. Voltage and current transducers are used to measure the stator voltages and stator/rotor currents. The rotor position is measured with a 10 000-ppr encoder. Sensorless control is also feasible [22], [23]. An interface board, based on a fieldprogrammable gate array, is used to implement the space vector modulation and data acquisition. Communication between the DSP and a PC is carried out using a DSK6713HPI daughter card. The input converter uses six SK60GM123 modules, and the output stage uses a SK35GD126 module. A sampling frequency of 10 kHz is used for the voltages, currents, and position signals. Voltages and currents are scaled when transformed to the d–q synchronous frame, so they represent the phase rms values in the steady state.

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Fig. 9. DC voltage transition between the two input converter modulation strategies.

The interaction between the second-order supply filter (see Fig. 1) and the IMC can lead to oscillations and even instability when the output power is increased [18], [19]. The method proposed in [20] to increase the stability of direct MCs is used in this paper. This method consists of filtering the measured input voltage signals using a filter in the synchronous reference frame, tuned to eliminate the high-frequency components of the input voltage [9], [21].

Fig. 10.

Rotor current regulation at variable speed and changing dc voltage.

VI. R ESULTS In this section, several experimental results are shown to illustrate the performance of the control strategy. Fig. 9 shows the “virtual dc link” voltage when the input converter modulation strategy is altered while the drive operates at constant speed (1000 r/min). Fig. 9(a) shows the transition from maximum to reduced “virtual dc link” voltage. Initially, the modulation provides maximum dc voltage, and at t ≈ 23 ms, the modulation strategy is changed to obtain a lower voltage. The opposite situation is depicted in Fig. 9(b), where the modulation strategy to obtain a reduced voltage is initially used. At t ≈ 19 ms, the modulation strategy is changed, and maximum voltage is attained. Fig. 10 shows the regulation of the rotor currents when the modulation of the input converter and the corresponding “virtual dc link” voltage are changed when the drive is operating close to the synchronous speed. For this test, the rotational speed is initially 1350 r/min, and it is increased to 1650 r/min [see Fig. 10(a)]. The average “virtual dc link” voltage is shown in Fig. 10(b). The average “virtual dc link” voltage is obtained from (8), using measurements of the input voltages and either the duty cycle expressions in Table II (maximum voltage) or those in Table V (reduced voltage). Initially, the modulation strategy of the input converter aims for maximum dc voltage. The required rotor voltage needed to impose the rotor current depends on the stator voltage, the rotational speed, the stator-torotor turns-ratio, and the voltage drop in the series impedances.

Fig. 11. Rotor current controller performance with different “virtual dc link” voltages.

This, together with a safety factor, is taken into account to decide when the strategy switches from high to low “virtual dc” voltage and vice versa. In this paper, in order to illustrate the performance of the current controller, the modulation strategy is changed and the dc voltage is reduced when the speed is about 1450 r/min (s = 3.3%). The rotor current is regulated at 5.5 A [see Fig. 10(c)]. The modulation strategy of the input converter is changed back to produce the maximum voltage when the speed is about 1550 r/min (s = −3.3%). As can be observed in Fig. 10, the change in the modulation strategy does not have any detrimental impact on the tracking of the rotor currents (for this test, the line voltage is 110 V). Fig. 11 shows the performance of the rotor current controllers to a step change in the q-axis rotor current reference, with the d-axis rotor current reference set to zero. When the q-axis rotor current is 3 A, a reduced “virtual dc link” voltage is used, whereas when the rotor current is 5 A, the modulation strategy for the input converter generates the maximum voltage. The speed of the machine is regulated at 1300 r/min. Good results are observed, and the change in “virtual dc link” voltage does not deteriorate the performance of the current controllers. Fig. 12 shows the average “virtual dc link” voltage for the rotor current step responses shown in Fig. 11. Fig. 13 shows the IMC input current and the equivalent phase to neutral voltage when the q-axis rotor current is changed from

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Fig. 12. Average “virtual dc link” voltage for the test conditions of Fig. 11.

Fig. 14. Input converter current for two “virtual dc link” voltage modulation strategies.

Fig. 13. IMC input current and phase voltage for both input converter modulation strategies.

3 to 5 A [see Fig. 11(a)] and from 5 to 3 A [see Fig. 11(b)]. For the low value of the q-axis rotor current, the modulation strategy to obtain a reduced dc voltage is used, and when the rotor current is increased, the modulation strategy is changed so that maximum “virtual dc link” voltage is obtained. In both conditions, the input converter operates with a displacement factor close to unity. The slight phase shift between the voltage and the current is due to the converter input filter. The speed of the generator in this test is regulated at 1300 r/min (fundamental output frequency = 6.66 Hz). Fig. 14 shows the IMC input current when the rotor current is regulated at 7.5 A, and the modulation strategy is changed from reduced to maximum “virtual dc link” voltage. For reduced “virtual dc link” voltage operation, the input current ripple is slightly higher than the current ripple when the maximum “virtual dc link” voltage is generated [10], which is a fact to take into account when designing the input filter. In order to demonstrate the increase in the input current ripple, for the reduced “virtual dc link” case, a model of the system was implemented using Matlab/Simulink. From this model, the switching functions for one leg of the input converter are obtained. Fig. 15 shows the switching functions for the top and bottom switches, Sap, and San for one leg of the input converter [see Fig. 3(a)]. The phase “a” input current can be obtained as (Sap-San) times the dc current. Fig. 16 shows the input current for both modulation strategies. A comparison of

Fig. 15. Switching functions for one leg of the input converter.

Fig. 16. Unfiltered input current for both strategies.

Fig. 16(c) and (d) (one cycle of the input current) illustrates the increase in the ripple of the input current. Fig. 17 shows the modulation indexes for both “virtual dc link” voltage modulation strategies when the speed varies

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Fig. 17. Modulation index for both modulation strategies.

from below to above the synchronous speed. Fig. 17(a) shows the modulation index when the voltage is reduced near the synchronous speed, whereas Fig. 17(b) shows the modulation index when maximum voltage is produced by the IMC. The reduction in the “virtual dc link” voltage takes place when the speed is above 1300 r/min and below 1700 r/min (with a slip of ≈ ±13.3%). In both modulation strategies, the reference voltage, at a given speed, is the same. In order to evaluate the advantages of the strategy in terms of CMV and losses, the system model implemented in Matlab/Simulink was used. Fig. 18 shows the spectrum of the CMV for a range of modulation indexes (from 10% to 50%) for a 10-Hz fundamental output frequency for both modulation strategies. The lower dc voltage modulation strategy shows a lower harmonic amplitude [comparing Fig. 18(a) and (b)], and this is due to two main reasons. First, for the lower dc voltage modulation strategy, the amplitude of the voltages making up the vectors is lower. Second, the common mode is usually highest at the zero modulation index because, at that point, all the outputs are almost identical. As the modulation index increases, the CMV harmonics reduce as the differential-mode ones increase due to the modulation. Therefore, it might be expected that the strategy that runs at a higher modulation index, i.e., the reduced “virtual dc link” voltage, will have a lesser CMV. These results are similar for other output frequencies ranging from 0 to 50 Hz. For the converter losses, Fig. 19 shows the output current and the voltage in one IGBT of the VSI for both modulation strategies. Using the procedure described in Section III, the estimated losses of the converter for s = −0.3, a 140-V supply voltage, and a 8-A rotor current are 25% lower if a reduced “virtual dc link” voltage is produced. The same technique will also have similar benefits for higher power applications. In order to evaluate the impact of the proposed technique on a full-size wind turbine, an 850-kW design is considered with a 1:3 turn ratio DFIG and a rated speed at slip = −25%. A 250-kVA rotor converter will be appropriate for this case. For the resulting voltage and current levels, the SEMiX904GB126HDs IGBT module is a suitable choice, operating a switching frequency of 6 kHz [17]. The

Fig. 18.

CMV spectrum. (a) High dc voltage. (b) Lower dc voltage.

reduced “virtual dc link” voltage strategy can be used when |slip| < 15%. The analysis and methodology of Section III yield a switching loss reduction estimate of 40% and an overall loss reduction estimate of 20%. Additionally, the input filter design will be different for this power level, but the advantages of size and weight will not be lost. Moreover, the advantages of the reduced “virtual dc link” strategy regarding the CMV will be maintained. VII. C ONCLUSION A control strategy for a DFIG using an IMC has been shown. The modulation of the input converter has been modified in order to reduce the voltage of the “virtual dc link” when the required rotor voltage is low, i.e., when the machine is running near the synchronous speed. The strategy has been implemented and experimentally verified using a 2-kW laboratory-based rig. It has been shown that the dynamics and regulation of the rotor current control are maintained regardless of the modulation strategy used for the input converter. The results have included step demand rotor current changes at fixed and variable speed as well as operation below and above the synchronous speed. A procedure has been presented to estimate the losses in the output converter for the modulation strategies used. For the cases considered, using low and medium output power IGBT modules, an overall loss reduction estimate of more than 20% has been obtained, with the reduction in switching losses as the most significant factor. Another advantage in using a reduced

PEÑA et al.: CONTROL OF A DFIG VIA AN INDIRECT MATRIX CONVERTER WITH CHANGING DC VOLTAGE

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Fig. 19. (a) and (b) Output current and IGBT voltage for maximum dc voltage. (c) and (d) Output current and IGBT voltage for reduced dc voltage. TABLE VII S PECIFICATION OF THE DFIG

TABLE VIII S PECIFICATION OF THE IMC I NPUT F ILTER

“virtual dc link” voltage refers to the CMV. It has been shown that operation with this strategy leads to a reduction in the CMV compared with the standard modulation approach. A PPENDIX S YSTEM PARAMETERS The specification of the DFIG is shown in Table VII. The specification of the IMC input filter is given in Table VIII. Current controllers: 350 rad/s with a 0.8 damping factor. The cut-off frequency of filter in the synchronous reference frame is 25 Hz. ACKNOWLEDGMENT The authors would like to thank Dr. L. Empringham and Dr. L. de Lillo of the Power Electronics, Machines and Control Group, University of Nottingham, U.K., for all their technical advice during the implementation of the experimental rig used in this paper.

[1] P. Wheeler, J. Rodriguez, J. Clare, L. Empringham, and A. Weinstein, “Matrix converters: A technology review,” IEEE Trans. Ind. Electron., vol. 49, no. 2, pp. 276–288, Apr. 2002. [2] L. Wei and T. A. Lipo, “A novel matrix converter topology with simple commutation,” in Conf. Rec. IEEE IAS Annu. Meeting, 2001, vol. 3, pp. 1749–1754. [3] C. Klumpner and F. Blaabjerg, “A new cost-effective multi-drive solution based on a two-stage direct power electronics conversion topology,” in Conf. Rec. IEEE IAS Annu. Meeting, 2002, vol. 1, pp. 444–452. [4] C. Klumpner and F. Blaabjerg, “Modulation method for a multiple drive system based on a two-stage direct power conversion topology with reduced input current ripple,” IEEE Trans. Power Electron., vol. 20, no. 4, pp. 922–929, Jul. 2005. [5] P. Correa, J. Rodriguez, M. Rivera, J. R. Espinoza, and J. W. Kolar, “Predictive control of an indirect matrix converter,” IEEE Trans. Ind. Electron., vol. 56, no. 6, pp. 1847–1853, Jun. 2009. [6] R. Cárdenas, R. Peña, J. Clare, and P. Wheeler, “Control of the reactive power supplied by a WECS based on an induction generator fed by a matrix converter,” IEEE Trans. Ind. Electron., vol. 56, no. 2, pp. 429–438, Feb. 2009. [7] D. Casadei, G. Serra, A. Tani, and L. Zarri, “Optimal use of zero vectors for minimizing the output current distortion in matrix converters,” IEEE Trans. Ind. Electron., vol. 56, no. 2, pp. 326–336, Feb. 2009. [8] E. Reyes, R. Pena, R. Cardenas, J. Clare, and P. Wheeler, “Control of a doubly-fed induction generator via a direct two-stage power converter,” in Proc. IET PEMD, York, 2008, pp. 280–285. [9] R. Pena, R. Cardenas, E. Reyes, J. Clare, and P. Wheeler, “A topology for multiple generation system with doubly fed induction machines and indirect matrix converter,” IEEE Trans. Ind. Electron., vol. 56, no. 10, pp. 4181–4193, Oct. 2009. [10] J. W. Kolar and F. Schafmeister, “Novel modulation schemes minimizing the switching losses of sparse matrix converters,” in Proc. 29th Annu. Conf. IEEE IECON, Roanoke, VA, 2003, vol. 3, pp. 2085–2090. [11] R. Pena, R. Cardenas, E. Reyes, J. Clare, and P. Wheeler, “Control strategy of an indirect matrix converter with modifying dc voltage,” in Proc. 13th Eur. Conf. Power Electron. Appl. EPE, Barcelona, Spain, 2009, pp. 1–8. [12] R. Peña, J. Clare, and G. Asher, “Doubly-fed induction generators using back-to-back PWM converters and its applications to variable-speed wind-energy generation,” Proc. Inst. Elect. Eng.–Elect. Power Appl., vol. 143, pp. 231–241, May 1996. [13] J. Arbi, M. J.-B. Ghorbal, I. Slama-Belkhodja, and L. Charaabi, “Direct virtual torque control for doubly fed induction generator grid connection,” IEEE Trans. Ind. Electron., vol. 56, no. 10, pp. 4163–4173, Oct. 2009. [14] L. Xu, D. Zhi, and B. W. Williams, “Predictive current control of doubly fed induction generators,” IEEE Ind. Electron., vol. 56, no. 10, pp. 4143– 4153, Oct. 2009. [15] E. Reyes, R. Pena, R. Cardenas, J. Clare, and P. Wheeler, “Control of a doubly-fed induction generator with an indirect matrix converter with changing dc voltage,” in Proc. IEEE ISIE, Bari, Italy, Jul. 2010, pp. 1230– 1235. [16] M. Apap, J. Clare, P. Wheeler, M. Bland, and K. Bradley, “Comparison of losses in matrix converters and voltage source inverters,” in Proc. IEE Semin. Matrix Converter (Digest No 2003/10100), 2003, pp. 4/1–4/6. [17] Semikron datasheet. [Online]. Available: http://www.semikron.com [18] H. Mosskull, J. Galic, and B. Wahlberg, “Stabilization of induction motor drives with poorly damped input filters,” IEEE Trans. Ind. Electron., vol. 54, no. 5, pp. 2724–2734, Aug. 2007. [19] C. Byungcho, K. Dongsoo, L. Donggyu, C. Seungwon, and S. Jian, “Analysis of input filter interactions in switching power converters,” IEEE Trans. Power Electron., vol. 22, no. 2, pp. 452–460, Mar. 2007. [20] D. Casadei, J. Clare, L. Empringham, G. Serra, A. Tani, A. Trentin, P. Wheeler, and L. Zarri, “Large-signal model for the stability analysis of matrix converters,” IEEE Trans. Ind. Electron., vol. 54, no. 2, pp. 939– 950, Apr. 2007. [21] R. Cardenas, R. Pena, G. Tobar, E. Reyes, J. Clare, P. Wheeler, and G. Asher, “Stability analysis of a wind energy conversion system based on a doubly fed induction generator fed by a matrix converter,” IEEE Trans. Ind. Electron., vol. 56, no. 10, pp. 4194–4206, Oct. 2009. [22] D. G. Forchetti, G. O. Garcia, and M. I. Valla, “Adaptive observer for sensorless control of stand-alone doubly fed induction generator,” IEEE Trans. Ind. Electron., vol. 56, no. 10, pp. 4174–4180, Oct. 2009. [23] R. Cárdenas, R. Peña, J. Clare, G. Asher, and J. Proboste, “MRAS observers for sensorless control of doubly-fed induction generators,” IEEE Trans. Power Electron., vol. 23, no. 3, pp. 1075–1084, May 2008.

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Rubén Peña (S’95–M’97) was born in Coronel, Chile. He received the B.S. degree in electrical engineering from the University of Concepción, Concepción, Chile, in 1984, and the M.Sc. and Ph.D. degrees from the University of Nottingham, Nottingham, U.K., in 1992 and 1996, respectively. From 1985 to 2008, he was a Lecturer with the University of Magallanes, Punta Arenas, Chile. He is currently with the Department of Electrical Engineering, University of Concepción. His main interests are in the control of power electronics converters, ac drives, and renewable energy systems.

Roberto Cárdenas (S’95–M’97–SM’07) was born in Punta Arenas, Chile. He received the B.S. degree from the University of Magallanes, Punta Arenas, in 1988, and the M.Sc. and Ph.D. degrees from the University of Nottingham, Nottingham, U.K., in 1992 and 1996, respectively. From 1989 to 1991 and from 1996 to 2008, he was a Lecturer with the University of Magallanes. From 1991 to 1996, he was with the Power Electronics, Machines and Control Group, University of Nottingham. He is currently a Professor of power electronics and drives with the Department of Electrical Engineering, University of Chile, Santiago, Chile. His main interests are in the control of electrical machines, variable speed drives, and renewable energy systems. Dr. Cárdenas was the recipient of the Best Paper Award from the IEEE T RANSACTIONS ON I NDUSTRIAL E LECTRONICS in 2005 and the “Ramon Salas Edward” Award for research excellence from the Chilean Institute of Engineers in 2009.

Eduardo Reyes was born in Valparaiso, Chile. He received the B.S. and M.Sc. degrees in electrical engineering from the University of Magallanes, Punta Arenas, Chile, in 2007 and 2010, respectively. He is currently working toward the Ph.D. degree in the Power Electronics, Machines and Control Group, University of Nottingham, Nottingham, U.K. From 2007 to 2009, he was a Research Assistant with the Department of Electrical Engineering, University of Magallanes. His main interests are in the control of power electronics converters and ac drives.

Jon Clare (M’90–SM’04) was born in Bristol, U.K. He received the B.Sc. and Ph.D. degrees in electrical engineering from the University of Bristol, Bristol. From 1984 to 1990, he was a Research Assistant and Lecturer with the University of Bristol, where he was involved in teaching and research in power electronic systems. Since 1990, he has been with the Power Electronics, Machines and Control Group, University of Nottingham, Nottingham, U.K., where he is currently a Professor in Power Electronics. His research interests are power electronic converters and modulation strategies, variable speed drive systems, and electromagnetic compatibility. Dr. Clare is a member of the Institution of Engineering Technology.

Patrick Wheeler (M’00) received the B.Eng. (Hons.) degree in electrical engineering and the Ph.D. degree, for work on matrix converters, from the University of Bristol, Bristol, U.K., in 1990 and 1994, respectively. In 1993, he was with the University of Nottingham, Nottingham, U.K., where he was a Research Assistant in the Department of Electrical and Electronic Engineering. He is currently with the Power Electronics, Machines and Control Group, University of Nottingham, where he was appointed Lecturer in 1996, subsequently Senior Lecturer in 2002, and Professor in Power Electronic Systems in 2007. His research interests are in power conversion, Energy and More Electric Aircraft technology. Dr. Wheeler is a member of the Institution of Engineering Technology.