Control Strategy for Input-Series–Output-Parallel High-Frequency AC ...

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 59, NO. 11, NOVEMBER 2012

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Control Strategy for Input-Series–Output-Parallel High-Frequency AC Link Inverters Deshang Sha, Member, IEEE, Kai Deng, Zhiqiang Guo, Student Member, IEEE, and XiaoZhong Liao, Member, IEEE

Abstract—This paper presents a control strategy for inputseries–output-parallel (ISOP) modular inverters. Each module is a high-frequency (HF) ac link (HFACL) inverter composed of an HF inverter, an HF transformer, and a cycloconverter. A PWM sequence generation based on DSP control is given, with which the circulating currents among all the constituent modules can be avoided automatically. To achieve input voltage sharing (IVS) and output current sharing (OCS) among the constituent inverter modules, a stable OCS scheme, which consists of one common output voltage regulation (OVR) loop and individual inner currents loops, is proposed. The OVR loop provides a common reference for all individual inner current loops, in which the current feedback for an individual module is the sum of all the other output currents instead of its own. The compensator designs of the OVR loop and individual inner current loops are also presented. With this control strategy, excellent IVS and OCS can be obtained. The effectiveness of the proposed control strategy is verified using the simulation and experimental results of a 1100-VA ISOP two-HFACL inverter system. Index Terms—Current sharing, high-frequency (HF) link inverter, input-series–output-parallel (ISOP), voltage sharing.

I. I NTRODUCTION

T

HE following can be the solutions for designing power converters for high-input dc voltage applications with low-voltage rating switches: the series connection of power switches [1], the multilevel converter using flying capacitors or diode clamping [2]–[4], and the input series-connected power converter modules [5]–[14]. Compared with the first two power structures, the last configuration possesses the following distinct features: standardized modular manufacturing leading to reduction in cost and time, flexibility of power extension to meet varying input–output-voltage specifications, and most importantly, the redundant operation capability and, hence, improvement of the overall reliability. In particular, the inputseries-connected converters can be divided into two categories: One is the input-series–output-parallel (ISOP) connection for low-voltage output applications, and the other is the inputseries–output-series (ISOS) used in high-voltage output appliManuscript received March 24, 2011; revised June 13, 2011 and September 19, 2011; accepted October 20, 2011. Date of publication November 2, 2011; date of current version June 19, 2012. This work was supported in part by the National Natural Science Foundation of China under Grant 50807005, by the Excellent Young Scholars Research Fund of Beijing Institute of Technology under Grant 2010YC0604, and by the Key Laboratory of Complex System Intelligent Control and Decision (Beijing Institute of Technology), Ministry of Education. The authors are with the School of Automation, Beijing Institute of Technology, Beijing 100081, China (e-mail: [email protected]; bitdengkai@ 163.com; [email protected]; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TIE.2011.2174538

cations. Apparently, the ISOP connection has been used more widely, and therefore, extensive research works have been done. One basic control objective for an ISOP system is to achieve power sharing among the constituent modules, which also implies input voltage sharing (IVS) and output current sharing (OCS). In terms of the modular configuration with a dc voltage input, the ISOP system can be classified into two types, dc–dc converters and dc–ac inverters. Indeed, ISOP dc–dc converters have been discussed more extensively. To achieve IVS and OCS among the constituent dc–dc modules, several control schemes have been proposed. A common duty ratio control results in a stable operation [5], but excellent IVS and OCS can only be achieved for modules with identical parameters. Charge control with input-voltage feedforward is applicable for two ISOPconnected converters [6]. Nevertheless, both individual input currents and voltages have to be sensed. A master/slave control scheme with input-current feedforward can achieve IVS, but with the control technique, the system may fail once the master module malfunctions [7]. A form of sensorless current mode control can achieve power sharing, but some component tolerances such as losses in transformers and inductors lead to a slight distortion of the sharing [8]. A double-loop control implemented by one common output voltage regulation (OVR) loop and individual IVS loops, such as the uniform input-voltage distribution [9], the decoupling IVS control scheme [10], [11], and the general control considerations [12], can achieve excellent IVS for this configuration. However, individual high input voltages have to be sensed with high-voltage rating voltage sensors. Moreover, the dynamic response may be degraded for lacking inner current loops. A three-loop control scheme is implemented by sensing both individual input voltages and output currents [13], but from the viewpoint of power balance, achieving IVS means automatically obtaining OCS. On the other hand, once OCS is achieved, IVS can also be ensured. Therefore, the implementation of the control circuit sensing both individual and output currents is complex. Cross-feedback OCS control, composed of a common OVR loop and individual inner current loops, provides a stable OCS control strategy for ISOP converters without employing any IVS loops [14], [15]. With this scheme, perfect IVS and OCS can be achieved not only under steady state but also under dynamic process even in the face of the turns-ratio mismatch. Although an ISOP dc–ac inverter system, as shown in Fig. 1, has the same circuit structure with an ISOP dc–dc converter system, it has some special and distinctive features: 1) ease of generating circulating currents among the constituent modules; 2) more power conversion stages required; and 3) adaptation to different loads needed.

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Fig. 1. ISOP inverter system.

For output-paralleled dc–dc modules, the problem of circulating currents is avoided by using the unidirectional power flow capability of rectifying diodes. However, for output-paralleled modular inverters, individual output voltages should have the same frequency, phase, amplitude, and even carrier waveform [16]. To suppress circulating currents, many control strategies have been proposed [17]–[19]; otherwise, excellent OCS cannot be achieved or even the system may fail. The constituent galvanic isolated modular inverter has more power conversion stages. Generally, a high-frequency (HF) isolated inverter consisting of an isolated dc–dc converter and a dc–ac inverter is widely used for its advantages compared with the lowfrequency transformer isolated inverter [20]–[25]. However, separated controllers are needed for the dc–dc converter and the dc–ac inverter, and thus, the control system design is more complicated than that for the HF isolated dc–dc converter. Furthermore, the input-series-connected inverter system should be more adaptive to many different loads such as capacitive, inductive, or even nonlinear loads, and hence, the influence of reactive power, as well as the active power, on IVS and OCS should be investigated. Regarding these special features owned by modular dc–ac inverter modules, generally, the aforementioned control strategies applied to the input-series-connected dc–dc modules cannot be directly applied to the input-series-connected dc–ac inverter modules. To achieve power balance for ISOP or ISOS inverter modules, a three-loop control strategy consisting of a common OVR loop, IVS loops, and individual inner current loops is presented and proven effective [22]–[25], with which both individual input voltages and output currents have to be sensed at the same time. Moreover, although the control structure is similar to that for modular dc–dc converters, the output of the OVR loop for inverter modules is a ac value, whereas that of the dc–dc modules is a dc value. Hence, the output of the OVR loop has to be multiplied with individual outputs of IVS loops, working as references for individual inner current loops. In addition, each constituent module is composed of an HF isolated dc–dc converter and a dc–ac inverter. Each stage needs a separated control system, complicating the whole control system design. Although IVS and individual inner current loops are used for ISOP inverters, circulating currents with low-frequency rippling cannot be successfully suppressed [22], [23]. In addition, the performance of nonresistive loads is not discussed. The relationship between IVS and OCS is discussed

only according to the active power influence, and the role of reactive power is not mentioned. Although experimental results due to different loads are made based on the ISOS connection [24], [25], the role of reactive power is still not discussed due to the unidirectional power flow capability of each constituent inverter modules. The HF ac link inverter composed of an HF inverter, an HF transformer, and a cycloconverter has attributes such as the elimination of bulky capacitors and bidirectional power flow capability. Hence, the conversion efficiency and reliability can be improved [26], [27]. Additionally, the control of the HF inverter and the cycloconverter can be implemented by only one control system, leading to the simplification of the control design. A universal grid-connected fuel-cell inverter is composed of the system integration of HFACL inverters, but the configuration is not truly modular because both the two outputside cycloconverters share the same full-bridge inverter through their individual HF transformer primary sides [27]. A two-loop control average current controller is widely used and is effective to meet the static and dynamic performances of HF isolated dc–dc converters even for current-fed dc–dc converters [28]. In this paper, a stable OCS control scheme composed of only two loops for ISOP inverters is proposed without employing any IVS control loops. Therefore, the sensing of high input voltages is avoided and the control design can be simplified and the cost can also be reduced. Moreover, each module is composed of an HF isolated HF inverter, an HF transformer, and a cycloconverter, which is suitable for different loads. In addition, a scheme for generating the PWM sequence for all switches is presented, with which circulating currents among the modules can be avoided in spite of load characteristics. This paper is organized as follows. The circuit configuration and PWM generation is introduced in Section II. The proposed control strategy is given, and the loop gain design for a twomodule system is given in Section III. In Section IV, the simulation and experiments are made to verify the effectiveness of the proposed control strategy. Section V gives the conclusion. II. C IRCUIT C ONFIGURATION AND PWM G ENERATION The proposed ISOP-connected n-module HFACL inverter system is shown in Fig. 2. Each inverter module in this figure consists of a full-bridge inverter, a center-tapped HF transformer, a cycloconverter, and an output low-pass LC filter. The HF transformer performs the galvanic isolation and voltage gains conversion between the input and output. Each switch of the cycloconverter is composed of two N-channel MOSFETs connected to a common source. In this figure, each diode in parallel with a MOSFET is the parasitic body diode of their respective switch. To avoid the generation of the circulating currents among the inverters, the generation of the gating signals for the cycloconverter switches is determined by the individual output inductor current. This can be explained by taking module #1 as an example. When iLf1 > 0, Q13 and Q14 are always off while the output inductor current iLf1 flows through their antiparallel diodes D13 and D14 , respectively. Q11 and Q12 are

SHA et al.: CONTROL STRATEGY FOR ISOP HFACL INVERTERS

Fig. 2.

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Configuration of ISOP-connected n-HFACL inverters.

Fig. 4. Gate-signal generation for module #1.

Fig. 3.

Equivalent circuit configuration when iLf1 > 0.

complementarily turned on and off with HF. When iLf1 < 0, Q11 and Q12 are always off while the output inductor current iLf1 flows through their antiparallel D11 and D12 diodes, respectively. Q13 and Q14 are turned on and off with HF. For the other modules, the cycloconverter switches in the same position have the same gating signals, i.e., Q11 . . . Qn1 are gated on and off simultaneously, which also applies for Q12 . . . Qn2 , Q13 . . . Qn3 , and Q14 . . . Qn4 , respectively. Assuming the output inductor current iLf1 is sensed to achieve zero crossing judgment, Fig. 2 shows the equivalent circuit configuration when iLf1 > 0. As seen from Fig. 3, when iLf1 > 0, all the output inductor currents have to flow to the load in the same direction due to the reverse blocking function of body diodes D13 . . . Dn3 and D14 . . . Dn4 . Therefore, the circulating currents among all the constituent inverter modules can be automatically avoided without employing any circulating current suppression control loops. When iLf1 < 0, the switches of Q11 . . . Qn1 and Q12 . . . Qn2 are always turned off and the individual output currents flow through their body diodes instead. Obviously, the circulating currents among all the inverter modules can also

be automatically avoided. Hence, at any time, no circulating currents can be generated at all with the method. For the ISOP inverters, in fact, an arbitrary output inductor current can be used to achieve polarity judgment. Assuming the output inductor current of module #1 is used, the generation for the cycloconverter switches of all the other modules depends on iLf1 . The schematic of gate-signal generation for all switches of module #1 is shown in Fig. 4. A DSP TMS320F2407 is selected to generate the PWM signal for all the switches and accomplish the closed-loop control. To improve the conversion efficiency, the primary HF inverters are controlled with the digital phase-shifted (PS) PWM. The generation of digital PS-PWM gate signals for all the primary-side switches S11 . . . S14 is achieved by setting different compare values [14]. It is worth noting that the PWM signals Sy1 and Sy2 shown in Fig. 4 are synchronous signals with the up- and downsides of the symmetrical triangle carrier waveform. The gate sequence for the cycloconverter switches can be obtained as follows:
Q11 = Sy2 • Plf , Q13 = Sy2 • Plf (1) Q12 = Sy1 • Plf , Q14 = Sy1 • Plf where the current polarity diction signal Plf is set at a high level when iLf1 is positive and at a low level when iLf1 is negative. Based on these gate signals, a uniploar SPWM waveform can be obtained from the HF ac link inverter output. A nearly pure sinusoidal waveform can be obtained by a low-pass LC filter. III. OCS C ONTROL S TRATEGY A. Interleaving OCS Control The closed-loop block diagram of the system is shown in Fig. 5. Gv is the voltage compensator, whereas the compensators for all the inner current loops are the same and

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waveform. Take modules #1 and #2 as examples. Assuming the compensation network for the individual inner current loops is identical with the proportional–integral (PI)-type one and substituting (5) into (4), we have the following:    n    kii   iref − iLfj Hij kip + s vcd1   j=2  − vo   iLf2  N1 AC   

      iref − iLfj Hij  kip + ksii vcd2   j=1   j
=2  = − v o  iLf1  N2 AC    

Fig. 5. Control strategy for n-module ISOP HFACL inverters.

denoted as Gic (s). KPWMj is the equivalent transfer function for the PWM generation unit. It should be noted that, for arbitrary individual modules, the inner current feedback is the sum of all the other output inductor currents. For arbitrary module #j, we have   n  if j |j
=i Gij KPWMj − vo iref − i=1

= sLf j .

iLfj

 iref −

n  j=2

 iref =

n  − if j j=1

 iref − =

n−1  j=1

if j

j
=2

...

iLf2 Gin KPWMn − vo .

(4)

Indeed, each HFACL inverter can be viewed as a single-phase inverter, and an equivalent transfer function for the PWM generation unit can be written as KPWMj =

vcdj Nj Ac

n 

(7)

 iLfj Hij

 kip + ksii vcd1 N1 Ac

   n  kip + ksii vcd2   − iLf1 iLfj Hij +iLf1 Hi1 . N2 Ac j=3

 Gi2 KPWM2 − vo

iLfn

Zo . 1 + nsCZo

  n  iref iLf1 kip + ksii vcd2 Zo = − iLf1 iLfj N2 Ac 1+nsCZ o j=1





iLfj

Substituting (7) into (6) leads to   n  iref iLf2 kip + ksii vcd1 Zo − iLf2 iLfj N1 Ac 1+nsCZo j=1

j=2

Gi1 KPWM1 − vo iLf1

n  j=1

− iLf2

 if j

vo =

(3)

According to Fig. 5 and based on (2) and (3)

(6)

where (kip + (kii /s)) is the compensator for all inner current loops and kip and kii are the proportional and integral coefficients, respectively. It is assumed that individual output filtering capacitors are identical with the value C; therefore, the output ac voltage can be expressed as

(2)

The individual output ac filtering inductors are designed with the same values, i.e., Lf 1 = Lf 2 . . . = Lf j . . . = Lf n .

n 

(5)

where Ac is the peak value of the carrier waveform of the PWM generation unit. All the modules share the same carrier

(8)

Supposing that modules #1 and #2 have identical parameters, we have N1 = N2 and Hi1 = Hi2 , considering that the two modules share the same input current and the same output voltage at steady states. According to the power balance, the relationship between the two individual input voltages and output currents can be expressed as vcd1 io1 = . vcd2 io2

(9)

For each module, its output inductor current can be viewed equivalent to its output load current by neglecting the performance of its output ac filtering capacitor. Therefore, we have the following: vcd1 iLf2 = vcd2 iLf1 .

(10)

SHA et al.: CONTROL STRATEGY FOR ISOP HFACL INVERTERS

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Substituting (10) into (8), we obtain iLf2

n 

iLfj

j=1

= iLf1

  n  kip + ksii vcd1 Zo +iLf2 iLfj Hij 1+nsCZo N1 Ac j=2

n 

iLfj

j=1



Zo 1+nsCZo

  kip + ksii vcd2 + iLf1 iLfj Hij +iLf1 Hi1  . (11) N2 Ac j=3 n 

Expanding (11), we have i2Lf2

Fig. 6. Diagram of instantaneous power and active and reactive powers.

Zo Zo + iLf1 iLf2 1 + nsCZo 1 + nsCZo

+ iLf2

n 

iLfj

j=3

where the coefficients A, B, and C are given by      cd1 iLf2 cd2 iLf1 = kip + ksii Hi1 vN A = kip + ksii Hi2 vN 1 AC 2 AC n   Z o B = iLfj 1+nsCZ o  j=3

Zo 1 + nsCZo

C=

  kii iLf2 vcd1 + iLfj Hij kip + s N1 AC j=3 n 

Zo Zo + iLf1 iLf2 1 + nsCZo 1 + nsCZo

+ iLf1

n 

iLfj

j=3

+

Zo 1 + nsCZo

  kii iLf1 vcd2 iLfj Hij kip + s N2 AC j=3

n 

  vcd2 kii + i2Lf1 Hi1 kip + . s N2 AC

(12)

Simplifying (12), we obtain n  Zo Zo + iLf2 iLfj 1 + nsCZo 1 + nsCZ o j=3   kii iLf2 vcd1 + iLf2 Hi2 kip + s N1 Ac

where θ is the phase difference between the output ac voltage and current and Vo and Io are the rms values of the output ac voltage and current. Then, the instantaneous power is defined as p = vi = 2Vo Io cos ωt cos(ωt − θ).

i2Lf2

n  Zo Zo + iLf1 iLfj 1 + nsCZo 1 + nsCZ o j=3   kii iLf1 vcd2 + iLf1 Hi1 kip + . s N2 Ac

(15)

As seen, the power is transferred from the input dc side to the output ac side during the normal mode in which the output voltage and individual output currents are in the same direction. Nevertheless, in the energy regenerative mode, the output ac voltage and individual output currents are in opposite directions, and the power is transferred from the output ac side to the input dc side. At steady states, assuming that all the input dividing capacitor voltages balanced during one fundamental period of the output ac voltage, they are denoted as Vcd1 , Vcd2 , . . . , Vcdn , respectively. For an inverter with purely sinusoidal output, the output voltage and current can be respectively expressed as
√ v = √ 2Vo cos ωt (16) i = 2Io cos(ωt − θ)

  vcd1 kii + i2Lf2 Hi2 kip + s N1 AC = i2Lf1

Zo 1+nsCZo .

(17)

Furthermore, the instantaneous power in (17) can be expressed as p = vi = Vo Io cos θ(1+cos 2ωt)+Vo Io sin θ sin 2ωt.

= i2Lf1

(13)

Equation (13) can be revised as (A + B) × iLf2 + C × i2Lf2 = (A + B) × iLf1 + C × i2Lf1 (14)

(18)

As seen, the instantaneous power contains two parts. The first part is the instantaneous active power, whereas the second part is the instantaneous reactive power. Fig. 6 shows the diagram of the instantaneous power and active and reactive powers. As seen, the fundamental frequency of the instantaneous power is twice that of the output voltage. To simplify the analysis, only modules #1 and #2 are taken as examples to reveal the relationship between the two output currents. Similarly, for individual modules, the individual input

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current can be divided into two parts. One is called active input current due to instantaneous active power, whereas the other is named reactive input current, resulting from instantaneous reactive power. For module #1, its input current can be expressed as iin1 = iina1 + iinp1

(19)

where iina1 and iinp1 represent active and reactive input currents, respectively, for module #1, respectively. For this module, the average input and output active power during one complete period can be written as  2π  2π  Vcd1 iin1a dωt iin1a dωt  0 = Vcd1 . 0 2π = Vcd1 ·Iin1a Pavein1 =  2π 2π Vo Io cos θ(1+cos 2ωt)dωt  Paveout1 = 0 = Vo ·Io1 ·cos θ1 2π (20) where θ1 is the phase difference between the output ac voltage and current for module #1. Vo is the rms value of the output ac voltage. For this module, Io1 is the rms value of the output current of this module, and Iin1 represents the average value of the input active current. In the same way, we can obtain the expressions of the average values of active input and output powers for module #2. According to the power balance, during one fundamental period, the individual input voltage can be viewed unchanged, and we can obtain the following:
Vcd1 · Iin1a = Vo · Io1 · cos θ1 (21) Vcd2 · Iin2a = Vo · Io2 · cos θ2 . Because of the input-series connection, the input average current of module#1 is identical with that of module#2; thus, we have Iin1a = Iin2a . As seen for the instantaneous reactive power, although its average value is zero during one complete period, we can calculate its average value during one complete half period, in which the direction of the reactive power is kept unchanged. The average input power from the input reactive current and the average of instantaneous reactive power during one complete half period can be expressed as  π π 2 2   Paveinp1 = 0 Vcd1 iin1p dωt = Vcd1 . 0 iin1p dωt = Vcd1 ·Iin1p π/2 π/2 π/2 π 2 V I  o o1 sin θ1 sin 2ωtdωt  ·sin θ1 Paveout1 = 0 = Vo ·Io1 π/2 π/2 (22) where Iin1p symbolizes the integration of reactive current over a complete half period. According to the power balance for reactive power, we have the following:
Vcd1 · Iin1p = Vo · Io1 · sin θ1 (23) Vcd2 · Iin2p = Vo · Io2 · sin θ2 . Because of the input-series connection, the input average current of module#1 is identical with that of module#2, i.e., Iin1p = Iin2p . From (21) and (23), we can obtain the following: Vcd1 Io1 · cos θ1 Io1 · sin θ1 = = . Vcd2 Io2 · cos θ2 Io2 · sin θ2

(24)

Fig. 7.

Control strategy for the two-module ISOP HFACL inverters.

Simplifying and rearranging (24), we have sin(θ1 − θ2 ) = 0.

(25)

As seen from (25), we can conclude that the output currents of modules #1 and #2 have the same or opposite phase angles. Neglecting the effect of individual capacitors, the instantaneous values of the two output inductor currents can be written as iLf1 = k · iLf2 = k · I · sin(ωt + θ)

(26)

where k is a constant and I is the peak value of output inductor current for module#2. Substituting (26) into (14) yields 1 1 (A+B)I sin(ωt+θ)+ CI 2 − CI 2 cos(2ωt+2θ) 2 2 1 2 2 1 2 2 = k(A+B)I sin(ωt+θ)+ k CI − k CI cos(2ωt+2θ). 2 2 (27) As seen, if the left side of the aforementioned equation is equal to its right side, we can deduce that k = 1, i.e., the instantaneous values of the two output inductor currents are equal to each other. Since both the two modules share one common output ac voltage and the values of individual filtering capacitors are identical, the instantaneous values of the two output currents are also identical. This conclusion also applies to the other modules, i.e., the instantaneous values of the output currents for other modules are also identical to each other. B. Loop Gain Design An ISOP two-inverter system is taken as an example to illustrate the loop-gain design. Before the analysis, it is assumed that both the two converters have identical parameters, i.e., Lf 1 = Lf 2 = L, Cf 1 = Cf 2 = C, KPWM1 = KPWM2 = KPWM , and N1 = N2 = N . Fig. 7 shows the control strategy for the two ISOP-connected HFACL inverters. According to the connection, we can obtain


v1 − vo = sLf 1 · iLf1 v2 − vo = sLf 2 · iLf2

(28)

whereas the output voltage is given by vo = (iLf1 + iLf2 )

Ro . 1 + 2sCRo

(29)

SHA et al.: CONTROL STRATEGY FOR ISOP HFACL INVERTERS

Fig. 8.

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Equivalent control diagram for the proposed control strategy.

Substituting (25) into (24) yields 

iLf1 iLf2





G1 = G2

G2 G1



v1 v2



where G1 and G2 are expressed as follows:  sL(1+2sCRo )+Ro G1 = [sL(1+2sCR o )+2Ro ]sL G2 =

−Ro [sL(1+2sCRo )+2Ro ]sL .

(30)

(31)

The proposed control strategy can also be shown in Fig. 8. According to this figure, the loop gain of the current loop for module#1 can be written as Tid1 (s) = Gi1 KPWM1 G2 Hi2   − kpi + ksii · Vcd1 · Ro · Hi2 . = N · Ac · [sL(1 + 2sCRo ) + 2Ro ] sL

(32)

It should be noted that the compensation network for the inner current loops is of PI type. According to Fig. 8, we have
(iref − Hi2 iLf2 )Gi1 KPWM = v1 (33) (iref − Hi1 iLf1 )Gi2 KPWM = v2 . Based on (28), (29), and (33), we obtain  +iLf2 )·Ro = iLf1 sLf 1 (iref −Hi2 iLf2 )Gi1 KPWM − (iLf1 1+2sCRo

+iLf2 )·Ro (iref −Hi1 iLf1 )Gi2 KPWM − (iLf1 = iLf2 sLf 2 . 1+2sCRo (34) Rearranging (34) and setting Gi1 = Gi2 = Gic , we get i Gic KPWM (1+2sCRo ) Lf1 iref = Hi Gic KPWM (1+2sCRo )+2Ro +sL(1+2sCRo ) (35) Gic KPWM (1+2sCRo ) iLf2 iref = Hi Gic KPWM (1+2sCRo )+2Ro +sL(1+2sCRo ) .

The equivalent transfer function for all current loops, shown in the dashed box in Fig. 8, is expressed as Giequ =

iLf1 +iLf2 iref

=

2Gic KPWM (1+2sCRo ) . (36) Hi Gic KPWM (1+2sCRo )+2Ro +sL(1+2sCRo )

The specifications of the two ISOP-connected HFACL inverters are as follows: 1) input voltage: 780–960 V dc; 2) output voltage: 110 V ac/50 Hz; 3) maximum rms value of the output current: 10 A; 4) switching frequency: 16.7 kHz; 5) transformer turns ratio: N1 = N2 = 2; 6) output LC filter: L = 0.3 mH, C = 20 µF. Based on the parameters for the ISOP configuration, the voltage Hv and current Hi sensor gains are 0.028 and 0.2, respectively, and the peak value of the ramp Ac is 0.375 V. Both PI-type compensations for output voltage and inner current loops are made. During uncompensated conditions, both the transfer functions of compensators Gic (s) and Gv (s) equal one. The crossover frequency of current loop is chosen to be 7 kHz, which is roughly below half of the switching frequency. The compensator network is chosen as Gic (s) = 2.5 +

(37)

2000 . s

(38)

As shown in Fig. 9, the original loop gain of Tid (s) has a magnitude of −8.4 dB at 7 kHz, but after compensation, the compensated loop gain has a crossover frequency of 7 kHz with a phase margin of 95.3◦ . For the OVR loop gain design, the compensator is also PI type and written as Gv (s) = 3 +

Therefore, the loop gain of the OVR loop is Tvo (s) = Hv Gv (s)Giequ (s)Ro /(2sRo C + 1).

Fig. 9. Uncompensated and compensated inner current loop gains.

2.5 × 104 . s

(39)

Fig. 10 shows the compensated OVR loop gains with the compensator shown in (35). As shown in the figure, the uncompensated loop gain has a magnitude of −8.7 dB at a crossover frequency of 3 kHz. However, after compensation, the phase margin of the compensated loop gain is 70◦ at this

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Fig. 11.

Simulated response with a step change of load.

Fig. 12.

Simulated response with a step change of the input voltage.

Fig. 10. Uncompensated and compensated OVR loop gains.

frequency, which is sufficient enough for the system to be stable. Moreover, at the fundamental frequency of 50 Hz, the compensated loop gain has a magnitude of 47.6 dB, which leads to high precision tracking of the voltage reference vref . IV. S IMULATION AND E XPERIMENTAL VALIDATION To test the validity of the proposed control strategy, the simulations and experiments are carried out on two HFACL inverters connected in an ISOP configuration. The main circuit of the ISOP inverter system can be seen in Fig. 2, and the specifications for the system are the same with those given for the loop gain design in Section III, except for the turns ratios of the two HF transformers. Note that, to verify the effectiveness of the control strategy in the presence of turnsratio mismatches, the turns ratios of the two HF transformers are purposely designed to be different with 2:1 and 1.9:1, respectively. A. Simulation Validation To verify the effectiveness of the control strategy, the simulation results are shown in Figs. 11 and 12. Fig. 11 shows the output voltage, the two output inductor currents, and the input individual dividing voltages facing a step change between the full and half loads. As seen, both instantaneous values of the output inductor currents are almost the same, and equal sharing of the load current as well as the total input voltage is achieved. Fig. 12 shows the response of the two individual output currents facing a step change of the input voltage. As shown, despite the step change, the output inductor currents are almost unaffected, and the OCS is achieved with negligible circuiting currents.

B. Experimental Validation Fig. 13 shows the gate signals for the cycloconverter switches for module #1 at an inductive load. As seen, when the output inductor current is positive, Q11 is gated on and off with HF, whereas Q13 is always kept off. However, when the output inductor current is negative, Q11 is always kept off, whereas Q13 is gated on and off with HF. The gating logic for the cycloconverter switches is determined by the polarity of the inductor output current instead of that of the output voltage. Fig. 14 shows the steady-state waveforms with the full resistive load. As seen, with the proposed control strategy, the load current can be shared fairly well between the two modules. The difference of the two inductor currents revealing the circulating current is almost zero, and the two inductor currents have almost the same instantaneous values.

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Fig. 13. Gating sequence for cycloconverter switches at an inductive load.

Fig. 16. Experimental steady-state waveforms under an inductive load.

Fig. 14. Steady-state waveforms under the full resistive load.

Fig. 17. Experimental waveforms of individual input voltages and the output inductor currents under a rectifier load.

Fig. 15. Primary voltages of HF transformers and individual output currents under the full resistive load.

Fig. 15 shows the primary voltages of the two HF transformers and the individual input voltages under the rated resistive load. Because the turns ratio of the HF transformer T2 is less than that of HF transformer T1 , to correct for the mismatch, the duty ratio for module #2 is smaller than that for module#1, whereas the two individual input voltages are kept almost the same. Fig. 16 shows the output voltage, individual output inductor currents, and HF link voltage waveform of module #1 under an inductive load which is series connected a 16-Ω resistor and a 24-mH inductor. As illustrated, the load current can be

evenly shared. The voltage waveform transmitted by the HF transformer is HF pulsating, and their low-frequency ripple is synchronous with the phase of the output voltage. Fig. 17 shows the individual input dividing voltages and output inductor currents under a full-bridge rectifier connected directly to a 1000-µF capacitor in parallel with a 20-Ω resistor. As seen, even under the nonlinear load, the two output inductor currents have almost the same instantaneous values despite the waveform distortion. The total input voltage is shared fairly well. Fig. 18 shows the transient response during a step change of the input voltage varying between 780 and 960 V. As seen, even during the transients, an even sharing of the load current by the two modules can be obtained. Figs. 19 and 20 show the transient waveforms during a step change of half and full resistive loads. As seen from Fig. 19, both the two output inductor currents have almost the same instantaneous value and the output ac voltage is unaffected during this process. In Fig. 20, IVS can be achieved well in spite of the load transient. V. C ONCLUSION In this paper, the ISOP-connected HFACL inverters, which are suitable for high-input-voltage applications, are discussed. Each inverter is composed of an HF inverter followed by a matrix converter by placing an HF transformer between them.

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Fig. 18. Experimental transient waveforms at the full resistive load against a step change of the input voltage.

To achieve power sharing balance for each module, a two-loop control scheme, composed of a common OVR loop and individual inner current loops, is presented by avoiding individual high input voltage sensing. It is worth noting that, for a specific module, its feedback of the inner current loop is the sum of all the other output inductor currents instead of itself. With this scheme, although individual input voltages are not detected, perfect sharing of the input voltage and the load current can be achieved not only under steady state but also under dynamic process even in the face of component mismatches such as the turns-ratio mismatch of individual power transformers. Two ISOP-connected HFACL inverters are taken as examples to show the loop gain design of the common OVR and OCS loops and the simulation and experimental verification. Simulation and experimental results of a 1100-VA prototype validate the effectiveness of the control strategy. R EFERENCES

Fig. 19. Output voltage corresponding to a step change between half and full resistive loads.

Fig. 20. Individual input voltages corresponding to a step change between half and full resistive loads.

Apart from the modular architecture advantages, by selecting the HFACL inverter as the constituent module, the configuration owes the features: bidirectional power flow capability, simplified control circuit design, more adaptivity to different loads. For the HFACL inverter modules, a PWM generation based on the detection of an arbitrary output inductor current is presented. With the proposed method, the circulating currents among the constituent modules can be avoided, and therefore, the general control strategy for the system can be simplified.

[1] P. J. Grbovic, “High-voltage auxiliary power supply using seriesconnected MOSFETs and floating self-driving technique,” IEEE Trans. Ind. Electron., vol. 56, no. 5, pp. 1446–1455, May 2009. [2] J. Rodriguez, S. Bernet, P. K. Steimer, and I. E. Lizama, “A survey on neutral-point-clamped inverters,” IEEE Trans. Ind. Electron., vol. 57, no. 7, pp. 2219–2230, Jul. 2010. [3] R. Stala, “The switch-mode flying capacitor dc–dc converters with improved natural balancing,” IEEE Trans. Ind. Electron., vol. 57, no. 4, pp. 1369–1382, Apr. 2010. [4] H. Abu-Rub, J. Holtz, J. Rodriguez, and G. Baoming, “Medium-voltage multilevel converters—State of the art, challenges, and requirements in industrial applications,” IEEE Trans. Ind. Electron., vol. 57, no. 8, pp. 2581– 2596, Aug. 2010. [5] R. Giri, V. Choudhary, R. Ayyanar, and N. Mohan, “Common-duty-ratio control of input-series connected modular dc–dc converters with active input voltage and load-current sharing,” IEEE Trans. Ind. Appl., vol. 42, no. 4, pp. 1101–1111, Jul./Aug. 2006. [6] J. W. Kim, J. S. Yon, and B. H. Cho, “Modeling, control, and design of input-series-output-parallel-connected converter for high-speed-train power system,” IEEE Trans. Ind. Electron., vol. 48, no. 3, pp. 536–544, Jun. 2001. [7] P. J. Grbovic, “Master/slave control of input-series-and output-parallelconnected converters: Concept for low-cost high-voltage auxiliary power supplies,” IEEE Trans. Power Electron., vol. 24, no. 2, pp. 316–328, Feb. 2009. [8] J. W. Kimball, J. T. Mossoba, and P. T. Krein, “A stabilizing, highperformance controller for input-series-output parallel converters,” IEEE Trans. Power Electron., vol. 23, no. 3, pp. 1416–1427, May 2008. [9] K. Siri, M. Willhoff, and K. Conner, “Uniform voltage distribution control for series connected dc–dc converters,” IEEE Trans. Power Electron., vol. 22, no. 4, pp. 1269–1279, Jul. 2007. [10] X. Ruan, W. Chen, L. Cheng, C. K. Tse, H. Yan, and T. Zhang, “Control strategy for input-series-output-parallel converters,” IEEE Trans. Ind. Electron., vol. 56, no. 4, pp. 1174–1185, Apr. 2009. [11] W. Chen, X. Ruan, H. Yan, and C. K. Tse, “DC/DC conversion systems consisting of multiple converter modules: Stability, contol and experimental verifications,” IEEE Trans. Power Electron., vol. 24, no. 6, pp. 1463– 1474, Jun. 2009. [12] Y. Huang, C. K. Tse, and X. Ruan, “General control considerations for input-series connected DC/DC converters,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 56, no. 6, pp. 1286–1296, Jun. 2009. [13] R. Ayyanar, R. Giri, and N. Mohan, “Active input-voltage and load-current sharing in input-series and output-parallel connected modular dc–dc converters using dynamic input-voltage reference scheme,” IEEE Trans. Power Electron., vol. 19, no. 6, pp. 1462–1473, Nov. 2004. [14] D. Sha, Z. Guo, and X. Liao, “DSP based series-parallel connected two full-bridge DC–DC converters,” J. Power Electron., vol. 10, no. 6, pp. 673–679, Nov. 2010. [15] D. Sha, Z. Guo, and X. Liao, “Cross feedback output current sharing control for input-series-output-parallel modular dc–dc converters,” IEEE Trans. Power Electron., vol. 25, no. 11, pp. 2762–2771, Nov. 2010.

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[16] H. Cai, R. X. Zhao, and H. Yang, “Study on ideal operation status of parallel inverters,” IEEE Trans. Power Electron., vol. 23, no. 6, pp. 2964– 2969, Nov. 2008. [17] M. Pascual, G. Garcerá, E. Figueres, and F. González-Espín, “Robust model-following control of parallel UPS single-phase inverters,” IEEE Trans. Ind. Electron., vol. 55, no. 8, pp. 2870–2883, Aug. 2008. [18] Z. Yao, L. Xiao, and Y. Yan, “Dual-buck full-bridge inverter with hysteresis current control,” IEEE Trans. Ind. Electron., vol. 56, no. 8, pp. 3153– 3160, Aug. 2009. [19] Z. Ye, P. K. Jain, and P. C. Sen, “Circulating current minimization in high-frequency ac power distribution architecture with multiple inverter modules operated in parallel,” IEEE Trans. Ind. Electron., vol. 54, no. 5, pp. 2673–2687, Oct. 2007. [20] M. Cacciato, A. Consoli, R. Attanasio, and F. Gennaro, “Soft-switching converter with HF Transformer for grid-connected photovoltaic systems,” IEEE Trans. Ind. Electron., vol. 57, no. 5, pp. 1678–1686, May 2010. [21] D. Sha, Z. Guo, and X. Liao, “Control strategy for input-parallel-outputparallel connected high-frequency isolated inverter modules,” IEEE Trans. Power Electron., vol. 26, no. 8, pp. 2237–2248, Aug. 2011. [22] W. Chen, K. Zhang, and X. Ruan, “A input-series- and output-parallelconnected inverter system for high-input-voltage applications,” IEEE Trans. Power Electron., vol. 24, no. 9, pp. 2127–2137, Sep. 2009. [23] W. Chen and X. Ruan, “An improved control strategy for input-series and output-parallel inverter system at extreme conditions,” in Proc. IEEE ECCE, 2010, pp. 2096–2100. [24] T. Fang, X. Ruan, and C. K. Tse, “Control strategy to achieve input and output voltage sharing for input-series-output-series connected inverter systems,” IEEE Trans. Power Electron., vol. 25, no. 6, pp. 1585–1596, Jun. 2010. [25] T. Fang, X. Ruan, and C. K. Tse, “Control strategy of achieving input voltage sharing and output voltage sharing for input-series-output-series inverters system,” in Proc. IEEE ECCE, 2009, pp. 908–915. [26] D. De and V. Ramanarayanan, “A dc-to-three-phase-ac high-frequency link converter with compensation for nonlinear distortion,” IEEE Trans. Ind. Electron., vol. 57, no. 11, pp. 3669–3677, Nov. 2010. [27] K. Mazumder, R. K. Burra, R. Huang, M. Tahir, and K. Acharya, “A universal grid-connected fuel-cell inverter for residential application,” IEEE Trans. Ind. Electron., vol. 57, no. 10, pp. 3431–3447, Oct. 2010. [28] A. K. Rathore, A. K. S. Bhat, S. Nandi, and R. Oruganti, “Small signal analysis and closed loop control design of active-clamped ZVS twoinductor current-fed isolated DC–DC converter,” IET Power Electron., vol. 4, no. 1, pp. 51–62, Jan. 2011.

Deshang Sha (M’09) was born in 1977. He received the B.S. degree in electrical engineering from Luoyang Institute of Technology, Luoyang, China, in 1998, the M.S. degree in electrical engineering from Nanjing University of Aeronautics and Astronautics, Nanjing, China, in 2001, and the Ph.D. degree in electrical engineering from the Institute of Electrical Engineering, Chinese Academy of Sciences, Beijing, China, in 2005. From 2005 to 2007, he was the Head and Chief Engineer of the full-digitalized welding machine research department of Time Group, Inc. Since 2008, he has been with the School of Automation, Beijing Institute of Technology (BIT), Beijing, where he is currently an Associate Professor. His research interests are in the areas of modeling of power converters, control of power converters, and power electronics application in renewable energy power generation systems. Dr. Sha was awarded as an Excellent Yong Scholar of BIT in 2010.

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Kai Deng was born in 1986. He received the B.S. degree in electrical engineering from Nanjing Agricultural University, Nanjing, China, in 2009. He is currently working toward the M.S. degree in electrical engineering at the Beijing Institute of Technology, Beijing, China. His research interests include digital control of power converters and system integration of modular power converters.

Zhiqiang Guo (S’11) was born in 1985. He received the B.S. degree in automation from Hebei University of Technology, Tianjin, China, in 2008 and the M.S. degree in automation from Beijing Institute of Technology (BIT), Beijing, China, in 2010, where he is currently working toward the Ph.D. degree in electrical automation. His research interests are in the areas of modeling and control of power electronics converters.

Xiaozhong Liao (M’09) was born in China in 1962. She received the B.S. and M.S. degrees in electrical engineering from Tianjin University, Tianjin, China, in 1982 and 1984, respectively, and the Ph.D. degree in control sciences and engineering from the Beijing Institute of Technology (BIT), Beijing, China, in 2004. She was a Visiting Researcher at the Department of Electrical and Electronic Engineering, University of Central Lancashire, Preston, U.K., from 1995 to 1996. She is currently an Associate Dean and Full Professor with the School of Automation, BIT. Her research interests are in the fields of power electronics, motor drives, and renewable energy power conversion.