Copper Pillar Bump Structure Optimization for Flip Chip Packaging ...

Copper Pillar Bump Structure Optimization for Flip Chip Packaging with Cu/Low-K Stack X.R. Zhang*, W.H. Zhu, B.P. Liew, M. Gaurav United Test & Assembly Center Ltd (UTAC) 5 Serangoon North Ave 5, Singapore 554916 *[email protected] A. Yeo and K.C. Chan GLOBALFOUNDRIES Singapore Pte Ltd 60 Woodlands Industrial Park D Street 2, Singapore 738406 Abstract Copper pillar bumping is a promising solution to cope with the challenges which flip chip packages face when bump pitch size keep shrinking. A large FCBGA(flip chip ball grid array) package for 45nm Cu/Low-K device with Cu pillar bumps is chosen to investigate the package reliability. Finite element models have been built with multi-level sub-modeling technique to consider the detailed Cu/Low-K structure in the chip. Comparison on Cu pillar bumps vs. solder bumps shows the former bump type generated about 20~30% higher stress on Cu/lowK structure. Thus package reliability may become a concern when Cu pillar is used. To improve the package reliability, design optimization is carried out on Cu pillar bump structure. DOE (design of experiment) study is done on the following factors: Cu pillar height, PI (polyimide) passivation opening and PI thickness etc. Loading is considered for both post flip chip attach process (reflow) and after full assembly (curing). It is found that the stress in post flip chip attach process is much higher than that after full assembly. For Cu/low-K devices, special care is needed for flip chip attach process. Stress on Cu/low-K interface has been analyzed in detail, and it is shown that the interface stress pattern is highly dependent on UBM structure design, especially PI opening and thickness. An overall picture of the PI effect is presented based on optimization results. Lower Cu pillar height, smaller PI opening and higher thickness are recommended for bump structure design. 1. Introduction Flip Chip technology is gaining more and more market share in high-density packaging, due to a growing demand for cheaper, smaller and faster consumer electronic devices[1]. Conventional solder bumped flip chip will encounter some challenges when bump pitch size keep shrinking. Firstly, with decreasing bump pitch, the electrical current and thermal energy density in the flip chip interconnects is increasing. This will pose a package reliability concern due to solder bump electromigration. Secondly, flip chip process will become more difficult as bumps getting closer to each other, shorting of I/O pads may happen as a result of bump bridging. Copper pillar bumping is one of the solutions to the above challenges, which use Cu-pillar bumps to replace

C 2010 IEEE 978-1-4244-7027-310/$26.00

solder ball bumps as a flip chip interconnects[2-4]. Cupillar bump comprises of two segments: a copper base and a solder tip or cap. The volume of solder tip is much smaller than that of conventional solder bump. It has superior electrical and thermal characteristics over its conventional counterpart, and can take the form of flexible shapes to resolve the problems that come with increased electrical current and thermal energy density[5-8]. Although Cu pillar bumping may have several advantages over its conventional counterpart. There are also challenges for this technology, especially for advance technology nodes devices using Cu/low-K stack[1]. Devices using low-K dielectric tends to be very sensitive to assembly and packaging stresses, due its inferior mechanical properties (i.e. low modulus, low strength and poor adhesion) compared to the conventional dielectric materials. Furthermore, Cu pillar bumps may cause higher stress in flip chip packages than its conventional counterpart, as Cu is much stiffer than solder materials. In this paper, a large FCBGA(flip chip ball grid array) package for Cu/Low-K device (45nm technology) bumped with Cu pillar bumps is investigated on the package reliability with finite element analysis method. Finite element models will be built with multi-level global-local technique to consider the detailed Cu/LowK structure in the chip. Comparison on the stress in Cu/lowK structure is done between Cu pillar bumps to traditional solder bumps. Based on the comparison results, the package reliability may become a concern when Cu pillar is used. Thus a further design optimization on Cu pillar bump structure is then carried on to minimize the stress. 2. Package Information and Simulation Model The FCBGA package (See Fig. 1) consists of the silicon die, Cu pillar bumps, underfill encapsulant, heat spreader, and BT substrate. A copper cover lid is attached on substrate by ring adhesive, and a thermal interface material (TIM) is applied on the top of die for heat conduction. It is noted that Cu pillar bumps are used here as the interconnection between die and substrate, instead of traditional solder bumps. Cu-pillar bump comprises of two segments: a copper base and a solder cap (SnAg2.3), as shown in Figure 2. Typical package dimensions are listed: Package size: 42.5x42.5mm2, Die size: 14.5 x 14.5 x 0.787 mm3, Bump

—1—

11th. Int. Conf. on Thermal, Mechanical and Multiphysics Simulation and Experiments in Micro-Electronics and Micro-Systems, EuroSimE 2010

standoff: 85 um, Heat spreader thickness: 0.5mm, 4-2-4 built-up substrate thickness: 0.89 mm. A 2D plane strain model is established, and only ½ of the package is modeled due to symmetry. A multi-level sub-modeling strategy including a global model, a local model and a micro-model is used, as shown in Figure 3 (see next page). The global model is the whole flip-chip package model including the die, underfill (UF), built-up substrate, Cu lid and stiffener, and pillar bumps (Geometric model see Figure 3a). The mesh of the global model is too dense to show the element outlines, only part of the mesh is zoomed as shown in Figure 3b. The local model includes only a portion of the package containing the die edge, part of substrate and the outermost bump interconnection (See Figure 3c). The micro-model includes Cu metal lines and various dielectric materials, such as FTEOS and low-k material, illustrates in Figure 3d. They are homogenized into different layers with equivalent properties, which are used in the local level modeling. The next level model uses the displacement generated by the up-level model as boundary conditions (cut boundary).The basic material properties of the models are listed in Table 1. As lowK is weak and brittle in the device, and Cu pillar is stiffer than solder, it is possible to see Cu/lowK or UBM failure in the device during assembly. Figure 4 shows the typical FCBGA assembly process flow. From this flow, 2 critical loading cases have been considered: 1) loading case a), cooling from 220°C to 25°C for post FC attach process, to simulate the reflow profile after the flip chip attached to the substrate (without underfill); 2) loading case b), cooling from 150°C to 25°C for after assembly process, to simulate the whole package after underfill and adhesive curing process (with underfill). HEAT SPREADER

STIFFENER RING EPOXY

THERMAL INTERFACE MATERIAL

CU PILLAR + SnAg2.3 Cap

UNDERFILL

M1: Copper post height M2: Solder cap height M3: Bump space (min 25um) Pad Pitch (um) 200 150 100 50

UBM size (um) 100 80 65 25

Cu Post M1 (um) 65 50 45 17

Cap M2 (um) 35 35 30 15

Fig. 2 Cu Pillar Design Rules Table 1 List of material properties Materials

E (GPa)

Poisson’s CTE1 (ppm/ Ratio C)

Si Die

131

0.3

2.8

Copper

127.4

0.3

17.4

Alumina

70.5

0.3

23.6

BT core

26.0

0.3

14

Build-up

4

0.3

47

FTEOS

53

0.3

1.6

LK1 (k=3.1)

15.5

0.3

10.1

LK2 (k=2.7)

7

0.3

20

Wafer income Wafer Saw HIGH DENSITY 10 LAYER SUBSTRATE

Flip Chip Attach

SOLDER BALL (PB Free)

a) Package diagraph

Flip Chip Reflow Underfill Plasma Underfill Dispense Underfill Cure

b) SEM cross-section Fig. 1 FCBGA with Cu Pillar Bump Interconnect

HS Epoxy/TIM Dispense

HS Attach

HS Epoxy Cure Ball Mount / Reflow

VM

Test/Ship

Fig. 4 FCBGA process flow

—2— 11th. Int. Conf. on Thermal, Mechanical and Multiphysics Simulation and Experiments in Micro-Electronics and Micro-Systems, EuroSimE 2010

(a) FCBGA geometric model

LK2 stack Stress plot path

(b) Zoom of global model

(c) Local model

LK1 stack

(d) Micro-model: Cu/Low-K stack-up

Fig. 3 Multi-level sub-model of Cu/low-k in FCBGA 3. Comparison between Cu Pillar and Solder bump In order to get information on Cu pillar effect on Cu/LowK stress, comparison is carried on Cu pillar bumps vs. conventional solder bumps (eutectic and leadfree). Figure 5 shows the equivalent stress in Cu components in the BEOL (backend of line) interconnection layers for both eutectic solder (Figure 5a) and Cu pillar bumps (Figure 5b) from micro-model. It can be seen that highest stress located in the lowest Cu layer from the bump side. Table 2 compares the maximum stress in the Cu and lowK components for solder bumps (eutectic and leadfree) and Cu pillar bumps. It is indicated that leadfree solder leads to 10~15% stress increase than eutectic solder, while Cu pillar leads to 20~30% stress increase. Thus with Cu pillar, more challenges are faced for the reliability of Cu/lowK devices.

a)

Eutectic solder (Equivalent stress MPa)

b) Cu pillar (Equivalent stress MPa) Fig. 5 Stress in Cu interconnection Table 2 Cu pillar vs. solder bump (' ) # * " + ,- .

" $# % % &

!

4. Simulation results Results will be presented first on stress analysis for control case (Cu pillar height=50um, PI opening=47um, PI thickness=4um), followed by Cu pillar height, PI opening and thickness effects. Stress distribution in UBM, Al pad, and Cu pillar will be presented, as well as the interfacial stress along with Cu/lowK interface. 4.1 Stress analysis for Control case


Figure 7 shows the stress in Cu pillar and solder cap. It is also noted that bump stress after FC attach reflow is much higher than after assembly. 4.2 Cu pillar height effect Since Cu pillar causes higher stress than solder as the former is harder, the Cu pillar height effect (thus Cu percentage in the bump) is studied to minimize the stress. 1020.0 1000.0 980.0 UBM Stress Seqv (MPa)

a) After FC attach reflow

960.0 940.0 920.0 900.0 880.0 Seqv_ubm 860.0 840.0 0

10

20

30

40

50

60

70

Cu Pillar Height (um)

Fig. 8 Effect of Cu pillar height on UBM stress b) After Assembly Fig. 6 Stress in UBM and Al Pad Figure 6 shows the stress in UBM and Al Pad. It is seen that after FC attach reflow, maximum principal and equivalent stress located in UBM left corner; and after full assembly, maximum equivalent stress located in UBM right corner. It should be noted that principal stress (tensile) after FC attach reflow is much higher than after assembly. As after FC attach reflow and before underfilling, die is connected to substrate only through cu pillar.

Figure 8 shows the effect of Cu pillar height on UBM equivalent stress after assembly. The height of solder cap is 35um. It is shown that lower pillar height, lower UBM (and also Cu pillar) stress. As well known, Cu/lowK interface is the potential interface for delamination, stress along the interface is the critical driving force. The top Cu/lowK interface is chosen here to study the typical stress behavior. Stress plot path is indicated in Figure 3d), which the distance covers a diameter of Al pad. The interface normal and shear stresses distribution along the path for different Cu pillar height after assembly are shown in Figure 9. It can be seen, that the lower pillar height, the lower Cu/LowK interface stress. The trend is same as the trend for UBM. 100

Lo w K In terface Stress (MPa)

50

a) After FC attach reflow

0 0.00

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

0.10

-50 -100

Sxy_50um Sy_50um

-150

Sxy_35um Sy_35um

-200

Sxy_65um Sy_65um

-250 Distance (m m)

Fig. 9 Cu/LowK interface stress

b) After Assembly Fig. 7 Stress in Cu Pillar and Solder Cap

4.3 PI (PI opening and thickness) effect PI geometric parameter effect is studied to look into the ways to lower the stress at UBM and Cu/Low-K interface from the bumping point of view. DOE run for 4 cases, with the combination of PI thickness (4um and 6um) and PI opening (30um and 47um).


LowK Interface Stress (MPa)

3.50E+02 3.00E+02

Sxy_47umOpening

2.50E+02

Sy_47umOpening Sy_30umOpening

2.00E+02

Sxy_30umOpening

PI Opening: 30um

1.50E+02 1.00E+02

PI Opening: 47um

5.00E+01 0.00E+00 -5.00E+01

0

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

0.1

Al pad: 73um

-1.00E+02 -1.50E+02

Distance (mm)

a) Ctrl case: 47um opening, 4um thick

(a) PI opening effect 3.50E+02 3.00E+02 Sxy_4umThick


2.50E+02

Sy_4umThick

PI Opening: 47um

2.00E+02

Sy_6umThick Sxy_6umThick

1.50E+02

Al pad: 73um

1.00E+02 5.00E+01

0.00E+00 0.00E+00 1.00E-02 2.00E-02 3.00E-02 4.00E-02 5.00E-02 6.00E-02 7.00E-02 8.00E-02 9.00E-02 1.00E-01 -5.00E+01 -1.00E+02 -1.50E+02 Distance (m m )

(b) PI thickness effect Fig. 11 PI Effect on LowK Stress

b) Case 1: 47um opening, 6um thick

PI geometric effect on Cu/LowK interface stress is shown in Figure 11. It is obvious that smaller opening, lower LowK interface stress from Figure 11 a). For the thickness effect, it can be seen that thinner passivation, slightly lower LowK interface stress under UBM pad, but it should also be noted on the higher stress under Al pad edge. The thickness effect is somewhat more complicate as compared to common understanding, i.e. thicker PI, lower stress. Further discussion is carried in next section. 4.4 Further discussion on PI effect To further explore the PI thickness effect, besides the previous comparison in Figure 11b) based on lager opening (47um), comparison based on smaller opening (30um) is also carried out.

c) Case 2: 30um opening, 4um thick

3.50E+02 Peak

2 Peak 1

3.00E+02 Sxy_4umThick


2.50E+02

d) Case 3: 30um opening, 6um thick Fig. 10 Stress in UBM and Al Pad

Sy_4umThick

2.00E+02

PI Opening: 47um

1.50E+02

Al pad: 73um

Sy_6umThick Sxy_6umThick

1.00E+02 5.00E+01 0.00E+00 0.00E+00 1.00E-02 2.00E-02 3.00E-02 4.00E-02 5.00E-02 6.00E-02 7.00E-02 8.00E-02 9.00E-02 1.00E-01 -5.00E+01 -1.00E+02

With comparison among Figures 10 a) to d) for the 4 cases study, it can be concluded that the thinner passivation and the smaller opening, the lower UBM stress. Overall, principal stress of Case 3 (combination of 30um opening and 6um thickness) is lower than that of control case.

-1.50E+02 Distance (m m)

(a) PI thickness effect (Larger opening 47um)


Peak 2

3.50E+02

Peak 1

3.00E+02

Sxy_30umOpen + 4umThick Sy_30umOpen + 4umThick


2.50E+02

Sy_30umOpen + 6umThick

2.00E+02

Sxy_30umOpen + 6umThick

PI Opening: 30um

1.50E+02 1.00E+02

Al pad: 73um

5.00E+01

0.00E+00 0.00E+ 1.00E- 2.00E- 3.00E- 4.00E- 5.00E- 6.00E- 7.00E- 8.00E- 9.00E- 1.00E-5.00E+01 00 02 02 02 02 02 02 02 02 02 01 -1.00E+02 -1.50E+02 Distance (m m )

(b) PI thickness effect (Smaller Opening 30um) Fig. 12 PI thickness effect (Further results) It can be seen from both Figures 12 a) and b), that there are 2 stress peaks in the LowK interface stress plot, i.e. Peak 1 related to PI opening edge, and Peak 2 related to Al pad edge. When PI opening is larger, Peak 1 is slightly higher than Peak 2; while opening is smaller, Peak 1 is obviously lower than Peak 2. It is interesting to notice that thicker PI leads to lower stress at Peak 2, but slightly higher stress at Peak 1. Peak 2


3.50E+02

opening yield less stress at Peak 1, is due to the increase of softer passivation material at the interconnection interface that can buffer more stress away. On the other side, larger PI opening which means more Cu material at the interconnection interface, can induce more stress at the Peak 1. A physical explanation of the PI thickness effect is proposed, as shown in Figure 14. After FC reflow, load is transferred from substrate to die only via pillar bumps, as there is no underfill applied. The load from cu pillar to die can be separate into two paths, i.e., path L1 of the bump peripheral and path L2 of the bump center. For path L2, load transferred from Cu pillar directly to Al pad through PI opening, while for path L1, load transferred from Cu pillar to Al pad via PI dielectric. If only PI thickness is slightly changed, while keeping all other parameters constant, the load from substrate to die can be assumed to be constant, i.e. L1+L2=constant, as overall mismatch is not changed. If PI thickness increases, load from L1 will decrease (as common sense), thus load from L2 will increase.

Peak 1

3.00E+02

Sxy_47umOpening

2.50E+02

Sy_47umOpening

L1

Sy_30umOpening

2.00E+02

Sxy_30umOpening

PI Opening: 47um

1.00E+02 5.00E+01 0.00E+00 -5.00E+01

0

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

0.1

Al pad: 73um

-1.00E+02

Fig. 14 Understanding PI Thickness Effect

-1.50E+02 Distance (mm)

(a) PI opening effect (Thinner PI 4um) 3.50E+02

Peak 2

Peak 1

3.00E+02

Sxy_47umOpen + 6umThick Sy_47umOpen + 6umThick

2.50E+02 LowK Interface Stress (MPa)

L2

PI Opening: 30um

1.50E+02

Sy_30umOpen + 6umThick

2.00E+02 1.50E+02 1.00E+02

Sxy_30umOpen + 6umThick

PI Opening: 30um PI Opening: 47um

5.00E+01 0.00E+00 0.00E+ 1.00E- 2.00E- 3.00E- 4.00E- 5.00E- 6.00E- 7.00E- 8.00E- 9.00E- 1.00E-5.00E+01 00 02 02 02 02 02 02 02 02 02 01 -1.00E+02

Al pad: 73um

-1.50E+02 Distance (m m )

(b) PI opening effect (Thicker PI 6um) Fig. 13 PI opening effect (Further results) PI opening effect is also re-examed at different PI thickness. As shown in Figure 13, PI thickness will also affect the relationship between Peak 1 and Peak 2 (i.e., which is higher) for large PI opening, and smaller PI opening leads to much lower stress at Peak 1, but has minor effect at Peak 2. The reason that smaller PI

In summary, below trend and design guidelines are achieved from simulation, 1) For lower UBM stress, passivation with lower thickness and smaller opening are preferred. 2) There are 2 stress peaks in Cu/LowK interface stress plot, i.e. Peak 1 related to UBM opening edge, and Peak 2 related to Al pad edge. This stress pattern is dependent on UBM structure design, especially PI opening and thickness, and their coupled effect. 3) Thicker PI leads to lower stress at Peak 2, but slightly higher stress at Peak 1. 4) Smaller PI opening leads to much lower stress at Peak 1, but has minor effect at Peak 2. 5) With smaller PI opening and higher thickness, the overall Cu/LowK interface stress is effectively reduced. Peak 1 stress reduced mainly by smaller opening, and Peak 2 stress reduced mainly by thicker passivation. 5. Conclusions The package reliability of a large FCBGApackage for Cu/Low-K device bumped with Cu pillar has been investigated with finite element simualtion. Multi-level


sub-modeling technique has been applied to consider the detailed Cu/Low-K structure in the chip. Comparison on Cu pillar bumps vs. solder bumps shows the former bump type generated about 20~30% higher stress on Cu/lowK structure. To improve the package reliability, design optimization is carried out on Cu pillar bump structure. DOE study has been done on Cu pillar height, PI passivation opening and PI thickness etc. Stress on Cu/low-K interface has been analyzed in detail, and it is shown that the interface stress pattern is highly dependent on UBM structure design, especially PI opening and thickness. It is interesting to see that PI opening and thickness effects are not one-directional, i.e. their effects are coupled. An overall picture of the PI effect is presented based on optimization results. Recommendations on lower Cu pillar height (appropriate for fine pitch) and smaller PI opening and higher thickness have been adopted by assembly and bumping house. Current available results with recommended smaller PI opening device show no issue after assembly. Reliability test results will be presented in a future paper. Acknowledgments Thanks to UTAC management for their guidance and support. /0

References

2.

3.

4. 5.

6.

7.

8.

Neha M. Patel 1 Vijay Wakharkar, Sairam Agrahram, et al., Flip-Chip Packaging Technology for Enabling

45nm Products 1 No. 2, Vol.12, IntelTechnology Journal, pp145-155, 2008 K. M. Chen, and T. S. Lin, “Copper pillar bump design optimization for lead free flip-chip packaging”, J Mater Sci: Mater Electron, Published online, 15 May 2009 M. Huang et al., Intermetallic formation of copper pillar with SnAgCu for flip-chip-on-module packaging. IEEE Trans. Compon.Packag. Tech. No. 7, Vol. 31, pp767–775, 2008 J. Kloeser, and E.-A. Weißbach, High performance flip-chip packages with copper pillar bumping. Global SMT Packaging, pp. 28–31, May 2006 A. Yeo, W.F. Lam, C. Lee, Development of novel joint resistance modeling technique for flip chip interconnection systems. International Electronic Manufacturing Technology conference, Malaysia, 2006, pp. 115–119 A.L.X. Jiang et al., Pillar bump technology and integrated embedded passive devices. 7th International Conference on Electronic packaging Technology, Shanghai, 2006, pp. 1–5 J.H.L. Pang et al., Thermal cycling fatigue analysis of copper pillar-to-solder joint reliability’’. 2nd Electronics System integration Technology Conference, UK, 2008, pp. 743–748 J. Yu et al., Reliability study on copper pillar bumping with lead free solder. 9th Electronic Packaging Technology Conference, Singapore, 2007, pp. 618–622
