course outline - PAMI - University of Waterloo

Department of Electrical and Computer Engineering ECE 124: Digital Circuits and Systems Winter Term 2012 COURSE INSTRUCTORS: Name Otman Basir Andrew Kennings

Class CE/EE (LEC001) SE (LEC002)

Office E5 5116 EIT 4102

Ext 36754 36909

Email [email protected] [email protected]

LAB INSTRUCTORS: Name Marcio Juliato Arash Tabibiazar

Office EIT 4141 E5 5119

Ext 37792 31470

Office E5 5111

Ext 31463

E5 5033 E5 4109

31457 31426

E5 5118 EIT 4129 EIT 4151

31469 37464 33781

Email [email protected] [email protected]

TEACHING ASSISTANTS: Name Haitham Amar Masoumeh Dadjou Mahdi Elghazali Sina Gholamian Mostafa Hassan Allaa Hilal Chirag Ravishankar Rupali Jain

ECE 124; Digital Circuits and Systems; Winter 2012

Email [email protected] [email protected] [email protected] [email protected] [email protected] [email protected] [email protected] [email protected]

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LECTURE SCHEDULE Type

Section

Fri LEC 001 12:30-1:20 (Basir) RCH302 Lectures* LEC 002 9:30-10:20 9:30-10:20 9:30-10:20 (Kennings) RCH302 RCH302 RCH302 *There are scheduled make-up lectures throughout the term. Check your schedule and/or consult the following table.

Type

Section LEC 001 (Basir)

Make-up Lectures

LEC 002 (Kennings)

Mon

#1 Jan 11 4:30-5:20 RCH 302 Jan 10 8:30-9:20 RCH 302

Tues 1:30-2:20 RCH302

Day of Week Wed

#2 Jan 25 4:30-5:20 RCH 302 Jan 24 8:30-9:20 RCH 302

Date #3 Feb 8 4:30-5:20 RCH 302 Feb 7 8:30-9:20 RCH 302

Thurs 1:30-2:20 RCH302

#4 Mar 7 4:30-5:20 RCH 302 Mar 6 8:30-9:20 RCH 302

#5 Mar 21 4:30-5:20 RCH 302 Mar 20 8:30-9:20 RCH 302

TUTORIAL SCHEDULE Type

Section

Mon

Tues

TUT101 TUT102 TUT103 Tutorials

TUT104 TUT105 TUT106


Day of Week Wed

Thurs 10:30-11:20 MC4060

Fri

3:30-4:20 MC4060 10:30-11:20 MC4060 12:30-1:20 CPH3604 12:30-1:20 CPH3604 1:30-2:20 CPH3604

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COURSE DESCRIPTION: This course will introduce the fundamentals of digital circuit design. This includes Boolean algebra and simplification of Boolean functions, combinatorial and sequential circuit design. The course has a laboratory component which will provide a basic introduction to the use of CAD tools for circuit implementation and to Field Programmable Logic Devices (FPGAs).

COURSE OBJECTIVES: By the end of the course you should have a greater appreciation of how digital circuits are designed and analyzed. You should be able to apply your knowledge to both the analysis and design of combinational and clocked digital circuits. You should have some familiarity with VHDL and hands-on experience with some FPGA design tools.

RECOMMENDED TEXTBOOKS: 1. S. Brown and Z. Vranesic, Fundamentals of Digital Logic with VHDL Design 3-rd Edition ISBN 9780-07-352953-0. McGraw Hill. 2. Laboratory Manual (all laboratory material is downloadable). Note: The recommended text book is not strictly required. However, assignment problems will be taken from this text book. The theory can be found in other text books. How to design circuits using VHDL can also be found in other books.

OTHER RESOURCES: 1. Laboratory material: http://ece.uwaterloo.ca/~ece124 2. Lecture material: http://sifaka.uwaterloo.ca/~akenning/courses/ece124. Different information will be posted on this website throughout the term. 3. LEARN.

COURSE CONTENTS: The following list is an approximate guide for the material that will be covered in this course. The material covered on a week-by-week basis will be put onto the course website. Binary logic and Boolean algebra; truth tables; Min-terms and max-terms; Canonical sum-ofproducts and product-of-sums and standard sum-of-products and product-of-sums; Logic gates. Logic minimization and Karnaugh Maps; Number representations; Addition and subtraction of signed/unsigned binary numbers. Combinational circuit design and analysis; Arithmetic circuits; Useful combinational circuits including multiplexers, priority encoders and decoders, comparators, etc. Latches and flip-flops (different types); State diagrams and state tables; Mealy and Moore finite state machines; Registers and counters. Sequential circuit design and analysis; State assignment and state reduction. Algorithmic state machines.


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Asynchronous circuit design and analysis with and without latches; State minimization of asynchronous circuits; Critical and non-critical races; race-free state assignment; Hazards and glitches. RAM, ROM and programmable logic devices. VHDL syntax. Other topics as are appropriate; e.g., timing analysis.

COURSE EVALUATION: The final course grade will be based on laboratory work, a midterm examination and a final examination. The final examination will be held during the Official Examination Period. All examinations are closed book and individual. The course has two marking schemes. If you receive >= 50% on the final examination, marking scheme #1 will be used. Otherwise, marking scheme #2 will be used. Course Component Final Examination Midterm Examination Laboratories TOTAL

Marking Scheme #1

Marking Scheme #2 50% 20% 30% 100%

80% 20% 0% 100%

You must be present to write both the midterm and final examinations to receive a numerical grade in the course. Failure to write either the midterm or final examination will result in a grade of DNW (exception by sufficient medial certificate only). You must complete all laboratory work to receive a numerical grade in the course. Failure to complete all laboratory work will result in a grade of INC.

ASSIGNMENTS: There are weekly assignments in the course which are based on end-of-chapter problems from the course textbook. Assignment problems are intended to help you learn the course material. There are no grades for assignments. Assignments will be posted on the course webpage.

LABORATORIES: The course includes 4 Lab experiments to be performed in groups of two in the E2-2356. Your time table should indicate your lab time slot. Each lab consists, more or less, of a pre-lab (which should be done prior to entering the lab), in lab experimentation, a demonstration of your work, and a post-lab report which is submitted for marking. Additional information on lab procedures and experiments are described and available at http://ece.uwaterloo.ca/~lab124 Lab reports will be due after you have demonstrated your lab. The exact due dates will be announced. Failure to submit a lab report on or before the specified due date will result in a late penalty of 10% per day.


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WORKPLACE HAZARDOUS MATERIALS INFORMATION SYSTEM (WHMIS): All students taking courses offered by the Faculty of Engineering must have appropriate instruction on issues of safety. The Workplace Hazardous Materials Information System (WHMIS) training satisfies this requirement. This requirement must be satisfied before students can be allowed to engage in lab work. In ECE124, this means it must be satisfied before the first lab session. For more info, please read http://www.safetyoffice.uwaterloo.ca/chemicals/whmis.htm.


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Academic Integrity, Grievance, Discipline, Appeals and Note for Students with Disabilities: see www.uwaterloo.ca/accountability/documents/courseoutlinestmts.pdf The text for this web site is listed below: Academic Integrity: In order to maintain a culture of academic integrity, members of the University of Waterloo community are expected to promote honesty, trust, fairness, respect and responsibility. [Check www.uwaterloo.ca/academicintegrity/ for more information.]

Grievance: A student who believes that a decision affecting some aspect of his/her university life has been unfair or unreasonable may have grounds for initiating a grievance. Read Policy 70, Student Petitions and Grievances, Section 4, www.adm.uwaterloo.ca/infosec/Policies/policy70.htm. When in doubt please be certain to contact the department’s administrative assistant who will provide further assistance.

Discipline: A student is expected to know what constitutes academic integrity [check www.uwaterloo.ca/academicintegrity/] to avoid committing an academic offence, and to take responsibility for his/her actions. A student who is unsure whether an action constitutes an offence, or who needs help in learning how to avoid offences (e.g., plagiarism, cheating) or about “rules” for group work/collaboration should seek guidance from the course instructor, academic advisor, or the undergraduate Associate Dean. For information on categories of offences and types of penalties, students should refer to Policy 71, Student Discipline, www.adm.uwaterloo.ca/infosec/Policies/policy71.htm. For typical penalties check Guidelines for the Assessment of Penalties, www.adm.uwaterloo.ca/infosec/guidelines/penaltyguidelines.htm.

Appeals: A decision made or penalty imposed under Policy 70 (Student Petitions and Grievances) (other than a petition) or Policy 71 (Student Discipline) may be appealed if there is a ground. A student who believes he/she has a ground for an appeal should refer to Policy 72 (Student Appeals) www.adm.uwaterloo.ca/infosec/Policies/policy72.htm.

Note for Students with Disabilities: The Office for persons with Disabilities (OPD), located in Needles Hall, Room 1132, collaborates with all academic departments to arrange appropriate accommodations for students with disabilities without compromising the academic integrity of the curriculum. If you require academic accommodations to lessen the impact of your disability, please register with the OPD at the beginning of each academic term.


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