Crossover Switches Cell (CSC): A New Multilevel Inverter Topology with Maximum Voltage Levels and Minimum DC Sources Hani Vahedi, Student Member IEEE, Kamal Al-Haddad, Fellow Member, IEEE, Youssef Ounejjar, Khaled Addoweesh École de Technologie Supérieure, University du Quebec GREPCI, Montreal, Canada
[email protected],
[email protected],
[email protected] [7-9]. Introducing new topologies of multilevel inverters that produce more levels at the output while using less switches and DC supplies, is a challenging part of research in this field [10, 11]. Optimizing the numbers of switches used in multilevel inverters reduces the required gate driver’s boards and consequently, the manufacturing cost will become cheaper. Pack U cell (PUC) is another topology for multilevel inverters that have lower switches and DC sources while generating more voltage levels [12, 13]. It uses six switches, one DC supply and one DC capacitor to generate seven-level inverter; however the maximum voltage value of the PUC cannot exceed the DC source voltage magnitude. In this paper, a new topology has been introduced by adding two crossover switches to the PUC inverter. The crossover switches cell (CSC) multilevel inverter uses eight switches, one DC source and one DC capacitor to generate nine levels which is the maximum possible number of levels. Besides, it can produce higher voltage levels than the DC supply voltage magnitude. The concept of multilevel inverter is described in section two. Section three contains the proposed CSC topology and its operation modes. The PWM switching technique required for the proposed nine-level CSC inverter as well as the designed voltage control strategy is clarified in section four. The simulations of proposed topology have been performed in Matlab/Simulink and the results are shown in section five that validate the efficiency of the CSC multilevel inverter.
Abstract- Renewable energy resources are widely used because of providing green and economic energy for the consumers. Multilevel inverters generates low harmonic waveforms at the output, therefore they are most suitable for energy conversion to deliver efficient power to the loads from renewable energy sources like photovoltaic systems. In this paper a new dc source less topology has been introduced for multilevel inverters. It uses crossover switches to generate the maximum output voltage levels. The Crossover Switches Cell (CSC) multilevel inverter can generate all possible voltage level among the DC supply and regulated DC voltage capacitor. A voltage controller has been proposed to keep the DC capacitor voltage regulated in case of load changes. The simulation results prove the capability of CSC in producing maximum voltage levels as well as the controller ability in balancing the capacitor voltage even if the DC supply voltage changes. Keywords: Multilevel Inverter, Packed U-Cell, Crossover Switches Cell, High Power Energy Conversion
I.
INTRODUCTION
Nowadays, research is focused and oriented toward more efficient energy conversion power electronics converters for high power applications which facilitates the integration of renewable energy resources into the grid supplying therefore high power loads and industrial consumers [1]. The power rating limit of semiconductor switches leads to low efficiency of conventional voltage source inverters (VSI) in high power applications. Therefore, multilevel inverters are widely developed that employs medium voltage switches in order to deliver high power and high voltage from DC side to the AC side [2]. Multilevel inverters are mostly employed in high power systems like: mining applications as regenerative conveyor, medical purposes like MRI gradient coil driver, hydro pump storage, STATCOM, FACTS, distributed generation, ship propulsion, train traction, aerospace and renewable energy conversion (wind and photovoltaic) [25]. Recently, low and medium power application using multilevel inverter is reported in applications like active filters because of the smooth output waveform [6]. Many topologies have been introduced while most of them have not attracted the industries. The most popular topologies are cascaded H-bridge (CHB) and neutral point clamped (NPC) which are mainly used in machine drives
978-1-4799-0224-8/13/$31.00 ©2013 IEEE
II.
MULTILEVEL INVERTER
Multilevel converters consist of several semiconductor switches and DC supplies and (or) floating capacitors. The combination of switches actions produces various voltage levels at the output to synthesis multilevel waveforms with low harmonic content. Figure 1 shows the basic concept of a multilevel inverter operation. It shows the DC link and one leg of inverter in two-level, three-level and n-level configuration. The performance of semiconductor switches is shown by ideal switches. Figure 1-a shows a conventional inverter which can produce +Vdc or –Vdc at the output point of ‘a’ with respect to the grounded neutral point, while the three-level inverter in figure 1-b produces
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+Vdc, 0 and –Vdc at the output and finally the n-level inverter in figure 1-c generates multilevel voltages of 0, ±Vdc, ±2Vdc, …. As it is depicted from the figure, the semiconductor switches voltage rating is usually less than the maximum output voltage, however the output voltage maybe more than Vdc. This feature of multilevel inverter helps the industries and renewably resources to reach high power demands and applications using medium-voltage equipment.
is V1 and the capacitor is V2. As it is shown, it can produce only seven levels which are listed in table 1. It should be mentioned that the switches in pairs of S1&S4, S2&S5 and S3&S6 turns ON and OFF in complementary of each other.
Fig. 1: One leg of a) 2-level, b) 3-level and c) n-levels inverter
Recently, multilevel inverters are gathering the researchers and industries attention due to their attractive features. Some of the major advantages of multilevel inverters are as follows [7, 14]: Lower distortion in the output voltage due to multiple levels of output waveform Lower dv/dt (voltage stress) that leads to endure the reduced voltage by switches. Lower common mode voltage which is helpful in motor drives Lower switching frequency results in lower switching losses Different kinds of multilevel inverters have been proposed and built which are mostly for medium-voltage and high power applications [4]; because of the fact that a single power switch cannot be connected to a mediumvoltage grid directly. In medium-voltage application the Neutral Point Clamped (NPC) and then the Cascade H-Bridge (CHB) have been introduced in 1980s [15, 16]. In addition to these two types, the Flying Capacitor (FC) inverter which was introduced in 1960 as a low voltage one, has been evolved to be employed in medium-voltage and high power industries in 1990 [17]. III.
Fig. 2: Single-Phase 7-Level PUC Inverter
TABLE I ALL VOLTAGE LEVELS GENERATED BY PUC
S1 1 1 1 1 0 0 0 0
S2 0 0 1 1 0 0 1 1
S3 0 1 0 1 0 1 0 1
Vab Vdc Vdc-Cdc Cdc 0 0 -Cdc Cdc-Vdc -Vdc
Although this topology has less components, it is obvious from the table 1 that the output voltage has the maximum magnitude as the DC source voltage. Therefore it is suitable for low power applications and not in high power systems where higher voltage is required at the output while using lower input DC link. Besides, as there is just one path to charge the capacitor, some problems may occur such as lack of energy for keeping the capacitor voltage constant in special states where the capacitor has been discharged and not charged for long time. The proposed CSC topology is a remedy to the mentioned problems of PUC. As it is illustrated in figure 3, the new topology has crossover switches between DC links to produce additional level of ±(V1+V2) at the output which makes it 9 levels.
PROPOSED CSC NINE-LEVEL INVERTER
The PUC inverter, introduced by Ounejjar is shown in figure 2 [18]. Assume the voltage magnitude of DC source
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TABLE II SWITCHING STATES AND VOLTAGE LEVELS OF CSC
This combination allows the capacitor to be charged in more paths which makes the DC voltage fixed and prevents it from increasing indefinitely (unstable condition), even if the DC voltage source magnitude or the load has been varied.
S1
S2
S3
S4
S5
S6
S7
S8
Output
Vab
1
0
0
0
0
1
1
0
+Vdc+Cdc
+4E
1
0
0
0
1
1
0
0
+Vdc
+3E
1
0
1
0
0
0
1
0
+Vdc
+3E
1
0
1
0
1
0
0
0
+Vdc-Cdc
+2E
0
0
0
1
0
1
1
0
+Cdc
+E
1
1
0
0
0
1
0
0
+Cdc
+E
0
0
1
1
0
0
1
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
0
0
0
0
1
0
1
0
0
0
0
1
1
1
0
0
0
-Cdc
-E
1
0
1
0
0
0
0
1
-Cdc
-E
0
1
0
1
0
1
0
0
-Vdc+Cdc
-2E
0
0
0
1
0
1
0
1
-Vdc
-3E
0
1
1
1
0
0
0
0
-Vdc
-3E
0
0
1
1
0
0
0
1
-Vdc-Cdc
-4E
TABLE III NUMBER OF COMPONENTS IN MULTILEVEL INVERTERS Topology
Diode Switch DC Source Capacitor
CHB with equal DC sources
0
16
4
0
CHB with unequal trinary DC sources
0
8
2
0
Fig. 3: single-phase 9-level CSC inverter
NPC
14
16
8
0
S7 and S8 are two bidirectional switches enabling the proposed topology to produce two extra higher levels of the output which is summation of DC supply and capacitor voltages. The all switching states of the CSC multilevel inverter are shown in table 2. Assuming that the DC supply voltage is 3E and the capacitor voltage is set to E, so the output Vab is calculated and shown in table 2. It is obvious from table 2 that the sixteen switching states generate nine levels of voltage at the output including the levels 0, ±E, ±2E, ±3E, ±4E while the DC source voltage magnitude is 3E. This means that the proposed CSC multilevel inverter can boost the output voltage and deliver higher power to the load than a standard PUC inverter. Regarding the number of required components in multilevel inverters topologies, table 3 shows the results for single-phase nine-level CHB, NPC and CSC, completely. As it is observed from table 3, the number of components in proposed CSC is less than the other topologies significantly. This fact has direct effect on manufacturing cost and its application in situations where the number of switches and DC sources are limited.
CSC
0
8
1
1
IV.
SWITCHING TECHNIQUE AND CONTROL STRATEGY FOR CSC A. Switching Technique
As explained above, for n-level multilevel inverter, n-1 carrier wave would be compared by sinusoidal wave. In two-level PWM assume the triangular wave amplitude ranges are –v to +v (shown in figure 4), and then in LevelShifted PWM, the carrier waves would have same frequency and amplitude. Note that the amplitudes of n-1 carriers are 1/(n-1) times of the carrier in two-level PWM. These carrier waves are vertically disposed such that the bands they occupy are adjacent. In order to produce the switching pulses for a nine-level inverter, eight carrier waves are required in PWM method. Figure 4 shows the diagram of carrier waves and sinusoidal reference modulation wave. According to the figure 4, each carrier (Cr1 to Cr8) generates pulses to command the associated switches in order to make the related voltage levels at the output. All carriers are compared to the reference wave, separately. For instance, if Cr1 is bigger than reference wave, the 4E
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auxiliary circuit to make additional path for capacitors currents has been reported that facilitate the energy exchanging of the capacitors to keep their voltages balanced [24]. One of the advantages of the proposed CSC topology is using less DC sources. In order to substitute a DC source by a capacitor, the voltage should be constant in all situations including healthy and faulty modes or when the load or parameter of the system changes. In this topology two PI controllers are employed to balance the capacitor voltage as shown in figure 6.
voltage level should be produced at the output. The next voltage level (3E) is generated when the reference wave is bigger than Cr2 and smaller than Cr1. The other levels are generated in similar procedure. Figure 5 shows the switching process of the proposed nine-level CSC. After comparison of carriers and reference, the required voltage level is selected. Based on the desired voltage level, the switching table send the associated pulses to the switches to generate that level at the output. Modulation Reference and Carriers Waveforms v
0
Fig. 6: control strategy for nine-level CSC
As illustrated in figure 6, at first, the capacitor voltage (V2) is compared to the reference value which is the onethird of the DC source voltage (V1) and goes to the PI controller block to minimize the capacitor voltage difference. Reference current (iref) is calculated by multiplying the first PI output by a unity sinusoidal wave. Afterwards, the derived reference current is compared to the measured load current (iload). The current difference is sent to the second PI controller to produce the modulation reference wave. This wave is the reference for logic comparator block shown in figure 5.
-v Modulation Reference Wave
Cr
1
Cr
2
Cr
3
Cr
4
Cr
5
Cr
6
Cr
7
Cr
8
Fig. 4: multicarrier PWM scheme
V.
SIMULATION RESULTS
The proposed nine-level CSC inverter has been simulated in Matlab/SimPowerSystems. The switching frequency is 1200 Hz and the RL load includes a 30Ω resistor and a 20mH inductance. The output voltage frequency is 60Hz and the DC voltage magnitude is 450V. The capacity of the DC capacitor is 4mF and it has been pre-charged. Figure 7 and 8 show the output voltage and load current. The output voltage has nine levels including 0, ±150, ±300, ±450, ±600. The voltage THD is 17.37% and the load current THD is 3.75%. in a similar condition, the output THD of a 7-level PUC inverter is 22.3%. These results demonstrate that the performance of the proposed CSC is enhanced as compared to other multilevel converters mentioned above. Also, the control strategy is efficient. The DC capacitor voltage is presented in figure 9 which shows that the controlling approach is working in an appropriate manner. Capacitor voltage has been fixed on 150V which is the one-third of the DC supply voltage. To indicate the good performance of CSC, the DC links current have been illustrated in figure 10 and 11which proves there are no short-circuit in DC supply and DC
Fig. 5: PWM technique for 9-level CSC
According to the table 2, there are some voltage levels that can be generated by various switching states e.g. 3E or 0 levels. Therefore based on the suitable transition from current switching state to the next one, the switching table block decides on next switching pulses. The mentioned point is to reduce the change in switching state for each switch leads to lower switching losses. B. Control Strategy Using a DC capacitor in multilevel inverter makes the voltage balancing inevitable. Such inverters are NPC, FC and PUC. Using a PI controller is a simple method to control the capacitor voltage while there are many proposed methods to balance the voltage [19-23]. For instance, if the levels of a NPC increase, the number of DC capacitor used in DC link raises. Therefore, the voltages of each capacitor and the middle points should be balanced to reach a smooth waveform for output voltage. Most of voltage balancing techniques are based on control methods such as PI, predictive model, fuzzy and etc. As well, using
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capacitor. The zoomed figures show the steady states of the DC links currents.
10 5 0 -5
800
Current (A)
-10
600
400
-15 -20
Voltage (V)
-25
200
-30 -35
0
-40
-200 -45 0
0.5
1
1.5
2
2.5
3
Time (s)
-400 10 5
-600
0
-800
2.03
2.04
2.05
2.06
2.07
2.08
2.09
2.1
-5
Time (s) -10
Current (A)
Fig. 7: output voltage of nine-level CSC 20
-15 -20 -25 -30
15
-35
Current (A)
10
-40 -45 1.4
5
1.41
1.42
1.43
1.44
1.45
1.46
1.47
1.48
1.49
1.5
Time (s)
Fig. 10: DC Supply Current 0 20
-5 15
-10 10
-15
5
2.03
2.04
2.05
2.06
2.07
2.08
2.09
Current (A)
-20
2.1
Time (s)
Fig. 8: load current of nine-level CSC
0 -5 -10
210 -15 200
-20 -25 0
190
0.5
1
1.5
2
2.5
3
Voltage (V)
Time (s) 20
180 15
170
10
Current (A)
160
150
5
0
-5
140 0
0.5
1
1.5
2
2.5
-10
3
Time (s) -15
Fig. 9: DC capacitor voltage in nine-level CSC
-20 1.4
1.41
1.42
1.43
1.44
1.45
1.46
1.47
1.48
1.49
1.5
Time (s)
Figure 11: Capacitor Current
Simulation results have clarified the performance of proposed CSC multilevel inverter with the designed controller and switching method. It generates the maximum output voltage levels while using minimum DC sources. 9 levels of the output voltage waveform reduce its THD and make it more similar to sinusoidal wave which reduces the power losses in electric network.
VI.
CONCLUSION
In this paper a modified topology of PUC inverter called CSC is proposed which produces the maximum voltage levels whereas using minimum DC sources and switches. In order to reduce the number of DC supplies, the DC capacitor has been used in this topology with a voltage
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[11] H. Vahedi, S. Rahmani, and K. Al-Haddad, "Pinned Mid-Points Multilevel Inverter (PMP): Three-Phase Topology with High Voltage Levels and One Bidirectional Switch," in IECON 2013-39th Annual Conference on IEEE Industrial Electronics Society, Austria, 2013. [12] K. Al-Haddad, Y. Ounejjar, and L. A. Gregoire, "Multilevel Electric Power Converter," US Patent 0280052 A1, 2010. [13] Y. Ounejjar, K. Al-Haddad, and L. A. Dessaint, "A Novel Six-Band Hysteresis Control for the Packed U Cells Seven-Level Converter: Experimental Validation," Industrial Electronics, IEEE Transactions on, vol. 59, pp. 3808-3816, 2012. [14] L. G. Franquelo, J. Rodriguez, J. I. Leon, S. Kouro, R. Portillo, and M. A. M. Prats, "The age of multilevel converters arrives," Industrial Electronics Magazine, IEEE, vol. 2, pp. 28-39, 2008. [15] A. Nabae, I. Takahashi, and H. Akagi, "A new neutral-point-clamped PWM inverter," Industry Applications, IEEE Transactions on, pp. 518-523, 1981. [16] R. H. Baker, "Bridge converter circuit," 4270163, 1981. [17] T. Meynard and H. Foch, "Dispositif électronique de conversion d’énergie électrique," France Patent, 1991. [18] Y. Ounejjar, K. Al-Haddad, and L. A. Grégoire, "Packed U cells multilevel converter topology: theoretical study and experimental validation," Industrial Electronics, IEEE Transactions on, vol. 58, pp. 1294-1306, 2011. [19] T. Hornik and Q. C. Zhong, "Parallel PI Voltage– H∞ Current Controller for the Neutral Point of a Three-Phase Inverter," Industrial Electronics Transactions, vol. 60, 2013. [20] J. Barros, F. Silva, and E. Jesus, "Fast predictive optimal control of NPC multilevel converters," 2013. [21] A. Shukla, A. Ghosh, and A. Joshi, "Improved multilevel hysteresis current regulation and capacitor voltage balancing schemes for flying capacitor multilevel inverter," Power Electronics, IEEE Transactions on, vol. 23, pp. 518-529, 2008. [22] K. Sano and H. Fujita, "Voltage-balancing circuit based on a resonant switched-capacitor converter for multilevel inverters," Industry Applications, IEEE Transactions on, vol. 44, pp. 1768-1776, 2008. [23] C. Xia, X. Gu, T. Shi, and Y. Yan, "Neutral-point potential balancing of three-level inverters in directdriven wind energy conversion system," Energy Conversion, IEEE Transactions on, vol. 26, pp. 1829, 2011. [24] Z. Shu, X. He, Z. Wang, D. Qiu, and Y. Jing, "Voltage Balancing Approaches for Diode-Clamped Multilevel Converters Using Auxiliary CapacitorBased Circuit," 2013.
controller scheme. Due to stable dynamic performance of the CSC and accurate operation of designed controller and switching pattern, the capacitor voltage has kept constant. As a result, the maximum voltage levels have been produced at the output. The simulation results prove the validity of the proposed topology in producing high voltage with nine levels containing low value of harmonics. The illustrated features of CSC makes it acceptable in energy conversion usage to boost the renewably energy resources output voltage with high efficiency. REFERENCES [1]
Enerdata. Global Energy Statistical Yearbook 2012 [Online]. Available: http://yearbook.enerdata.net/ [2] P. Samuel, R. Gupta, and D. Chandra, "Grid interface of wind power with large split-winding alternator using cascaded multilevel inverter," Energy Conversion, IEEE Transactions on, vol. 26, pp. 299-309, 2011. [3] Y. Liu, A. Q. Huang, W. Song, S. Bhattacharya, and G. Tan, "Small-signal model-based control strategy for balancing individual DC capacitor voltages in cascade multilevel inverter-based STATCOM," Industrial Electronics, IEEE Transactions on, vol. 56, pp. 2259-2269, 2009. [4] S. Kouro, M. Malinowski, K. Gopakumar, J. Pou, L. G. Franquelo, B. Wu, J. Rodriguez, M. A. Perez, and J. I. Leon, "Recent advances and industrial applications of multilevel converters," Industrial Electronics, IEEE Transactions on, vol. 57, pp. 2553-2580, 2010. [5] S. Daher, J. Schmid, and F. L. Antunes, "Multilevel inverter topologies for stand-alone PV systems," Industrial Electronics, IEEE Transactions on, vol. 55, pp. 2703-2712, 2008. [6] V. Biagini, M. Sumner, P. Zanchetta, and M. Degano, "Low Carrier-Fundamental Frequency Ratio PWM for Multilevel Active Shunt Power Filters for Aerospace Applications," 2011. [7] J. Rodriguez, J. S. Lai, and F. Z. Peng, "Multilevel inverters: a survey of topologies, controls, and applications," Industrial Electronics, IEEE Transactions on, vol. 49, pp. 724-738, 2002. [8] M. Malinowski, K. Gopakumar, J. Rodriguez, and M. A. Perez, "A survey on cascaded multilevel inverters," Industrial Electronics, IEEE Transactions on, vol. 57, pp. 2197-2206, 2010. [9] J. Rodriguez, S. Bernet, P. K. Steimer, and I. E. Lizama, "A survey on neutral-point-clamped inverters," Industrial Electronics, IEEE Transactions on, vol. 57, pp. 2219-2230, 2010. [10] H. Vahedi and K. Al-Haddad, "Half-Bridge Based Multilevel Inverter Generating Higher Voltage and Power," presented at the Electric Power and Energy Conference (EPEC), Halifax, Canada, 2013.
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