programming is done after installation, a simple interface port can be added to the PCB to ... Application Note AN555-1.
Application Note AN555-1
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Custom Silicon Solutions, Inc.
CSS555(C)
Micropower Timer (EEPROM Serial Interface)
Overview The CSS555 and CSS555C IC’s include an internal memory to store configuration and trim data. The data is stored in a non-volatile memory (EEPROM) so that the information is held even when the device is not powered. A four-wire serial interface provides Read/Write access to the EEPROM. To maintain the standard number of 555 pins, four pins have secondary functions. The alternate functions have been defined so they do not interfere with normal timer operation. The EEPROM includes an internal program voltage generator so no external high voltage signals are required to store new data. The memory access mode is initiated by forcing the CONTROL pin to GND. After the access mode is enabled, the TRIGGER, RESET and OUTPUT pins provide the Serial Clock, Data In and Data Out functions respectively. They are used to enter commands, select an address and input/output data. Each access cycle consists of an eight-bit control byte followed by eight bits of input (or output) data. A detailed description of the pin functions, commands, bit assignments and signal timing is provided in the following figures and tables. A block diagram of the interface circuit is shown below. (see Figure 1) The EEPROM data can be programmed either before or after the device is installed into the system. If programming is done after installation, a simple interface port can be added to the PCB to allow access to the serial interface pins. Several examples are shown in Figures 7-9.
Block Diagram Serial Interface Circuit Threshold
6
CSS555 IC
555C only
CT
Capacitor Trim EEPROM
8
EEOUT
100pF
Reset
4
DIN_Enbl
555C only Enbl DIN
Serial Data In CA_Enbl
Data In Register
Enbl DIN Clk
Serial Clock
Clk
EEOUT
DOUT
6
CMD
CMD
2
5
DIN
Command & Address Register
In0
ADD
Out
4
ADD
Sequence Controller Reset
Control Voltage
8
Control
4
Trigger
DOUT
Clk
Configuration EEPROM
EE Add
3
Output
In1
Read EEPROM
Sel
3
2:1 Mux
Read
7
Store CA_Enbl
CA_Enbl
DIN_Enbl
DIN_Enbl
Enable EE Access
Config In
Timer Out
Discharge
Dischg
555 Timer & Decade Counter Trig
Control
Thresh
Reset
from Analog Input Pins
Vsw ~ 0.75V
Figure 1
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Custom Silicon Solutions, Inc. ©2008
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Version 1.0, October 2008
AN555-2
CSS555
Micropower Timer (EEPROM Serial Interface)
Serial Interface Description Four pins have dual functions to provide Read and Write access to the EEPROM. The CONTROL pin is used to enable the EEPROM programming mode. The voltage at the CONTROL pin (VCONTROL) is normally set to ⅔VDD by an internal resistive divider. If VCONTROL is held below 0.5V, the programming mode is enabled. When the programming mode is active, three additional pin functions are modified to provide the “Serial Clock”, “Serial Data In” and “Serial Data Out” functions. The special pin functions for accessing the EEPROM are listed in Table 1.
Pin Number 1 2 3 4 5 6 7 8
Pin Name VSS TRIGGER OUTPUT RESET CONTROL THRESHOLD DISCHARGE VDD
Pin Function Primary or Secondary or Timer Mode EEPROM Program Mode GND GND Start Timer Serial Clock Timer Output Pulse Serial Data Out Stop Timer Serial Data In Upper Trip Level (⅔VDD) Program Enable Upper Comparator Input CT Discharge FET Positive Supply Positive Supply
Table 1 In the programming mode, the serial clock is provided by the TRIGGER pin. The RESET pin becomes “Serial Data In” and “Serial Data Out” is provided by the OUTPUT pin. In the normal timing mode, the TRIGGER input is connected to the inverting input of the lower comparator and its switch level is (½ V CONTROL). In the programming mode, the TRIGGER input drives a standard CMOS digital input. Its switch level is approximately (½ V DD). All access cycles start by forcing the CONTROL pin low and shifting in an eight-bit control byte. (see Figures 2 and 3) The control byte contains a four-bit command and a four-bit address. The command portion is used to specify either a Read or Write cycle. The address portion selects the location to be accessed. A summary of the interface commands is provided in Table 2. If a Read command is entered, the next eight clocks shift the contents of the selected address onto the OUTPUT pin. (Configuration bit assignments are shown in Table 3. Capacitor trim bits (CSS555C only) are entered LSB to MSB.) If a Write command is entered, new data is loaded during the next eight clocks and it is th programmed into the EEPROM during the 9 clock pulse. The access cycle is terminated when the CONTROL pin is released. (The internal divider will pull it up to ⅔VDD and the normal timer mode will be re-established.)
Interface Commands (Control Byte) Control Byte Mode Normal Read EE1 Read EE2 (Note1) Store EE1 Store EE2 (Note1)
Control Pin > 1.0V < 0.5V < 0.5V < 0.5V < 0.5V
Description 555 Timing mode Read Configuration Data Read Capacitor Trim Data Program Configuration Data Program Capacitor Trim Data
MSB
Address xxxx 0001 0010 0001 0010
LSB
Command xxxx 0001 0001 0010 0010
Table 2
Note1: CSS555C only
Configuration Bits (Data Byte) Counter Configuration MSB
LSB
xxxxx000 xxxxx001 xxxxx010 xxxxx011 xxxxx100 xxxxx101 xxxxx110 xxxxx111
Mode Control
Counter Setting (Multiplier) 1 (Std. 555) 10 100 1K 10K 100K 1M 1 (Std. 555)
MSB
LSB
xxxx0xxx xxxx1xxx xxx0xxxx xxx1xxxx xx0xxxxx xx1xxxxx Bit 6 Bit 7
Function Astable Mode (“Don’t Care” if Std. 555) Monostable Mode (“Don’t Care” if Std. 555) Micro Power Low Power Standard Voltage (Trip levels = ⅓ & ⅔ VDD) Low Voltage (Trip levels = 10% & 90% VDD) Unused 0 if 555, 1 if 555C (Read only)
Table 3
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Version 1.0, October 2008
AN555-2
CSS555
Micropower Timer (EEPROM Serial Interface)
Timing Diagrams Read EEPROM (1 Byte) PROGEN
Control Byte
Control Pin
Data Byte
Enter Command & Address
Read EE Data
SCLK Trigger Pin
DATA IN Reset Pin
X
C0
C1
C2
C3
DATA OUT
A0
A1
A2
A3
X
Counter Output
Output Pin
EE ADDR Internal Buss
EE READ
ED0
ED1 ED2 ED3 ED4 ED5 ED6 ED7
Counter Output
EA0
EA1 EA2 EA3 EA4 EA5 EA6 EA7
X
Read EE (Configuration or Cap Trim Byte)
Internal Signal
Figure 2
Program EEPROM (1 Byte) PROGEN
Control Byte
Control Pin
Data Byte Enter New EE Data
Enter Command & Address
Store ~10ms
SCLK Trigger Pin
DATA IN Reset Pin
DATA OUT Output Pin
X
C0
C1
C2
C3
A0
A1
A2
A3
X
ED0 ED1 ED2 ED3 ED4 ED5 ED6 ED7
Counter Output
Counter Output
EE ADDR
EA0
Internal Buss
EE STORE
EA1 EA2 EA3 EA4 EA5 EA6 EA7
X
Enter New EE Data & Program 1 Byte
Internal Signal
VPP (~20V)
Store
Internal Signal
Figure 3
Program Byte1, Data = 2B (hex), Read Byte1 PROGEN
Read Data
Load Data & Program
Control Pin
Control = 12 hex
SCLK
Store ~10ms
Data In = 2B hex
Data Out = 2B hex
Control = 11 hex
Trigger Pin CMD
DATA IN Reset Pin
X
LSB
DATA OUT Output Pin
ADD
0 1 0 0 1 0 0 0 LSB
DATA IN 1 1 0 1 0 1 0 0
CMD X
X
LSB
LSB
Counter Out
Counter Out
ADD
1 0 0 0 1 0 0 0
X
LSB
DATA OUT 1
1 0 1 0 1 0 0
Counter Out
LSB
EE READ
Read Byte1
Internal Signal
EE STORE Internal Signal
Enter Data & Program Byte1
VPP (~20V)
Store
Internal Signal
Figure 4
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Version 1.0, October 2008
AN555-2
CSS555
Micropower Timer (EEPROM Serial Interface)
Serial Interface Timing Specifications VDD = 1.5V to 5.5V, Temperature = -40°C to +85°C Parameter Symbol Conditions
Min
Typ
Serial Clock Period Serial Clock High Time Serial Clock Low Time Serial Clock Rise/Fall Times Data In Setup Time
tCLKP tCLKH tCLKL tR, tF tDSU
50% duty cycle Rising to falling edge Falling to rising edge 20% to 80%, 80% to 20% Data valid to rising clock edge
500 250 250
200 100 100
Max
50
25
ns ns ns ns ns
Data In Hold Time Mode Lead Time Data Output Delay Time EEPROM Store Time
tDHD tMLD tDOD tSTR
Falling clock edge to data invalid Control pin low to first clock edge Rising clock edge to Data Out valid Clock low time (17th pulse)
50 1000
25 500 50 10
ns ns ns millisec
100
25
100 100
Units
Note 1: Typical values are for operation at 3V, 25°C Note 2: Data Output Delay Time (tDOD) measured with CLOAD = 10pF and RLOAD = 1MΩ.
Table 4
Serial Interface Timing Diagram Read Mode Read EE Data (8 clock cycles)
Enter Command & Address (8 clock cycles) tCLKL
EEMODE
tCLKH
Exit EE Mode
tCLKP
Control Pin tMLD
SCLK Trigger Pin tDSU
DATA IN
tDHD CMD0
Reset Pin
CMD1 tDOD
DATA OUT
DOUT0
Timer Out
Output Pin
DOUT1
DOUT2
Timer Out
Figure 5
Program Mode Store 1 Byte into EEPROM (17th clock pulse)
Enter Command, Address & Data (16 clock cycles) tCLKL
EEMODE
tCLKH
Exit EE Mode
tSTR
Control Pin tMLD
SCLK Trigger Pin tDSU
DATA IN Reset Pin
DATA OUT Output Pin
tDHD CMD0
CMD1
Timer Out
Timer Out
Figure 6
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Version 1.0, October 2008
CSS555C
Micropower Timer (EEPROM Serial Interface)
Serial Interface Examples
Programming After Installation
The CSS555’s serial interface is very straightforward and requires minimal extra components to implement. It consists of three digital input signals that provide control, clock and data input functions and a single digital output that allows data to be read back from the device. The hardware needed to program the EEPROM depends on whether the IC is “loose” or has been installed in a system. Examples for both conditions are shown in Figures 7, 8 and 9.
If the CSS555 has been installed into a system, the changes required to implement the serial interface are still relatively minor. An example of one approach is shown in Figure 9. Test points TP1-TP4 have been added to provide access to the TRIGGER, RESET, CONTROL and OUTPUT pins. If three-state buffers are used to generate the test signals, the device can still be operated in the timer mode. In addition to the test port, resistors R1 and R2 have been added to allow the external ATE or “Programmer” to control the TRIGGER and RESET signals. Since these pins are high impedance CMOS inputs, the additional series resistance will not affect their operation or increase the operating current of the circuit. A value between 10KΩ to 100KΩ is suggested for R1 and R2.
Programming Before Installation The circuit in Figure 7 shows a diagram for an interface schematic between an ATE (Automatic Test Equipment) and an uninstalled or “loose” IC. This example allows data to be written to and read from the internal EEPROM. No external components are required for this programming setup. (The timing components RA, RB and C have been omitted.) A.T.E.
System PCB
VSS
Trigger Timer Out +V/Reset
+V CSS555
GND
VSS
R1
TP1
R2
RA
VDD
Trigger Dischg
TP2
RB
Output Thresh
TP3
TP4 Reset Control
VDD
C
SCLK Data Out
Trigger Dischg
NC
Output Thresh
NC
Data In
Reset Control
Program Enable
VDD CSS555
Test Port
Figure 9 Program and Read “In the System”
VCONTROL
Figure 7 Program & Read EEPROM Only If the timer function also needs to be tested, the circuit in Figure 8 shows an interface circuit that supports the Read, Write and Timer operating modes. The timing components RA, RB and C have been added. The output driver that provides the VCONTROL signal has been changed to a threestate output buffer. The normal timer mode is enabled when the VCONTROL buffer is disabled (OE=0). This allows the IC to set the voltage level at the CONTROL pin, which is about ⅔VDD. A timer cycle is started by pulsing SCLK (Trigger) low. (Reset/Data In must be held high.)
A.T.E.
+V CSS555
GND
VSS
SCLK Data Out Data In
Output Thresh
RB
Reset Control
C
OE Program Enable
RA
VDD
Trigger Dischg
VCONTROL
Figure 8 Program, Read and Timer Functions
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Version 1.0, October 2008
Custom Silicon Solutions, Inc. ©2008
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Ver. 1.0 – October 2008
