Current-Fed High-Frequency AC Distributed Power ... - IEEE Xplore

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 60, NO. 9, SEPTEMBER 2013

Current-Fed High-Frequency AC Distributed Power System for Medium–High-Voltage Gate Driving Applications Huiqing Wen, Weidong Xiao, Member, IEEE, and Zhengyu Lu, Senior Member, IEEE

Abstract—A current-fed high-frequency alternating-current (HFAC) distributed power system is presented in this paper for medium- or high-voltage gate driving applications. The distributed gate driving modules (GDMs) at the high-voltage side are isolated from the low-voltage-side current-source power supply through magnetic coupling of current transformers (CTs), which are assembled by a high-voltage cable carrying HFAC and passing through the center of toroid magnetic cores. The centralized high-frequency current-source power supply is designed and composed of a two-stage resonant inverter and a double Γ-CL resonant network. The resonant network is parameterized by considering the tradeoff between the quality factor and component stress. Different magnetic core samples are tested and compared to construct the CTs for improving transmission efficiency. A 400-W prototype was built and experimentally evaluated with two load conditions, including resistive loads and practical GDMs. It showed significant improvements with regard to sinusoidal current output, system stability, and efficiency. Finally, the proposed current-fed HFAC power supply system was successfully applied to a practical solid-state fault current limiter, demonstrating the advantages of multiple outputs (n > 10), high-voltage isolation, low harmonic distortion, high efficiency, easy installation, and flexible extensibility. Index Terms—Gate driving system, harmonic, high-frequency alternating current (HFAC), high-voltage isolation, multiple outputs, resonant network.

A BBREVIATIONS HFAC DPS SSFCL CHFCS SSSVR GDM TSRI CT

High-frequency alternating current. Distributed power systems. Solid-state fault current limiter. Centralized high-frequency current-source current limiter. Secondary-side shunt voltage regulator. Gate driving module. Two-stage resonant inverter. Current transformer.

Manuscript received January 16, 2012; revised May 5, 2012; accepted June 15, 2012. Date of publication July 10, 2012; date of current version May 2, 2013. H. Wen and W. Xiao are with Masdar Institute of Science and Technology, Abu Dhabi, United Arab Emirates (e-mail: [email protected]). Z. Lu is with the College of Electrical Engineering, Zhejiang University, Hangzhou 310027, China (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TIE.2012.2207659

FB GDPS

Full bridge. Gate drive power supply. N OMENCLATURE

Ldc TFCL T1 −T8 Za(b,c) ua(b,c) Vin S1 −S5 io → − Io vo is2,5 Tb Db iLo ILo Req fhb ω ωr β Z F |Z| ψ g |g| θ Q is is1 vC1 vC1,1 iC1 iC1,1 Tr μr Lm vps vss iss Iins

DC limiting inductor of the SSFCL. Transformer of the SSFCL. Thyristors of the SSFCL. Load impedance of the SSFCL. Grid phase voltage of the SSFCL. Input voltage of the TSRI. MOSFETs of the TSRI. Output current of the TSRI. Vector representation of output current io . Output voltage of the TSRI. Transient current through switches S2 and S5 . Switching period of the buck converter. Duty cycle of the buck converter. Transient current through inductor Lo . Average value of the current through inductor Lo . Equivalent load resistance. Switching frequency of the FB converter. Angular frequency of the FB converter. Resonant angular frequency of the network. Ratio of ω and ωr . Input impedance of the resonant network. Ratio of active and reactive parts of Z. Magnitude of input impedance Z. Phase angle of input impedance Z. Current transfer function of the resonant network. Magnitude of current transfer function g. Phase angle of current transfer function g. Quality factor of the resonant network. Input current of the resonant network. Fundamental component of is . Voltage across C1 of the resonant network. Fundamental component of vC1 . Transient current through C1 . Fundamental component of iC1 . CTs. Relative permeability of Tr . Magnetizing inductance of Tr . Primary voltage of the CTs Tr . Secondary voltage of the CTs Tr . Secondary current of the CTs Tr . Input current of the SSSVR.

0278-0046/$31.00 © 2012 IEEE

WEN et al.: CURRENT-FED HFAC DPS FOR MEDIUM–HIGH-VOLTAGE GATE DRIVING APPLICATIONS

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Fig. 2. Schematic of the SSFCL using stacked thyristors.

Fig. 1. Architecture of HFAC power distribution system: (a) voltage-fed; (b) current-fed.

Dsb Tsb M S1 DS1 Cso Vso

Duty cycle of the SSSVR. Switching period of the SSSVR. MOSFET of the SSSVR. Diode of the SSSVR. Output capacitor of the SSSVR. Output voltage of the SSSVR. I. I NTRODUCTION

HFAC systems that were originally proposed for aerospace power supplies [1] have been recently attracting a lot of attention in the applications of uninterruptible power supplies [2], personal computers [3], telecommunication [4], vehicles [5], electronic transformers [6], microgrids [7], [8], and DPS [9]–[12]. The HFAC architecture shows the advantages of simple structure, low cost, small component count, and effective ground noise isolation in comparison with its counterpart dc DPS [13]–[15]. The conventional HFAC DPS is voltage fed and based on the high-frequency voltage bus, as shown in Fig. 1(a). The architecture consists of the front-end inverters and distributed back-end output rectifier modules for point-of-use management. The output rectifier modules are parallel connected to the high-frequency alternating-voltage bus via the transformers, which transmit energy to individual loads. However, this voltage-fed HFAC architecture is not suitable for medium–high-voltage gate driving applications. The GDPS requires multiple outputs (n > 10) and high-voltage isolation for the medium–high-voltage applications, which include SSFCLs, static synchronous compensators [16], HVdc transmission [17], and adjustable-speed drives [18]. These systems usually require a large number of high-power switching devices such as thyristors, gate turn-off thyristors (GTOs), insulated gate bipolar transistors (IGBTs), and integrated gate-commutated thyristors (IGCTs) to meet system operating voltage requirements. Stack structures are commonly adopted so that each high-power

switching device in the stack only bears a small part of the system operating voltage. For example, 35 switching devices were reported to be used for the eight-level reinjection converter [16]. In short, the voltage-fed HFAC architecture demonstrates the following constraints for the above applications: 1) the limited number of output modules due to the reliability issue caused by output module interaction; 2) the insulation property of conventional voltage transformers that restricts the application for medium–high-voltage systems. The solution for medium–high-voltage GDPS can be achieved by specially designed transformers [19]–[23]. A special transformer with distributed windings was reported in [19], which provides high-voltage insulation for up to 4500 V. Other approaches have been proposed to meet the voltage insulation requirement, which include the coreless printed-circuit-board transformer [20], the piezoelectric transformer [21], [22], and the oil-immersed transformer [23]. In addition, a special design of the medium–high-voltage isolated power supply for gate driving the IGCTs was reported in [24]. However, the above solutions can only support a limited number of GDMs, usually six or less. Furthermore, the system structure is inflexible for on-site installation. As a result, this paper focuses on a currentfed HFAC architecture to meet the medium–high-voltage gate driving requirements. As shown in Fig. 1(b), the output modules of the current-fed HFAC are series with the HFAC bus, which distributes power to point-of-use loads through the CTs. Fig. 2 shows the schematic of a thyristor-based SSFCL, which is a protection system to limit the short-circuit current in electric power systems [25], [26]. In normal status, the thyristors of the SSFCL, i.e., T1 −T8 , are gated in full conduction and the equivalent impedance of the SSFCL is very low. When a short-circuit fault occurs, the dc limiting inductor Ldc can limit the rise rate of the short-circuit current. Then, the trigger angle of gate driving pulses for T1 −T6 is controlled, and the short-circuit current is regulated to gradually decrease to zero. Considering that the operating voltage of the practical SSFCL is high up to 15 kV [27], high-voltage isolation is essential to design the GDPS for such high-voltage applications. Each symbol of T1 −T8 represents a stack of eight series-connected thyristors, as shown in Fig. 2. The total number of thyristors is 64 in the practical SSFCL system-0083 to handle the rated dc bus voltage of 15 kV. Consequently, the SSFCL system requires 61 gate drive power supplies in total since four common-ground thyristors can share one power supply module.

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To address the difficulties shown above, the current-fed HFAC architecture shown in Fig. 1(b) is adopted in [28]– [30] and shows that it is superior to the counterpart voltagefed architecture due to the capability of supporting multiple thyristor gate drivers and high-voltage isolation. The prior work validates the feasibility of implementing the current-fed HFAC DPS for medium–high-voltage applications. However, the previous design shows the following drawbacks. 1) The output current is a square wave, and the total harmonic distortion (THD) is high. This will cause highfrequency radiation and introduce serious electromagnetic interference (EMI). 2) A 25-Ω resistor must be series connected along the primary winding of the CT to improve the stability margin of the DPS for light-load conditions. This extra resistor produced additional power loss and degrades the system efficiency of the GDMs, which is lower than 40% for the light-load condition. 3) The efficiency of the SSSVR is low due to the linear voltage regulation techniques [30]. Thus, a bulky heat sink should be implemented to dissipate heat generated from the power loss. The size and weight of the back-end GDMs also cause inflexibility for on-site installation. This paper presents an improved GDPS system that adopts the current-fed HFAC architecture and meets the requirements of high-voltage isolation, multiple outputs, good extensibility, and installation flexibility. Other performance metrics of the GDPS system in terms of output current THD, system stability margin, and efficiency are also greatly improved. The organization of this paper is shown as follows. Section II introduces the overall gate driving system, which is composed of a current-fed HFAC power supply system and an optical-fiber communication subsystem for transmitting gate signals. Section III shows the topology and operation modes of the CHFCS, which combines a TSRI with a double Γ-CL resonant network. The optimal parameters of the resonant network are determined by analyzing the tradeoff between the quality factor of the proposed resonant network and stresses on the main components. In Section IV, the requirement for CTs is outlined and the major parameters of selecting the magnetic core materials are discussed. A switched-mode SSSVR is proposed to replace traditional linear SSSVRs to achieve high efficiency for the GDMs’ design. Section V illustrates the experimental evaluation of a 400-W current-fed HFAC power supply prototype with two load conditions, including the resistive load and several practical GDMs. The CTs with various magnetic core samples are compared according to their transmission efficiency. The prototype system is tested with a practical 400 V/300 A SSFCL system, which is designed to limit a 1500-A short-circuit current. The experimental results validate the effectiveness of the proposed current-fed HFAC power supply system for medium- or high-voltage gate driving applications. II. G ATE D RIVING A RCHITECTURE FOR SSFCL The proposed gate driving architecture is composed of two systems, namely, the current-fed HFAC power supply system

Fig. 3. Medium–high-voltage gate driving architecture with independent transmission of HFAC energy and gate signals.

and the optical-fiber communication system for transmitting gate signals, as shown in Fig. 3. The gating signals are produced by the central controller and transformed to optical signals, which are resistant to external EMI. The GDMs transform the optical signals to electrical gate driving pulses, which are sent to the gates of high-power switching devices. The mechanism is commonly named as the optically activated gate control [31]. The proposed current-fed HFAC power supply system is composed of three subsystems, which are located on different voltage sides: a CHFCS at the low-voltage side and CTs and SSSVR for each GDM at the high-voltage side. The HFAC produced by the CHFCS is transmitted by the high-voltage cable, which passes through the center of CTs. The structure of CTs includes a toroid magnetic core, primary windings, and secondary windings. The primary side of CTs has only one-turn winding for on-site installation convenience. The energy required by the GDMs is obtained by magnetic coupling of CTs. The proposed gate driving architecture shows the following advantages: 1) high-voltage isolation because the HFAC and gate signals are independently transmitted by the high-voltage cable and fiber optic cables; 2) good system extensibility considering that the current-fed HFAC architecture is adopted and the GDMs are series with the high-frequency current bus; 3) on-site installation flexibility because the location of the GDMs can be freely arranged and is close to the switching devices; and 4) high reliability since each GDM is individually controlled and the mutual interference among GDMs is significantly reduced. III. H IGH -F REQUENCY C URRENT S OURCE The CHFCS is located at the low-voltage side, which converts the input dc power to HFAC. The design should meet the following requirements: 1) regulated HFAC current with constant frequency; 2) power capacity to support all GDMs; 3) low magnetizing current of the CTs for high transmission efficiency; 4) low harmonic current for attenuating EMI; and 5) high efficiency for a wide operating range. In this section,


Fig. 4.

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Current-fed parallel resonant network.

the topology and operation modes of TSRI are presented. The double Γ-CL resonant network is proposed, analyzed, and parameterized according to the above requirements. A. TSRI Topology To avoid the drawbacks shown in the previous development [28]–[30], a resonant network is added to link the FB converter and the CTs. Among the various structures of the resonant network [32]–[38], the current-fed parallel resonant network composed of two energy storage elements [32]–[34] is investigated and shown in Fig. 4. The resonant impedance Zlc of inductor Lp and capacitor Cp regarding switching frequency is expressed by (1), which can be simplified as a magnitude–angle notion Zlc (ω) =

jωLp jβReq = 2 1 − ω Lp C p (1 − β 2 )Q

(1)

Zlc (ω) = |Zlc (ω)| ∠ϕ

(2)

where β=

ω ωr

Q=

Req ω r Lp

ωr =

1 Lp C p

π βReq ϕ = sign(1 − β) · . 2 Q|1 − β | 2 The parameters of a parallel resonant network are determined by considering the tradeoff between resonant impedance |Zlc | and quality factor Q. A large Q is preferable for the resonant network to filter the input square-wave current is into an ideal sinusoidal current signal io . However, increasing Q results in a decreased |Zlc |, which introduces a rapid increase in current stress. The current-fed parallel resonant network shows the following drawbacks: 1) The operating point at the resonant frequency should be avoided due to the catastrophic electrical stresses of the components at this resonant point; and 2) the filtering effect of the resonant network is valid only for a limited load range; therefore, the THD of the output current waveform at a light-load condition is high. A three-energy-storage-element resonant network is recommended for designing radio-frequency circuits, including πtype [35], T-type [36], and LLC structure [37]. However, these networks also show the drawbacks of parasitic resonance, lowcurrent transfer gain, high THD, and high power losses [38]. These drawbacks can be overcome by adding a fourth energy storage element. In this paper, a cascaded double Γ-CL resonant network shown in Fig. 5 is proposed for the high-frequency current-source design. Fig. 6 illustrates the CHFCS circuits comprising the currentfed TSRI and the double Γ-CL resonant network. The first stage is a buck converter, which provides the regulated dc |Zlc (ω)| =

Fig. 5. Proposed double Γ-CL resonant network.

current. The second stage is an FB converter that generates the HFAC current and outputs it to the double Γ-CL resonant network. Compared with the topologies proposed in [39] and [40], the TSRI topology is expected to minimize the THD of the output current by applying a fixed duty ratio switching strategy and a properly tuned fourth-order resonant filter. B. Operation Modes Analysis The operation modes are analyzed and based on the following assumptions: 1) the antiparallel diodes and parasitic capacitors are included in the model of MOSFETs; 2) the parasitic resistances in the circuit are neglected; 3) the switching transients of MOSFETs, such as the Miller effect and tail current, are neglected; and 4) the current distribution is uniform between the two legs when all MOSFETs of the FB converter are in the ON state. Fig. 7(a) illustrates the typical waveforms and operation modes of the TSRI, where vgs represents the MOSFET gate signals for switches S1−5 . The duty cycle of the gate signals vgs2−5 is set to be higher than 50% in order to avoid an open circuit of the current-source converter. In Fig. 7(a), td represents the overlap time of the FB converter in one switching period, and vC1 represents the voltage across capacitor C1 of the resonant network, which links to the output of the FB converter. Tb represents the switching period of the buck converter. The transient current through switches S2 and S5 and the voltage signals across switches S2 and S5 are symbolized as is2,5 and us2,5 , respectively. The switching frequency of the buck converter is set to twice the switching frequency of the FB converter. The operation mode of the TSRI can be analyzed as follows. Interval [t0 −t1 ]: Switches S1 , S2 , and S5 are switched on. The current through S2 (or S5 ) is the same as the inductor current iLo . The voltages across S2 and S5 , i.e., us2,5 , become low ON-state voltages. Inductor Lo is charged. The equation can be written as Lo · diLo /dt = Vin − vC1 .

(3)

Interval [t1 −t2 ]: Switch S1 is switched off. S2 and S5 remain in ON state. Diode D1 is in ON state and forms a freewheeling current path. Lo is discharged as Lo · diLo /dt = −vC1 .

(4)

Interval [t2 −t3 ]: Switches S2 , S3 , S4 , and S5 are in the ON state. Diode D1 remains in the ON state to form a freewheeling current path. The current of inductor Lo shows no change. The current through S2 (or S5 ) is regarded as half of the inductor current iLo .

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Fig. 6. Topology of current-fed TSRI.

Based on the voltage-second balance of the inductor Lo in one switching period, the equation can be derived as Ts Db Vin Ts =

vC1 dt.

(5)

0

Voltage vC1 is time varying and depends on the current flowing into capacitor C1 . Based on the above analysis, the voltage stresses of the FB switching devices S2 , S3 , S4 , and S5 depend on voltage vC1 , which is dependent on the characteristics of the resonant tank. The vC1 dynamics will be further discussed with the characteristics analysis of the double Γ-CL resonant network. When the inductor and the switch losses of the TSRI are neglected, the average inductor current ILo can be written as ILo = (Io )2 Req /(Db Vin )

(6)

where Req represents the equivalent load resistance. Equation (6) shows that the duty cycle of the buck converter is the control variable to regulate the inductor current ILo . Due to the high inductance of Lo in the TSRI, current ILo can be considered as a constant dc current. Therefore, the current stress on the FB switching devices S2 , S3 , S4 , and S5 is low. In addition, the proposed TSRI topology can effectively prevent the overcurrent fault of the CHFCS supply. The waveforms of is2,5 and us2,5 in Fig. 7(b) indicate that S2 and S5 experience zero-voltage-switching (ZVS) turnoff since the voltage across S2 and S5 us2,5 increases from zero after current is2,5 reduces to zero. Similarly, switches S3 and S4 can experience ZVS turnoff. C. Double Γ-CL Resonant Network

Fig. 7. Typical waveforms and operation modes of the proposed current-fed TSRI: (a) typical waveforms; (b) operation modes.

Interval [t3 −t4 ]: Switches S2 and S5 are switched off. The other two switches S3 and S4 are in the ON state. Inductor Lo is discharged. The Lo current decreases in a similar manner as that in interval [t1 -t2 ] and is expressed as (4). Interval [t4 −t5 ]: Switches S1 , S3 , and S4 are in the ON state, and inductor Lo is charged. The current of Lo increases in a similar manner to interval [t0 -t1 ] and is expressed as (3).

The proposed double Γ-CL resonant network consists of four energy storage elements, i.e., C1 , L1 , C2 , and L2 . Input current is is a square-wave current with the amplitude alternating between −ILo and +ILo . For circuit analysis, Req is the equivalent load resistance, which can represent the actual power consumption of the GDMs. Considering that the double Γ-CL resonant network is a fourth-order system, the input impedance and the input–output current transfer function of the resonant network are generally complex and the proper parameters of the resonant components are also difficult to determine. Furthermore, the design of a


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four-energy-storage-element resonant network, which covers various combinations of the four parameters, is not discussed in previous literature works. Thus, in the practical design, inductances L1 and L2 are set to be the same as L and capacitance values C1 and C2 are the same as C in order to simplify the resonant network design. As a result, the input impedance of the resonant network can be expressed by either (7) or a magnitude–angle notion F (1 − β 2 ) + jβ(2 − β 2 ) Req F (1 − 3β 2 + β 4 ) + jF 2 β(2 − β 2 ) Z(β) = |Z|∠ψ

Z(β) =

(7) (8)

where ω ωr

Req 1 F = = Req ωr C ωr = √ ωr L LC F 2 (1 − β 2 )2 + β 2 (2 − β 2 )2 |Z| = Req 2 F (1 − 3β 2 + β 4 )2 + F 4 β 2 (2 − β 2 )2 2 β(2 − β 2 ) −1 F β(2 − β ) − tan . ψ = tan−1 F (1 − β 2 ) (1 − 3β 2 + β 4 ) β=

Symbols ω, ωr , F , and β represent the angular frequency of the FB converter, the resonant angular frequency of the double Γ-CL resonant network, the ratio of active and reactive parts of the input impedance Z, and the ratio of ω and ωr , respectively. In order to determine the parameters of the resonant network, the characteristics of the three parameters, including Z, β, and F , should be analyzed. The resonant point of the resonant √ network is determined at β = 2 according to (7) because at the operating point, the magnitude of input impedance |Z| is equal to Req and the phase angle of input impedance ψ is equal to 0 for any value of F . Fig. 8 illustrates the characteristics of the magnitude |Z| and phase angle ψ against parameter β with respect to various F values. It is noticeable that the ratio of |Z|/R √ eq is 1 and the phase angle ψ is 0 when parameter β is set to 2. The current transfer function of the resonant network is represented by io (β) = |g|∠θ is1 (β)

Fig. 8. Characteristics illustration of input impedance magnitude |Z| and phase angle ψ of the proposed double Γ-CL resonant network versus parameter β: (a) |Z|/Req versus β; (b) ψ versus β.

(9)

where |g| =

1

(1 − 3β 2 + β 4 )2 + F 2 β 2 (2 − β 2 )2 F β(2 − β 2 ) . θ = − tan−1 (1 − 3β 2 + β 4 )

Symbol is1 represents the fundamental component of input current is . From (9), the magnitude√of the current transfer function |g| is always unity if β = 2 for any value of F . Similarly, the magnitude of the current transfer function |g| and the phase angle of the current transfer function θ against parameter β, with √ respect to various F , are characterized in Fig. 9. When β = 2, the magnitude |g| becomes unity and the phase angle θ is 180◦ , regardless of the value of F . Based on the above analysis, the switching angular frequency of the FB converter ω can be set exactly to the resonant angular frequency ωr without inducing catastrophic stresses

Fig. 9. Characteristics illustration of the current transfer function magnitude |g| and phase angle θ of the proposed double Γ-CL resonant network versus parameter β: (a) |g| versus β; (b) phase angle θ versus β.

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→ − −−→ 2 VL1 = −β + jβ(1 − β 2 )/F Req Io

(14)

→ − −−−→ VC1,1 = 1 − β 2 + jβ(2 − β 2 )/F Req Io

(15)

− → −−−→ IC1,1 = jF (1 − β 2 )β − (2 − β 2 )β 2 Io

(16)

− → −→ Is,1 = jF (2 − β 2 )β − (3 − β 2 )β 2 + 1 Io .

(17)

Based on Fig. 10, the expression of α and ϕ with respect to parameters F and β can be written as

Fig. 10. Phasor diagram for voltage and current vectors of the proposed double Γ-CL resonant network.

on switching devices and resonant components, which is the main drawback of the parallel resonant network. Considering the component parameter variations due to the manufacturing process and the effect of operating temperature, the actual β varies from 1.3 to 1.5.

D. Stresses for Main Components In order to determine the range of F , the stress on the switching devices and the resonant components is analyzed. As shown in Fig. 7, the constant current ILo flows through the FB switching devices S2 , S3 , S4 , and S5 . Thus, the current stresses of these devices are low. The voltage stresses are dependent on voltage vC1 , which shows time-varying characteristics and depends on the capacitor current dynamics. The stress analysis should consider both the fundamental and harmonics components since capacitor C1 shows a filtering effect to the high-order harmonics. For other resonant components C2 , L1 , and L2 , only the fundamental component is considered for the stress analysis because the high-frequency harmonics are insignificant. The symbols defining the important current and voltage are illustrated in Fig. 5. The corresponding current and voltage vectors with respect to the output current vector of the TSRI → − Io are illustrated as a phasor diagram shown in Fig. 10. The relationship of these vectors can be expressed as follows accordingly:

Z=

→ − −−→ VL2 = jβReq Io /F

(10)

−−→ → − VC2 = (1 + jβ/F )Req Io

(11)

−→ → − IC2 = (jF β − β 2 ) Io

(12)

−→ → − IL1 = (jF β − β 2 + 1) Io

(13)

sin α = β/ F 2 + β 2 sin ϕ = 1/ (F β)2 + (1 − β 2 )2

(18) (19)

−−−→ where VC1,1 represents the voltage vector of vC1,1 , and −−−→ −→ IC1,1 and Is,1 represent the current vector of iC1,1 and is,1 , respectively. Based on (17), the RM S value of input fundamental current Is,1 can be expressed with respect to the RM S value of output current Io . Considering that the input current of the resonant network shows square waveform, the expression of the input current harmonics can be derived based on the expression of the fundamental component. Therefore, the Fourier series expression of input current is can be derived and shown in Table I. Similarly, the Fourier series expression of current iC1 regarding Io can be derived considering that most harmonics are absorbed by capacitor C1 . Table I also presents the analytical expression of current IC1 and voltage VC1 , which represents the RM S value of current through C1 and the RM S value of voltage across C1 . The expressions shown in Table I indicate that both of them are apparently affected by harmonics. As shown in (10)–(19) and Table I, the stresses for the main components of the resonant network are determined by parameters F and β. In order to achieve a high-quality sine-wave current output, the range of parameter β is set from 1.3 to 1.5, which is close to the resonant point of the network. This has been explained in the analysis of the input impedance and the current transfer function. Thus, F should be properly tuned to guarantee a reasonable range of voltage and current stresses. It is noticeable in (10)–(19) that the voltage stresses of the resonant components decrease with parameter F , but the current stresses of the resonant components go in the opposite direction. As a result, the range of parameter F should be properly tuned to balance these two design aspects. The input impedance of the proposed resonant network Z can be expressed in the form of active and reactive components and is shown at the bottom of this page. The quality factor of the resonant network Q, which is defined in terms of the ratio of the energy stored in the resonator to the energy supplied by a source for each cycle, is expressed by (20). Solving (20) gives

F (1 − β 2 ) + jβ(2 − β 2 ) F 2 + j(2F β + 3F 3 β 3 + 5F β 5 ) + j(2F 3 β + 7F β 3 + F 3 β 5 + F β 7 ) Req = Req 2 4 2 2 F (1 − 3β + β ) + jF β(2 − β ) [F (1 − 3β 2 + β 4 )]2 + [F 2 β(2 − β 2 )]2


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TABLE I EXPRESSIONS FOR THE C URRENT AND VOLTAGE OF C OMPONENT C1

parameters can be plotted in a 3-D format and shown in Fig. 11. It indicates that the value of F1 is varying from 0.4 to 1.2 to assure a high-quality factor and reasonable electrical stresses of the resonant components. As shown in Fig. 11(b), the value of F2 varies from 4 to 16, which indicates a current stress of nearly 20 times the output current. Considering the voltage and current ratings of power MOSFETs and resonant components, F1 is selected and its value varies from 0.4 to 1.2. With the determined ranges of parameters F and β, the main electrical stresses of the resonant components are therefore calculated based on (9) (10)–(19) and the analytical expressions shown in Table I. Fig. 12 illustrated the main electrical stresses of the resonant components with respect to parameters F and β. The voltage stresses of C1 and C2 are within 1.6 times and 4 times of the output voltage, respectively, as shown in Fig. 12(a) and (b). Fig. 12(a) also indicates that high-order harmonics, particularly the third harmonic, cannot be neglected in the analysis of VC1 . The current stress of L1 is below 3 times the output current, as illustrated in Fig. 12(c). In summary, the electrical stresses of power MOSFETs and resonant components are well defined for practical implementations. Based on the determined ranges of F and β, the parameters of the double Γ-CL resonant network are determined as

Fig. 11. and β.

Characteristics among F , Q, and β: (a) F1 , Q, and β; (b) F2 , Q,

two F values, i.e., F1 and F2 , as illustrated in (21) and (22), respectively 3F 2 β 3 + 2β + 5β 5 F Q − Q2 − 12β 3 (2β + 5β 5 ) F1 = 6β 3 Q + Q2 − 12β 3 (2β + 5β 5 ) F2 = . 6β 3 Q=

L=

Req β ωF

(23)

C=

β2 ω2 L

(24)

where ω = 2π × 105 rad/s, F = 0.4−1.6, β = 1.3−1.5, and the equivalent load resistance Req ranges from 0 to 60 Ω corresponding to the delivered power range.

(20) IV. G ATE D RIVE M ODULES (21) (22)

The characteristics among parameters F , Q, and β should be evaluated to assign a proper range of F , which determines the range of voltage and current stresses. High Q values (Q > 50) should be achieved to assure low harmonic output current. With the assigned ranges of Q and β, the characteristics among three

The proposed gate driving architecture with independent transmission of energy and gate signals is shown in Fig. 3. The CTs are the energy links between the CHFCS and the distributed GDMs. The secondary current of CTs is rectified and converted to a constant dc voltage by the SSSVR. The gate signals are optically transmitted through fiber optic cables and transformed to the gate driving pulses of high-power switching devices by the gate drive circuits. In this section, the requirement of CTs is outlined, and the criteria of selecting the magnetic core materials are discussed. A switched-mode SSSVR is

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TABLE II MAIN PARAMETERS OF M AGNETIC C ORE M ATERIALS

Fig. 13. Switched-mode SSSVR: (a) schematics; (b) operation mode when MS1 is in ON state; (c) operation mode when MS1 is in OFF state.

Fig. 12. Main electrical stresses of resonant components with regard to F and β: (a) VC1 and VC1,1 , F , and β; (b) VC2 , F , and β; (c) IL1 , F , and β.

proposed to replace traditional linear voltage regulators for high efficient conversion.

simple structure and excellent compact magnetic coupling. The transmission efficiency of the CTs becomes critical considering that the primary winding is just one turn. An ideal CT should meet the following requirements: high permeability for large magnetic inductance, short magnetic path length and large cross section for good magnetic coupling effect, low magnetic core loss, high saturate magnetic flux density Bs , good temperature characteristic, and high Curie temperature Tj [41]. The available magnetic core materials are listed and compared in Table II in terms of relative permeability μr , saturate magnetic flux density Bs , Curie temperature Tj , and resistivity ρ. The experimental tests and comparison of magnetic core samples in terms of permeability and transmission efficiency will be presented and analyzed in Section V. B. SSSVR

A. CTs A high-voltage cable is adopted as the primary winding of the CTs, and the turn of the primary side is just one to ease the on-site installation. The HFAC produced by the CHFCS flows in the primary winding of the CTs, as shown in Fig. 6. The magnetic field is produced in the magnetic core of the CTs, and the secondary current is accordingly induced by magnetic coupling of CTs. For the SSFCL application, toroid magnetic cores are selected for constructing the CTs due to their

The SSSVR is configured for each GDM, which is located at the high-voltage side. Considering the high power loss of traditional linear voltage regulation techniques, a switchedmode SSSVR is proposed with the schematic shown in Fig. 13. The topology is similar to conventional boost converters except for ignoring the input inductor because the input of the SSSVR is a continuous dc current source. Iins represents the input current of the SSSVR, which is the rectified current of the secondary current iss . Considering that the input current Iins


and the output voltage Vso are constant at steady state, the basic operation modes of the switched-mode SSSVR can be analyzed as follows. Mode I: MOSFET MS1 is switched on, and there is no current flowing through diode DS1 because the input current source is in short-circuit state. The operation mode is illustrated in Fig. 13(b). Output capacitor Cso is discharged, and the voltage drop across Cso is expressed as (25), where Dsb and Tsb represent the switching duty cycle and the switching period of this SSSVR, respectively Δvso =

V so Dsb Tsb . C so R so

Iins − Vso /Rso (1 − Dsb )Tsb . C so

(26)

Based on the current-second balance of output capacitor Cso in a switching period, the average output voltage of the SSSVR Vso can be regulated by the switching duty cycle and expressed as Vso = Iins Rso (1 − Dsb ).

TABLE III SPECIFICATIONS AND PARAMETERS OF THE P ROTOTYPE

(25)

Mode II: MOSFET M S1 is switched off, and diode Ds1 is conducting. The operation mode is illustrated in Fig. 13(c). Output capacitor Cso is charged with input current Iins . The voltage rise during this stage becomes Δvso =

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was built with the rated output current of 2.5 A. The CHFCS is evaluated by using two load conditions, including the resistive loads and practical GDMs. For resistive load, the prototype is evaluated in terms of output current THD, power factor, and efficiency. The CTs with different magnetic core samples are compared with respect to the transmission efficiency. Finally, the application of the prototype in a practical 400 V/300 A SSFCL system is presented, and the experimental results are analyzed. A. Current Source With Resistive Loads

(27)

The output voltage of the SSSVR Vso is sensed and regulated to a constant value set by an analog chip, TL431, which is a three-terminal adjustable precision shunt regulator. Each SSSVR is self-regulated to reduce the interference among GDMs. The proposed switched-mode SSSVR shows 80% efficiency in comparison with that of the linear voltage regulators, which is less than 40% for this application. The improved efficiency results in the significant reduction of the size and weight of the SSSVR since a bulky heat sink is no longer needed. C. Gate Drive Circuits The gate drive circuits amplify and transform the gate signals transmitted by fiber optic cables to electrical gate driving pulses, which are sent to high-power switching devices. For voltage-controlled switching devices such as IGBTs or MOSFETs, the TTL electrical gate driving pulses can be used directly to drive these switching devices. For current-controlled switching devices such as thyristors or GTOs, the amplitude of gate driving current needs to be specifically defined and a level shifting circuit, including a strong trigger circuit, should be included. In addition, special gate driving IC is required for the gate drive circuit of GTO considering the requirements of negative pulse and negative voltage. V. E XPERIMENTAL E VALUATION To verify the proposed architecture, a 400-W current-fed HFAC power supply prototype was developed according to the specifications and parameters shown in Table III. The prototype

The prototype is first evaluated with resistive loads. For comparative study, the experimental results of the current source without resonant networks and the current source with the parallel resonant network are presented. The output current and its harmonics distribution of the current source without resonant networks are shown in Fig. 14. Without the resonant networks, the third harmonic of the output current is as high as 30% and the measured THD is 41.3%. The parallel resonant network shown in Fig. 4 was designed with the following parameters: Lp = 58 μH and Cp = 47 nF. Its filtering effect was experimentally evaluated and analyzed. With the parallel resonant network, the output current has low harmonics at the rated load condition. However, it shows obvious distortion in the output current for the light-load condition. Fig. 15 shows the output current and harmonics distribution for the lightload condition, which corresponds to 20 Ω the equivalent load impedance Req . It shows that the third harmonic is 12.5%, and the measured THD is 15.6%. Fig. 16 shows the output current waveforms of the proposed 400-W CHFCS prototype with the double Γ-CL resonant network responding to different load conditions, including shortcircuit, half-load, and full-load conditions, which are related to the load resistances Req of 0, 30, and 60 Ω, respectively. The harmonics distribution under three different resistive load conditions is demonstrated in Fig. 17. The third harmonics of the output current is 6.3% under the short-circuit condition. The corresponding third harmonics of the output current are 2.8% and 2.9% under the half-load and full-load conditions, respectively. The measured THDs of the output current are 6.7%, 2.9%, and 3.0% for the three different load conditions, correspondingly. The improvement is noticeable in terms of output current THD and the applicable load range by comparing

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Fig. 15. Output current and harmonics distribution of the high-frequency current source with the parallel resonant network for light-load condition: (a) output current; (b) harmonics distribution. Fig. 14. Output current and harmonics distribution of the high-frequency current source without resonant networks: (a) output current; (b) harmonics distribution.

Figs. 14 and 15. Furthermore, it indicates that the CHFCS has the capability of output sine-wave current under the shortcircuit condition. This feature shows the improvement of the system flexibility and reliability. Fig. 18 shows the output current RM S value versus the power delivery. The RM S value of the output current constantly maintains at 2.5 A within ±5% errors. The errors can be explained by the fact that the output current of the current source is rectified and the control variable of the current source is the mean value of the rectified current of the output current, rather than the corresponding RM S value. The efficiency and power factor are plotted together and shown in Fig. 19. The proposed TSRI topology combined with a double Γ-CL resonant network demonstrates the advantages of the high power factor and efficiency. The power factor of the resonant network is always above 0.98 for the whole power delivery range. Peak efficiency reaches 91%, which corresponds to the rated power of 400 W. The efficiency is higher than 80% from half-load to full-load conditions, which covers the majority of the power range of the gate driving system for the SSFCL, as shown in Fig. 3. For light-load conditions that the output power is less than 50 W, the proposed solution shows 60% efficiency in comparison with 40% in the case that no resonant network is implemented. The efficiency improvement

results from removing of the series-connected 25-Ω resistor, which must be added along the primary winding of the CTs for the previous designs [28]–[30] to improve the stability margin for light-load conditions. Based on the specifications and parameters of the prototype shown in Table III, the estimated power loss distribution of the prototype with respect to the power delivery is calculated and shown in Fig. 20. The losses include the buck MOSFET conduction and switching losses PS1 , the buck diode losses PD1 , four FB switching devices losses PS2−S5 , and the losses for buck inductor and resonant components PMag . It can be found that the loss of PMag is almost constant for the whole range of power delivery. The loss of PS2−S5 is increasing in a nearly linear manner with the power delivery. For light-load conditions, the losses of PS1 and PD1 are dominant and greatly affect the efficiency of the CHFCS. Therefore, minimizing the losses of PS1 and PD1 will be studied in the future to improve the efficiency at the light-load condition. B. Magnetic Cores of CTs As shown in Fig. 3, a high-voltage cable carrying the HFAC passes through the center of toroid magnetic cores. Major requirements and parameters for the magnetic cores are discussed in Section IV. The experimental tests and comparison of magnetic core samples with respect to the transmission efficiency are presented in the following paragraphs.


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Fig. 17. Harmonics distribution analysis of the high-frequency current source under different resistive load conditions, including short-circuit, half-load, and full-load conditions.

Fig. 18. Output current RMS value of the high-frequency current source versus the power delivery.

Fig. 16. Output current of the high-frequency current source under different resistive load conditions: (a) short-circuit condition; (b) half-load condition; (c) full-load condition.

Table IV provides the specifications and parameters of the CTs. Table V shows the experimental results of different magnetic core samples. The magnetic core samples are numbered according to the magnetic material, magnetic size, and relative permeability. The main parameters of the magnetic core samples listed in Table V include the magnetic core material, secondary-side magnetizing inductance of CTs Lm , relative permeability μr , and secondary current RM S value Iss . The

Fig. 19. Efficiency and power factor of the high-frequency current source under resistive load conditions with regard to power delivery.

size of the toroid magnetic core is defined by the outer diameters φo , inner diameters φi , and height h. As shown in Table V, the transmission efficiency of CTs is affected by the magnetizing inductance Lm , which is determined by the relative permeability μr . For the same magnetic material, a magnetic core with higher Lm generally shows better transmission efficiency because the magnetizing current of the CTs

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Fig. 20. Loss breakdown distribution of the high-frequency current source under resistive load conditions with regard to power delivery. TABLE IV SPECIFICATION AND PARAMETERS OF THE CT S

TABLE V EXPERIMENTAL R ESULTS OF T OROID M AGNETIC C ORE S AMPLES

Fig. 21. Measured voltage and current waveforms of the CT with the “ferrite 4” magnetic core: (a) primary vps and secondary voltages vss ; (b) primary io and secondary currents iss . TABLE VI MAIN PARAMETERS OF THE E XPERIMENTAL SSFCL P ROTOTYPE

is reduced and more current is transmitted to the secondary side of CTs. The measured secondary current Iss verifies the analysis. During the test, a significant temperature rise that is higher than that of ferrite magnetic core samples is observed when the amorphous magnetic core samples are tested. This disadvantage results in reliability issues for medium–high-voltage gate driving system applications although the amorphous magnetic cores show high transmission efficiency. The “ferrite 4” magnetic core is selected because of its good thermal properties, high permeability, and transmission efficiency. Fig. 21 shows the voltage and current waveforms of both primary and secondary sides when the “ferrite 4” magnetic core is adopted. Symbol io represents the output current of the TSRI, which is also the primary current of the CTs. Symbol iss represents the secondary current of the CTs. Symbols vps and vss represent the primary and secondary voltages of the CTs. The measured transmission efficiency using the “ferrite 4” magnetic core reaches 86.1%. C. Application for SSFCL The current-fed HFAC DPS is finally tested to supply multiple GDMs for a practical 400 V/300 A SSFCL system with the capability of limiting a 1500-A short-circuit current. Equivalent load resistance Req is defined by the actual power assumption of these GDMs, which also varies from 0 to 60 Ω. For resistive

loads, three different load conditions are tested, including shortcircuit, half-load, and full-load conditions. Similarly, the prototype evaluation is based on various different load conditions determined by the number of operating GDMs. The light-load condition indicates fewer GDMs being used. When all GDMs are in standby mode, it corresponds to the short-circuit condition, and the equivalent load resistance Req is zero because of the actual zero power consumption. Fig. 22 shows the measured output voltage vo and current io of the CHFCS when seven GDMs are supplied. Output current io is sinusoidal, showing a low harmonic distortion, and the measured THD is 3.7%. The output voltage is nearly a square-wave voltage, and its amplitude is determined by the turn ratio of CTs and the constant output voltage of the SSSVR, which is set to 12 V. In Fig. 22, the output current io shows noticeable spikes when the practical GDMs are connected, which is different from the test shown in Fig. 16 when the pure resistive load is applied. This results from the nonlinear characteristic of the diode rectifier, which is used in each GDM to convert the ac to dc.


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indicates that the current of Ldc shown in channel 1 increases to the maximum value of 1500 A in about 10 ms after the fault. Then, the trigger angle of gate driving pulses for T1 −T6 is controlled by a central controller, which regulates the current of Ldc to follow a reference value. At zero-crossing instants of the input phase current, the trigger angle is set to 180◦ , then thyristors T1 −T6 are completely shut off. Fig. 23 shows that the current of Ldc is limited to zero within 20 ms. The above description corresponds to the current-limiting process, which is followed by a soft-start process. During this process, T7 and T8 are first switched on and the initial angle of gate driving pulses for T1 −T6 is set to 90◦ . Then, by gradually reducing the trigger angle of gate driving pulses for T1 −T6 , the current of Ldc increases with the rate set by the central controller. The SSFCL system enters the steady state within 80 ms, and the corresponding current RM S value of the limiting dc inductor is stabilized at 350 A, which is the RM S value of the rectified current corresponding to 200-A phase current. The waveforms shown in Fig. 23 describe the whole process of the SSFCL operation and verify the effectiveness of the proposed current-fed HFAC DPS for medium–high-voltage gate driving applications. VI. C ONCLUSION Fig. 22. Measured output voltage and current waveforms of the highfrequency current source with loads of seven GDMs: (a) output voltage vo ; (b) output current io .

Fig. 23. Experimental waveforms of the experimental SSFCL system.

Finally, the proposed current-fed HFAC gate driving system is tested for the fault current-limiting operation. The SSFCL system specification is shown in Table VI. The system is rated as 400 V/300 A, with the maximum short-circuit current of 1500 A. Fig. 23 shows experimental results, where channel 1 indicates the current waveform of the dc inductor and channel 2 shows the gate driving pulses applied to the thyristors. When the three-phase short-circuit fault occurs, the input voltage is directly applied to the dc limiting inductor Ldc as the load voltage becomes zero during the short-circuit fault. The current of Ldc shown in channel 1 rapidly rises and exceeds the protection threshold current of the SSFCL in 10 ms. After detecting the fault, the central controller blocks the gate driving pulses for T7 and T8 and the initial angle of gate driving pulses for T1 −T6 is set to 90◦ for limiting the rise rate of the shortcircuit current and minimizing the current overshoot. Fig. 23

A novel current-fed HFAC DPS system has been presented for medium–high-voltage gate driving applications. The power of the distributed GDMs at the high-voltage side is supplied by the low-voltage-side current-source power supply through magnetic coupling of CTs, which are constructed by a highvoltage cable carrying HFAC and passing through the center of toroid magnetic cores. At the low-voltage side, a structure of TSRI combined with a double Γ-CL resonant network has been proposed for the highfrequency current source. The first stage is a buck converter, and the second stage is an FB converter, which is modulated by a fixed duty ratio. By comparison to various current-fed resonant networks, the double Γ-CL resonant network is utilized and shows the following advantages: 1) low harmonic output current; 2) high current transfer gain; 3) wide operating range; and 4) low voltage and current stresses even when the operating frequency is set to the resonant frequency. The proposed resonant network is parameterized considering the design aspects of the quality factor, current transfer gain, and electrical stresses of the main components. At the high-voltage side, toroid magnetic cores are used to transmit energy from the high-frequency current bus to individual GDM. The experimental tests and comparison of magnetic core samples, with respect to the transmission efficiency, have been presented. Switched-mode SSSVRs are specifically designed to replace traditional linear voltage regulators, showing improved efficiency and high power density. A 400-W current-fed HFAC power supply prototype with the rated output current of 2.5 A is accordingly developed. The measured THDs of the output current are 6.7%, 2.9%, and 3.0% for the three load conditions of short-circuit, half-load, and full-load conditions. The peak efficiency reaches 91%, which corresponds to the rated power delivery. The experimental

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results show the advantages of the proposed HFAC power supply system in terms of low harmonic output, wide load range, and high efficiency. The prototype is successfully applied to a practical 400 V/300 A SSFCL system with the capability of limiting 1500-A short-circuit current. The application validates the important features of the current-fed HFAC power supply system, including multiple outputs (n > 10) and high-voltage isolation. Furthermore, the proposed gate driving architecture demonstrates high reliability, good extensibility, and installation flexibility as the energy and gate signals are independently transmitted by a high-voltage cable and fiber optic cables. R EFERENCES [1] F. S. Tsai and F. C. Y. Lee, “High-frequency AC power distribution in space station,” IEEE Trans. Aerosp. Electron. Syst., vol. 26, no. 2, pp. 239–253, Mar. 1990. [2] R. P. Torrico-Bascope, D. S. Oliveira, Jr., C. G. C. Branco, and F. L. M. Antunes, “A UPS with 110-V/220-V input voltage and highfrequency transformer isolation,” IEEE Trans. Ind. Electron., vol. 55, no. 8, pp. 2984–2996, Aug. 2008. [3] C. Daolian, “Novel current-mode AC/AC converters with high-frequency AC link,” IEEE Trans. Ind. Electron., vol. 55, no. 1, pp. 30–37, Jan. 2008. [4] Z. M. Ye, P. K. Jain, and P. C. Sen, “Analysis and design of full bridge resonant inverter for high frequency AC distributed power system application,” in Proc. 31st IEEE IECON, 2005, p. 8. [5] C. C. Antaloae, J. Marco, and N. D. Vaughan, “Feasibility of highfrequency alternating current power for motor auxiliary loads in vehicles,” IEEE Trans. Veh. Technol., vol. 60, no. 2, pp. 390–405, Feb. 2011. [6] H. Krishnaswami and V. Ramanarayanan, “Control of high-frequency AC link electronic transformer,” Proc. Inst. Elect. Eng.—Elect. Power Appl., vol. 152, no. 3, pp. 509–516, May 2005. [7] S. Lourdes, S. Y. Ng, and P. C. K. Luk, “An alternative power grid—High frequency AC power distribution platforms,” in Proc. IEEE 6th IPEMC, 2009, pp. 1949–1956. [8] M. Sarhangzadeh, S. H. Hosseini, M. B. B. Sharifian, and G. B. Gharehpetian, “Multiinput direct DC–AC converter with highfrequency link for clean power-generation systems,” IEEE Trans. Power Electron., vol. 26, no. 6, pp. 1777–1789, Jun. 2011. [9] Y. Zhongming, P. K. Jain, and P. C. Sen, “Circulating current minimization in high-frequency AC power distribution architecture with multiple inverter modules operated in parallel,” IEEE Trans. Ind. Electron., vol. 54, no. 5, pp. 2673–2687, Oct. 2007. [10] F. C. Lee, P. Barbosa, X. Peng, Z. Jindong, B. Yang, and F. Canales, “Topologies and design considerations for distributed power system applications,” Proc. IEEE, vol. 89, no. 6, pp. 939–950, Jun. 2001. [11] Y. Zhongming, J. C. W. Lam, P. K. Jain, and P. C. Sen, “A robust onecycle controlled full-bridge series–parallel resonant inverter for a highfrequency AC (HFAC) distribution system,” IEEE Trans. Power Electron., vol. 22, no. 6, pp. 2331–2343, Nov. 2007. [12] Y. Zhongming, P. K. Jain, and P. C. Sen, “A two-stage resonant inverter with control of the phase angle and magnitude of the output voltage,” IEEE Trans. Ind. Electron., vol. 54, no. 5, pp. 2797–2812, Oct. 2007. [13] W. Xiaopeng, Y. Ruoping, and R. Fangquan, “Subsystem-interaction restraint in the two-stage DC distributed power systems with decouplingcontrolled-integration structure,” IEEE Trans. Ind. Electron., vol. 52, no. 6, pp. 1555–1563, Dec. 2005. [14] P. Karlsson and J. Svensson, “DC bus voltage control for a distributed power system,” IEEE Trans. Power Electron., vol. 18, no. 6, pp. 1405– 1412, Nov. 2003. [15] Z. M. Ye, P. K. Jain, and P. C. Sen, “A full bridge resonant inverter with modified phase shift modulation,” in Proc. 36th IEEE PESC, 2005, pp. 642–649. [16] Y. H. Liu, J. Arrillaga, and N. R. Watson, “A new STATCOM configuration using multi-level DC voltage reinjection for high power application,” IEEE Trans. Power Del., vol. 19, no. 4, pp. 1828–1834, Oct. 2004. [17] Y. H. Liu, J. Arrillaga, and N. R. Watson, “Multi-level voltage reinjection—A new concept in high voltage source conversion,” Proc. Inst. Elect. Eng.—Gener. Transm. Distrib., vol. 151, no. 3, pp. 290–298, May 2004. [18] J. Rodriguez, L. Moran, J. Pontt, P. Correa, and C. Silva, “A highperformance vector control of an 11-level inverter,” IEEE Trans. Ind. Electron., vol. 50, no. 1, pp. 80–85, Feb. 2003.

[19] L. Heinemann, J. Mast, G. Scheible, T. Heinzel, and T. Zuellig, “Power supply for very high insulation requirements in IGBT gate-drives,” in Conf. Rec. 33rd IEEE IAS Annu. Meeting, 1998, vol. 2, pp. 1562–1566. [20] S. Y. Hui, S. C. Tang, and H. S. H. Chung, “Some electromagnetic aspects of coreless PCB transformers,” IEEE Trans. Power Electron., vol. 15, no. 4, pp. 805–810, Jul. 2000. [21] A. M. Flynn and S. R. Sanders, “Fundamental limits on energy transfer and circuit considerations for piezoelectric transformers,” IEEE Trans. Power Electron., vol. 17, no. 1, pp. 8–14, Jan. 2002. [22] L. Ray-Lee, S. Hsu-Ming, L. Chen-Yao, and L. Kuo-Bin, “A family of piezoelectric-transformer-based bridgeless continuous-conduction-mode charge-pump power-factor-correction electronic ballasts,” IEEE Trans. Ind. Appl., vol. 47, no. 3, pp. 1149–1158, May/Jun. 2011. [23] T. Tsuboi, J. Takami, S. Okabe, K. Inami, and K. Aono, “Experiment on multiple-times voltage application to evaluate insulation reliability of oilimmersed transformer,” IEEE Trans. Dielect. Elect. Insul., vol. 17, no. 5, pp. 1657–1664, Oct. 2010. [24] J. Afsharian, N. Zaragari, and W. Bin, “A special high-frequency softswitched high-voltage isolated DC/DC power supply for multiple GCT gate drivers,” in Proc. IEEE ECCE, 2010, pp. 2441–2445. [25] L. Zhengyu, J. Daozhuo, and W. Zhaolin, “A new topology of fault-current limiter and its parameters optimization,” in Proc. 34th IEEE PESC, 2003, vol. 1, pp. 462–465. [26] F. WanMin, Z. YanLi, and L. ZhengYu, “Novel bridge-type FCL based on self-turnoff devices for three-phase power systems,” IEEE Trans. Power Del., vol. 23, no. 4, pp. 2068–2078, Oct. 2008. [27] A. Abramovitz and K. M. Smedley, “Survey of solid-state fault current limiters,” IEEE Trans. Power Electron., vol. 27, no. 6, pp. 2770–2782, Jun. 2012. [28] H. Wen, X. Wen, and Z. Lu, “AC distributed power supplies used for solid state short-circuit fault current limiter,” in Proc. ICEMS, 2007, pp. 1871– 1875. [29] Z. Yanli, F. Wanmin, and L. Zhengyu, “A novel isolation power supply for gating multiple devices in FACTS equipment,” in Proc. 7th Int. Conf. PEDS, 2007, pp. 117–119. [30] Z. Zhongyuan, L. Zhengyu, J. Gaoxian, F. Wanmen, and X. Linghui, “Development of gate-driving system of thyristor valve with multiple isolated outputs used in new-type solid-state short-circuit fault current limiter in electric power system,” in Proc. 35th IEEE PESC, 2004, vol. 4, pp. 3233–3236. [31] S. K. Mazumder and T. Sarkar, “Optically-activated gate control for power electronics,” IEEE Trans. Power Electron., vol. 26, no. 10, pp. 2863–2886, Oct. 2011. [32] M. Matsuo, T. Suetsugu, S. Mori, and I. Sasase, “Class DE current-source parallel resonant inverter,” IEEE Trans. Ind. Electron., vol. 46, no. 2, pp. 242–248, Apr. 1999. [33] L. Tsorng-Juu, C. Ren-Yi, and C. Jiann-Fuh, “Current-fed parallel–resonant DC–AC inverter for cold-cathode fluorescent lamps with zero-current switching,” IEEE Trans. Power Electron., vol. 23, no. 4, pp. 2206–2210, Jul. 2008. [34] J. M. Alonso, J. Garcia, A. J. Calleja, J. Ribas, and J. Cardesin, “Analysis, design, and experimentation of a high-voltage power supply for ozone generation based on current-fed parallel–resonant push–pull inverter,” IEEE Trans. Ind. Appl., vol. 41, no. 5, pp. 1364–1372, Sep./Oct. 2005. [35] W. A. Davis and K. Agarwal, Radio Frequency Circuit Design., 1st ed. Hoboken, NJ: Wiley-IEEE Press, Feb. 23, 2001. [36] M. Borage, K. V. Nagesh, M. S. Bhatia, and S. Tiwari, “Design of LCL-T resonant converter including the effect of transformer winding capacitance,” IEEE Trans. Ind. Electron., vol. 56, no. 5, pp. 1420–1427, May 2009. [37] R. Beiranvand, B. Rashidian, M. R. Zolghadri, and S. M. H. Alavi, “Using LLC resonant converter for designing wide-range voltage source,” IEEE Trans. Ind. Electron., vol. 58, no. 5, pp. 1746–1756, May 2011. [38] F. L. Luo and H. Ye, “Investigation and verification of a cascade double Γ-CL current source resonant inverter,” Proc. Inst. Elect. Eng.—Elect. Power Appl., vol. 149, no. 5, pp. 369–378, Sep. 2002. [39] Q. Mei and P. K. Jain, “System performance of a high frequency AC power distribution system,” in Proc. 24th Annu. INTELEC, 2002, pp. 491–496. [40] Z. M. Ye, P. K. Jain, and P. C. Sen, “A modified resonant inverter for AC distributed power supplies with extended zero voltage switching,” in Proc. 4th IPEMC, 2004, vol. 2, pp. 947–952. [41] J. A. Paulsen, C. C. H. Lo, J. E. Snyder, A. P. Ring, L. L. Jones, and D. C. Jiles, “Study of the Curie temperature of cobalt ferrite based composites for stress sensor applications,” IEEE Trans. Magn., vol. 39, no. 5, pp. 3316–3318, Sep. 2003.


Huiqing Wen received the B.S. and M.S. degrees in electrical engineering from Zhejiang University, Hangzhou, China, in 2002 and 2006, respectively, and the Ph.D. degree in electrical engineering from the Chinese Academy of Sciences, Beijing, China, in 2009. From 2009 to 2010, he was an Electrical Engineer with GE (China) Research and Development Center Company, Ltd., Shanghai, China. From 2010 to 2011, he was an Engineer at China Coal Research Institute, Beijing. Currently, he is a Postdoctoral Fellow at Masdar Institute of Science and Technology, Abu Dhabi, United Arab Emirates. His research interests include bidirectional dc–dc converter, power electronics in flexible ac transmission (FACTS) applications, electrical vehicles, and high-power three-level electrical driving system.

Weidong Xiao (M’07) received the M.Sc. and Ph.D. degrees from the University of British Columbia, Vancouver, BC, Canada. He is currently an Assistant Professor of electrical power engineering with Masdar Institute of Science and Technology, Abu Dhabi, United Arab Emirates. Before his academic career, he was with MSR Innovations Incorporation as an R&D Engineering Manager focusing on projects related to integration, monitoring, evaluation, optimization, and design of photovoltaic power systems. His research area includes power electronics, photovoltaic power systems, digital control techniques, and industrial applications.

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Zhengyu Lu (SM’02) received the B.S. degree in hydraulic power engineering from Hohai University, Nanjing, China, in 1982 and the Ph.D. degree in power electronics from Zhejiang University, Hangzhou, China, in 1987. From 1996 to 1998, he was a Visiting Scholar and Researcher with the University of Birmingham, Birmingham, U.K., and Imperial College London, London, U.K. He is currently a Professor with Zhejiang University and the Director of China National Power Electronics Laboratory. Since 1982, he has been doing teaching and research work on power electronic device and power converter for more than 20 years in Zhejiang University. His main current research interests include power converter, electrical track, renewable power, and power electronics system integration.