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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 53, NO. 1, FEBRUARY 2006

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Current Programmed Control of a Single-Phase Two-Switch Buck–Boost Power Factor Correction Circuit Gert K. Andersen and Frede Blaabjerg, Fellow, IEEE

Abstract—This paper presents a new current programmed control (CPC) technique for a cascaded two-switch buck–boost converter suitable as a low-cost power factor correction (PFC) rectifier in a variable speed motor drive. This new CPC technique, which is an extension of the conventional CPC method, enables the variable output dc voltage, and is therefore suitable in a pulse amplitude modulated (PAM) motor drive or as a universal input-power supply. The CPC method is very simple and requires only a constant-current reference without any changes in the transition between boost and buck operating mode, and the line current is practically unaffected by the topology-mode shift. Simulations and experimental results verify the presented control technique. Compliance with IEC-61000-3-2 class A is achieved. The experimental setup is based on a commercial CPC integrated circuit (IC) for dc–dc converters. This new control technique enables a simple low-cost control circuit for the two-switch buck–boost converter, which complies with IEC-61000-3-2, and the PFC circuit has inherent in-rush and overcurrent protection. Index Terms—Buck–boost, current harmonics, current programmed control (CPC), peak current control, power factor correction (PFC), valley current control.

I. I NTRODUCTION

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EGULATIONS such as IEC-61000-3-2 demand some sort of input current shaping for single-phase equipment [1]. Active current shaping is usually used in the power range around 2 kW in order to reduce the volume of the converter, and it usually consists of a conventional diode bridge followed by a dc–dc switch-mode converter, which shapes the current. Introducing an active power factor correction (PFC) in a lowpower (single-phase connection) adjustable-speed drive (ASD) increases production cost and complexity, and decreases efficiency. Therefore, a PFC control technique in a low-cost motor drive must be simple and robust. Fig. 1 lists some important features that have to be taken into account when designing a single-phase ASD for a threephase induction motor. The input power is pulsating and discontinuous due to the single-phase voltage. The output power is constant at each operating point. The power-electronic converter usually consists of a rectifier stage and an inverter stage, which are interfaced by a capacitor. In an application-specific Manuscript received October 22, 2002; revised May 10, 2005. Abstract published on the Internet November 25, 2005. G. K. Andersen is with Vestas Wind Systems, Randers DK-8900, Denmark (e-mail: [email protected]). F. Blaabjerg is with the Institute of Energy Technology, Aalborg University, Aalborg DK-3220, Denmark (e-mail: [email protected]). Digital Object Identifier 10.1109/TIE.2005.862252

Fig. 1. Features of a general adjustable-speed three-phase induction-motor drive with a single-phase connection.

ASD for a heating, ventilating, and air conditioning (HVAC) system, the inverter is typically controlled by a programmed Va /fa characteristic that fits the application. Thus, if an active PFC is added to a conventional pulsewidth modulation (PWM)controlled inverter, there will be high switching-frequency losses in both the rectifier and in the inverter. If the inverter should only generate the fundamental frequency, the inverter switching frequency can be reduced dramatically as a fixed modulation index or a specific pulse pattern can be used. Hence, a PFC circuit with variable output dc voltage, as a supply in a low-cost adjustable speed induction-motor drive, is interesting, as seen from a drive-design point of view, as the inverter switching losses can be reduced. There exists a variety of control techniques for switch-mode converters and PFC circuits, and most of these techniques are supported by commercial and available integrated circuits (ICs) for the basic converter topologies like boost, buck, buck–boost, push–pull, forward, flyback, sepic, c´ uk, etc. [2], [3]. Different PFC control techniques are compared in [3]. Average current control (ACC) is relatively immune towards noise because only average signals are used, but ACC requires a currentreference generator, which may be expensive. Current programmed control (CPC) is inherently more sensitive towards noise, and circuit layout must be done very carefully. CPC is a simple control technique that provides cycle-by-cycle current limiting, and the use of a wave-shaping reference generator can be omitted. The stability of CPC has been subjected to intense study in the literature (cf., [2]–[12]). However, stability is not an issue if the switch duty cycle is restricted into a range equal to one half of the switching period. This range can be 0 ≤ d ≤ 0.5 or 0.5 ≤ d ≤ 1, depending on the control strategy, which will be shown later. Hysteresis current control

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TABLE I CONTROL TECHNIQUES FOR PFC CIRCUITS

is a simple technique, which is sensitive towards noise in the same manner as CPC, and this technique also requires two current-reference generators [14]. In addition, hysteresis control, in its most simple structure, has a variable switching frequency. Borderline control is basically a hysteresis-control technique, where the lower boundary is 0. In addition, there exist some types of control techniques, which require no direct current reference, and are, therefore, relatively immune towards input voltage distortions [15], [16]. Compliance with IEC-61000-3-2 depends strongly on the choice of switching frequency and switching inductance for CPC, whereas ACC and limit cycle control are able to comply with IEC-61000-3-2, regardless (practically) of the switching frequency and the switching inductor. A summary of these statements is listed in Table I. CPC is an interesting control method when cost and complexity should be minimized at the expense of line-current performance. This paper describes a new simple CPC technique with constant command current and without ramp compensation for the two-switch buck–boost PFC converter capable of complying with IEC-61000-3-2. The output dc voltage can be varied by adjusting the command current, and the application used here is a PFC dc voltage supply for a pulse amplitude modulated (PAM) inverter. Since no commercial IC exists for controlling such converter topology, a control strategy based upon existing CPC ICs is developed and tested in the laboratory.

II. C URRENT P ROGRAMMED C ONTROL (CPC) CPC has been described heavily in the literature, (cf., [2]–[12]) and the major issue has been the stability analysis because conventional CPC inherently becomes unstable, when the switch duty cycle is greater than 0.5. Ramp compensation can be added in order to expand the range of stability. Fig. 2(a) depicts the basic idea behind CPC for continuous conduction mode. The switch is turned ON at the beginning of each switching period, and the switch is turned OFF at the time instant when the inductor or switch current equals the command current Ic . This kind of CPC is denoted here as Peak CPC (PCPC). Fig. 2(b) shows another CPC technique, where the switch is turned OFF at the beginning of each switching period, and the

Fig. 2. Waveforms of inductor current iL , and the switch control signal q for (a) PCPC and (b) VCPC.

switch is turned ON at the time instant when the inductor current drops to the command current Ic . This kind of CPC is denoted here as valley CPC (VCPC). PCPC corresponds to the conventional CPC technique used in the literature. PCPC has inherently an overcurrent protection, and the average inductor current per switching period is always lower than the command current. In contrary, VCPC needs an additional overcurrent protection, which can be realized by a single comparator. The average inductor current per switching period is always higher than the command current for VCPC. Since PCPC detects the current during the ON time of the switch, the switch current can be measured, which is not possible in VCPC because VCPC detects the current during the OFF time of the switch. Detecting the switch current enables switch protection, and the current detecting resistor has lower ohmic losses because the current only flows during the ON time. Premature detection of the switch instant can be a problem when detecting the switch current because the switch current is the sum of the inductor current and the diode reverse recovery current during turn ON. Since VCPC only detects the current during the OFF time of the switch, the noise problems related to reverse-recovery current are eliminated. Both PCPC and VCPC are used in this paper. III. C ONVERTER T OPOLOGY Single-phase PFC in the power range around 1–2 kW is usually achieved by a conventional boost converter. If the dc voltage has to be varied according to the actual operating point, a buck–boost or buck type of converter must be utilized.

ANDERSEN AND BLAABJERG: CPC OF A SINGLE-PHASE TWO-SWITCH BUCK–BOOST PFC CIRCUIT

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IV. A NALYSIS

Fig. 3.

Two-switch buck–boost converter topology.

The two-switch buck–boost rectifier shown in Fig. 3 is found to be the most promising buck–boost topology in [13] for a single-phase PFC with variable dc voltage at the power level around 2 kW, and this topology is therefore selected for analysis in this paper. This converter is described more in details in [17]. The converter has two operating modes: a buck mode and a boost mode. Buck mode occurs when the rectified voltage vref is higher than the dc voltage, and boost mode occurs when the rectified voltage is lower than the dc voltage. The boost switch (s2 ) is turned OFF constantly in buck mode, and only the buck switch (s1 ) is modulated in buck mode. The buck switch is turned ON constantly in the boost mode, and only the boost switch is modulated in the boost mode. A disadvantage of the buck–boost topology is the need for a mode detection function. Previously, no reported CPC technique has been adapted to the present buck–boost topology, and commercial control ICs are only available for PCPC. The proposed CPC technique is shown in Fig. 4. When the converter operates as a boost converter, PCPC is used with a constant-current command and without ramp compensation, which means that the duty cycle is limited to 0.5. The inductor-current ripple decreases to 0 as the rectified voltage increases towards the dc voltage because the ON -state inductor voltage becomes 0. The boost switch duty cycle also drops to 0. The average input current per switch period increases from the zero crossing towards the point where the dc voltage and the rectified voltage become equal and the converter shifts to buck mode. If PCPC is used in the buck mode then the average input current per switch period will decrease when the converter shifts from boost mode to buck mode if the same current command is used which introduces low-order harmonics. If VCPC is used in the buck mode then the average input current per switch period will continue to increase as it did in boost mode. Thus, if PCPC and VCPC are used in the boost and buck modes, respectively, and the command current is constant then the average input current per switch period will be unaffected by the topology-mode shift. Fig. 4 also shows the duty cycles, and it appears that the buck duty cycle decreases smoothly from unity at the topology-mode shift but the buck switch duty cycle is higher than 0.5 in the entire buck range. Conventional CPC without ramp compensation becomes unstable when the duty cycle exceeds 0.5, and the next section will describe the stability in a generalized manner regardless whether PCPC or VCPC is used.

The stability range of CPC is generalized here, and the derivations are based on the simple model, as presented in [2]. This known model assumes constant-current slopes, and neglects the effects of the modulator. The analysis assumes that the current slopes (mon , moﬀ ) and the command current Ic are constant during a switching period. The slope before the switching instant is denoted mw , the slope after the switching instant is denoted mu , and, consequently, the corresponding durations are w and u, respectively. Fig. 5 shows the definitions of the steady-state inductor current and the perturbed waveforms in PCPC [Fig. 5(a)] and in VCPC [Fig. 5(b)]. At first, the ideal case is shown, where the error is 0, and the current at the switching instant iL (wT ) is iL (wT ) = iL (0) + mw wT ⇒ w=

iL (wT ) − iL (0) mw T

(1) (2)

where iL (0) is the current at the beginning of the switching period T . The current at the end of the switching period becomes iL (T ) = iL (wT ) + mu uT ⇒ u=

iL (T ) − iL (wT ) . mu T

(3) (4)

Thus, in steady state, (mw = Mw , mu = Mu , w = W , u = U ) the volt-second balance yields 0 = Mw W T + Mu U T ⇒ Mu W = . − U Mw

(5) (6)

Equation (6) shows the volt-second balance in steady state, where the error is 0. In the ideal case, the entire range of switch duty cycle can be utilized without stability problems, but these ideal considerations are not sufficient in reality because stability becomes a problem due to noise, delays, and other nonideal effects. The stability will be calculated and analyzed by introducing a small perturbation εil (0) of the initial inductor current iL (0) (cf., Fig. 5). The current becomes iL (0) = IL (0) + εil (0),

where |εil (0)| |IL (0)|

(7)

where IL (0) is the ideal steady-state inductor current at the beginning and at the end of a switching period. It should be noted that the error relates to the deviation from the steady-state operation. The current errors at the switching instant and at the end εil (T ) of the switching period are εil (0) = mw wT ˜ ∧ εil (T ) = mu wT ˜ ⇒ εil (T ) =

mw εil (0) mu

(8)

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Fig. 4. Simulated waveforms at Vdc = 250 V. Top: rectified voltage (vrec ), dc voltage (Vdc ), and converter mode (mode). Middle: inductor current iL and bottom: duty cycles.

TABLE II STABILITY FOR PCPC AND VCPC

Fig. 6.

Control diagram.

where Fig. 5. Definition of waveforms for (a) PCPC and (b) VCPC. ∆

β= where w ˜ denotes the perturbed value of w. Equation (8) shows the relation between the initial error and the error after a switching period. After n-switching periods, the error can be written as εil (nT ) = εil (0)

mw mu

n

= εil (0) · β n

(9)

W mu W =− . ≈− mw U 1−W

(10)

When n increases towards infinity, the error becomes   for |β| < 1 0, lim εil (nT ) = εiL (0) · lim β n = ±εiL (0), for |β| = 1 . n→∞ n→∞   ∞, for |β| > 1 (11)


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Fig. 7. Simulated waveforms at Vdc = 250 V. Top: Inductor current and the reference current. Middle: error current and topology-mode signal. Bottom: error current to the comparator. TABLE III SYSTEM PARAMETERS FOR THE BUCK–BOOST CONVERTER

Fig. 8. Measured waveforms at Vdc = 250 V. Top: Inductor current (5 A/div) and the reference current. Middle: error current and topology-mode signal (2 A/div). Bottom: error current to the comparator (2 A/div).

Thus, the stability is determined by the variable β, which demands W < 0.5, but there has been no assumption on whether W is the switch duty cycle D or the complement of the switch duty Q = 1 − D cycle. Table II depicts the stability range without ramp compensation for PCPC and VCPC, respectively. The generalized description shows that the stability range is inverted when changing between PCPC and VCPC. Thus, stable operation with duty cycles greater than 0.5 can be achieved without ramp compensation by using VCPC.

Fig. 9. Measured waveforms at Vdc = 200 V. Top: inductor current. Bottom: rectified voltage, dc voltage, and mode signal.

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Fig. 10. Simulated waveforms at Vdc = 220 V. Top: mode signal and inductor current. Bottom: line current.

V. R EALIZATION Fig. 6 depicts the control diagram of the developed CPC technique. The control is based on a commercial CPC control IC for dc–dc converters with limited duty cycle. In order to implement the VCPC technique when the converter operates in buck mode, the error signal and the gate signal are both inverted. The error signal is inverted in the buck mode by the multiplier. The signal to the multiplier from the mode signal is unity in boost mode, and is equal to −1 in the buck mode. Thus, the multiplier has no effect in the boost mode. The logic on the output makes the buck switch turn ON in the entire boost mode, and makes the boost switch turn OFF in the entire buck mode. Fig. 7 shows simulated waveforms at Vdc = 250 V, and Fig. 8 shows the measured waveforms at Vdc = 250 V. The bottom plot shows the error-signal feed to the current comparator, and the inversion of the error signal in the buck mode is obvious.

VI. R ESULTS

Fig. 11. Measured waveforms at Vdc = 220 V. Top: topology-mode signal (high: buck and low: boost). Middle: inductor current at 2 A/div. Bottom: line current at 2 A/div.

Simulation and experimental results are presented and compared. Table III depicts the nominal system parameter used. It should be noted that no design optimization has been done in order to select the values listed in Table III. Fig. 9 shows the inductor current, the rectified voltage, the dc voltage, and the topology-mode signal. It appears how the converter shifts between PCPC and VCPC when the rectifiedvoltage signal crosses the dc voltage signal. Figs. 10 and 11 show simulated and measured waveforms at Vdc = 220 V, respectively, and Figs. 12 and 13 show simulated and measured waveforms at Vdc = 250 V, respectively. From Figs. 7–13, it can be seen that simulations and measurements exhibit similar waveforms, and verifies the functionality

of this CPC technique developed to the two-switch buck–boost converter. The line current is practically unaffected by the topology-mode shift. The small disturbance in the line current at the topology shift is due to the fact that the input filter is exposed to a load step, because the buck–switch current shifts between continuous and discontinuous modes as the converter shifts between boost and buck. Additional damping of the input filter can be added in order to decrease this disturbance. The dc voltage can directly be controlled by the command current, which in total makes it a simple PFC technique. Fig. 14 shows the harmonic currents for the measurements in Figs. 11 and 13 and the limits set by IEC-61000-3-2. It appears


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Fig. 12. Simulated waveforms at Vdc = 250 V. Top: mode signal and inductor current. Bottom: line current.

Fig. 13. Measured waveforms at Vdc = 250 V. Top: topology-mode signal (High: buck and low: boost). Middle: inductor current at 2 A/div. Bottom: line current at 2 A/div.

Fig. 14. Harmonic spectra of the line current and the IEC-61000-3-2 limits. Top: the harmonic current for the measurement in Fig. 11. Bottom: the harmonic current for the measurement in Fig. 13.

that this control method complies with IEC-61000-3-2 in both cases. In order to quantify how well the developed control technique complies with the regulations, Table IV lists the harmonic currents, as shown in Fig. 14, together with the limits of IEC61000-3-2. From the simulated and the experimental waveforms, it appears that the proposed control technique operates as intended. The reference current Iref (cf., Fig. 6) is a dc-type signal, as seen in Figs. 7 and 8. The current-reference signal is the output of the dc voltage controller. Hence, the developed control technique generates inputcurrent harmonics well below the limits of IEC-61000-3-2,

and the conventional multiplier for sinusoidal current-reference generation has been eluded. This illustrates the advantages of the developed control technique: The proposed control technique is very simple as it avoids advanced current-reference generation, and the technique is robust as it has an inherent cycle-by-cycle current limitation. In addition, the proposed technique is able to vary the output voltage very simple by adjusting the level of the reference current Iref . VII. C ONCLUSION A new CPC technique has been developed to the cascaded two-switch buck–boost PFC converter, which uses constant

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TABLE IV HARMONIC CURRENTS

command current and without ramp compensation. The control circuit is built on a commercial CPC IC for dc–dc converters with a maximum duty cycle at 1/2. This new control technique enables a simple low-cost control circuit for the two-switch buck–boost converter, which complies with IEC-61000-3-2. This new simple PFC circuit has inherent inrush and overcurrent protection. The new CPC technique described and considered in this paper is a generalization of the conventional CPC technique, which can be used directly in many other applications. Simulations and experimental results verify the functionality of the developed CPC technique, where the stability range can be shifted between 0 ≤ d ≤ 0.5 or 0.5 ≤ d ≤ 1, without introducing ramp compensation. The developed control technique can be advanced by adding ramp compensation in order to expand the range of stability. The command current could be modulated to emulate the rectified voltage in order to provide an even higher power-factor performance. ACKNOWLEDGMENT The authors wish to thank the Power Electronics Laboratory in the Department of Electronics and Informatics, University of Padova, Italy, where the experimental part of this paper has been carried out. R EFERENCES [1] Part 3.2: Limits—Limits for Harmonic Current Emissions (equipment input current ≤ 16 A per phase), International Standard, Edition 1.2. EC 61000-3-2, 1998–2004. [2] R. W. Erickson, Fundamentals of Power Electronics. New York: Chapman & Hall, 1997. [3] L. Rossetto, G. Spiazzi, and P. Tenti, “Control techniques for power factor correction converters,” in Proc. Power Electronics and Motion Control (PEMC), Warsaw, Poland, 1994, pp. 1310–1318.

[4] R. D. Middlebrook, “Modeling current-programmed buck and boost regulators,” IEEE Trans. Power Electron., vol. 4, no. 1, pp. 36–52, Jan. 1989. [5] C. A. Canesin and I. Barbi, “Analysis and design of constant-frequency peak-current-controlled high-power-factor boost rectifier with slope compensation,” in Proc. Applied Power Electronics Conf. (APEC), San Jose, CA, 1996, vol. 2, pp. 807–813. [6] D. Maksimovic, “Design of the clamped-current high-power-factor boost rectifier,” IEEE Trans. Ind. Appl., vol. 31, no. 5, pp. 986–992, Sep./Oct. 1995. [7] J. P. Gregner and C. Q. Lee, “Linear peak current mode control: A simple active power factor correction control technique for continuous conduction mode,” in Proc. Power Electronics Specialists Conf. (PESC), Baveno, Italy, 1996, vol. 1, pp. 196–202. [8] R. Redl and B. P. Erisman, “Reducing distortion in peak-currentcontrolled boost power-factor correctors,” in Proc. CIEP, Puebla, Mexico, 1994, pp. 92–100. [9] K. Mahabir, G. Verghese, J. Thottuvelil, and A. Heyman, “Linear averaged and sampled data models for large signal control of high power factor AD-DC converters,” in Proc. Power Electronics Specialists Conf. (PESC), San Antonio, TX, 1990, pp. 372–381. [10] D. J. Perreault and G. C. Verghese, “Time-varying effects in models for current-mode control,” in Proc. Power Electronics Specialists Conf. (PESC), Atlanta, GA, 1995, vol. 1, pp. 621–628. [11] E. A. Mayer and R. J. King, “Previously unobserved effects of delay on current-mode control,” in Proc. Power Electronics Specialists Conf. (PESC), Charleston, SC, 1999, vol. 1, pp. 13–18. [12] Y. Lo and R. J. King, “Sampled-data modeling of the averaged-input current-mode-controlled buck converter,” IEEE Trans. Power Electron., vol. 14, no. 5, pp. 918–927, Sep. 1999. [13] G. K. Andersen, “Average current control of a buck + boost PFC rectifier for low cost motor drives,” in Proc. Nordic Workshop Power and Industrial Electronics (NORPIE), Aalborg, Denmark, 2000, pp. 174–179. [14] M. Dawande and G. K. Dubey, “Bang-Bang current control with predecided switching frequency for switch-mode rectifiers,” IEEE Trans. Ind. Electron., vol. 46, no. 1, pp. 61–66, Feb. 1999. [15] D. Maksimovic, Y. Jang, and R. W. Erickson, “Nonlinear-carrier control for high-power-factor boost rectifiers,” IEEE Trans. Power Electron., vol. 11, no. 4, pp. 578–584, Jul. 1996. [16] J. Rajagopalan, F. C. Lee, and P. Nora, “A general technique for derivation of average current mode control laws for single-phase power-factorcorrection circuits without input voltage sensing,” IEEE Trans. Power Electron., vol. 14, no. 4, pp. 663–672, Jul. 1999. [17] M. C. Ghanem, K. AI-Haddad, and G. Roy, “A new single phase buck–boost converter with unity power factor,” in Conf. Rec. IEEE-IAS Annu. Meeting, Toronto, ON, Canada, 1993, vol. 2, pp. 785–792.


Gert K. Andersen was born in Hov, Denmark, in May 1974. He received the M.Sc. degree in electrical engineering from Aalborg University, Aalborg, Denmark, in June 1998. His master’s thesis was entitled “Power Factor Optimized Control of a Two-Phase Switched Reluctance Motor (4/2-SRM) Drive.” The thesis considered a new low-cost drive topology with near-unity power factor based on a 4/2-SRM. He is working toward the Ph.D. degree in electrical engineering in the Section of Power Electronic Systems at Aalborg University. His research area was component-minimized single-phase to three-phase converters for induction-motor drives. The main topics in the project are simple and sensor minimized control of single-phase to three-phase induction-motor drives, input power factor correction (PFC), converter design, and simulation of power-electronic systems. Since February 2005, he has been with Vestas Wind Systems A/S, Randers, Denmark. His main research areas are in the field of power-converter topologies, modulation technique, sensorless control of induction machines, and simulation of power-electronic systems.

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Frede Blaabjerg (S’86–M’88–SM’97–F’03) was born in Erslev, Denmark, on May 6, 1963. He received the M.Sc.E.E. and Ph.D. degrees from Aalborg University, Aalborg, Denmark, in 1987 and 1995, respectively. He was employed at ABB-Scandia, Randers, Denmark, from 1987 to 1988. He became an Assistant Professor in 1992 at Aalborg University, an Associate Professor in 1996, and a Full Professor in power electronics and drives in 1998. He has authored or coauthored more than 300 publications in his research fields, including the book Control in Power Electronics (Academic, 2002). He is an Associate Editor of the Journal of Power Electronics and the Danish journal Elteknik. Dr. Blaabjerg received the 1995 Angelos Award for his contribution in modulation technique and control of electric drives, and the Annual Teacher prize at Aalborg University in 1995. In 1998, he received the Outstanding Young Power Electronics Engineer Award from the IEEE Power Electronics Society. He has received five IEEE Prize Paper awards during the last five years. In 2002, he received the C.Y. O’Connor fellowship from Perth, Australia, the Statoil-prize in 2003 for his contributions in Power Electronics, and the Grundfos-prize in 2004 for his contributions in power electronics and drives. He is an Associate Editor of the IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS and the IEEE TRANSACTIONS ON POWER ELECTRONICS. He has held a number of chairman positions in research policy and research funding bodies in Denmark.