Current Programmed Control of a Single Phase Two-Switch Buck-Boost Power Factor Correction Circuit Gert K. Andersen, Frede Blaabjerg Aalborg University, Institute of Energy Technology, Denmark
[email protected] be 0 2 d 5 1/2 or 1/2 2 d 5 1 depending on the control strategy which will be shown later. Limit cycle, hysteresis or bang-bang current control is a simple technique which is sensitive towards noise in the same manner as CPC and this technique also requires two current reference generators[l4]. In addition, hysteresis control, in its most simple structure, has a variable switching frequency. Borderline control is basically a hysteresis control technique where the lower boundary is zero. In addition there exist some types of control techniques which requires no direct current reference and are therefore relative immune towards input voltage distortions[151,[161. Compliance with IEC-610003-2 depends strongly on the choice of switching frequency and switching inductance for CPC whereas ACC and limit cycle control are able to comply with IEC-61000-3-2 reI. INTRODUCTION gardless (practically) of the switching frequency and the EGULATIONS like IEC-61000-3-2 demand some sort switching inductor. A summary of these statements are of input current shaping for single phase equipment [l]. listed in Table I. Active current shaping is usually used in the power range around 2 kW in order to reduce the volume of the converter CPC is an interesting control method when costs and and the converter usually consists of a conventional diode complexity must be minimized at the expense of line curbridge followed by a dc-dc switch-mode converter which rent performance. shapes the current. An active power factor correction (pfc) This paper describes a new simple CPC technique with circuit with variable output dc-voltage as a supply in a low- constant command current and without ramp compensacost adjustable speed induction motor drive is interesting tion for the two-switch buck-boost pfc converter capable from a drive-design point of view because there exists only of complying with IEC-61000-3-2. The output dc-voltage high switching frequency in the rectifier. The pfc control can be varied by adjusting the command current and the technique in a low-cost motor drive must be simple and application used here is a pfc dc voltage supply for a PAM robust. inverter. Since no commercial IC exists for controlling this There exist a variety of control techniques for switch mode converter topology a control strategy based upon existing converters and power factor correction circuits and most of CPC ICs is developed and tested in the laboratory. these techniques are supported by commercial and available ICs for the basic converter topologies like boost, buck, 11. CURRENTPROGRAMMED CONTROL buck-boost, push-pull, forward, flyback, sepic, kuk etc. [2], Current Programmed Control (CPC) has been described [3]. Different pfc control techniques are compared in [3]. Average Current Control (ACC) is relative immune to- heavily in the literature (cf. [2]-[12]) and the major issue wards noise because only average signals are used but ACC has been the stability analysis because conventional CPC requires a current reference generator which may be expen- inherently becomes unstable, when the switch duty cycle sive. CPC is inherently more sensitive towards noise and is greater than 1/2. Ramp compensation can be added in circuit layout must be done very carefully but CPC is a sim- order to expand the range of stability. Fig. l a depicts the ple control technique which provides cycle-by-cycle current basic idea behind CPC for continuous conduction mode. limiting, and the use of a wave-shaping reference generator The switch is turned on at the beginning of each switchcan be omitted. Stability of CPC has been subjected to in- ing period and the switch is turned off at the time instant tense study in the literature (cf. [2]-[12])but stability is not when the inductor or switch current equals the command an issue if the switch duty cycle is restricted into a range current IC. This kind of C P C is here denoted as Upperequal to one half of the switching period. This range can Boundary-Current-Programmed-Control (UBCPC). AbstractThis paper presents a new Current Programmed Control (CPC) technique for the cascaded two switch buck-boost converter suitable as a low-cost Power Factor Correction (pfc) rectifier in a variable speed motor drive. This new C P C technique, which is an extension of the conventional CPC method, enables variable output dcvoltage and is therefore suitable in a Pulse Amplitude Modulated (PAM) motor drive or as an universal input power supply. The CPC method is very simple and requires only a constant current reference without any changes at the transition between boost and buck operating mode and the line current is practically unaffected by the topology mode shift. The presented control technique is verified by simulations and experimental results and compliance with IEC 61000-32 class A is achieved. The experimental setup is based on a commercial C P C IC for dc-dc converters.
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0-7803-6618-2/01/$10.000 2001 IEEE
350
CONTROL TECHNIQUES FOR P F C
CIRCUITS.
TABLE I t FORCONVENTIONAL IMPLEMENTATION.
DEPENDS ON
THE NOMINAL POWER LEVEL.
DCM:
DISCONTINUOUS CONDUCTION MODE, CCM: CONTINUOUS CONDUCTION MODE.
1
Control Technique Average Current Peak Current Current Clamping Hysteresis Borderline Automatic
4
O
11
Frequency t
I
Constant
Operating Mode DCM+CCM
Constant
DCM+CCM
Constant
DCM+CCM
Variable Variable Constant
DCM+CCM Borderline DCMSCCM
I
Line Current Harmonics Low Low/ Medium Low/ Medium Low Low Medium/High
I
Cost
I
Complexity
High
High
Medium
Medium
Low
Low
Medium Low Low
Medium Medium Low
I
4
T
2
4
T
t
0
T 2 T t b)
Fig. 2. Two switch Buck-boost converter topology.
Fig. 1. Waveforms of inductor current ZL and the switch control signal q for a) Upper-Boundary-CPC and b) Down-BoundaryCPC
Fig. l b shows another CPC technique where the switch is turned off at the beginning of each switching period and the switch is turned on a t the time instant when the inductor current drops to the command current I,. This kind of CPC is here denoted as Down-Boundary-CurrentProgrammed-Control (DBCPC). UBCPC correspond to the conventional CPC technique used in the literature. UBCPC has inherently an overcurrent protection and the average inductor current per switching period is always lower than the command current. In contrary, DBCPC needs an additional over-current protection which can be realized by a single comparator. The average inductor current per switching period is always higher than the command current for DBCPC. Since UBCPC detects the current during the on-time of the switch the switch current can be measured which is not possible in DBCPC because DBCPC detects the current during the off-time of the switch. Detecting the switch current enables switch protection and the current detecting resistor has lower omich losses because the current only flows during the on-time. Premature detection of the switch instant can be a problem when detecting the switch current because the switch current is the sum of the inductor current and the diode reverse recovery current during turn-on. Since DBCPC only detects the current during the off-time of the switch the noise problems related to reverse recovery current are eliminated. Both UBCPC and DBCPC will be used in this paper.
111. CONVERTER TOPOLOGY Single phase Power Factor Correction (pfc) in the power range around 2 (kW) is usually achieved by a conventional boost converter. If the dc-voltage has to be varied according to the actual operating point a buck-boost or buck type of converter must be utilized. The two switch buck-boost rectifier shown in Fig 2 is found to the most promising buck-boost topology in [13] for single phase power factor correction with variable dc-voltage at the power level around 2 kW and this topology is therefore selected for analysis in this paper. This converter is described in [17]. The converter has two operating modes: a buck mode and a boost mode. Buck mode occurs when the rectified voltage vref is higher than the dc-voltage U&, and boost mode occur when the rectified voltage is lower than the dc-voltage. The boost switch (sz) is turned off constantly in buck mode and only the buck switch (SI) is modulated in buck mode. The buck switch is turned on constantly in boost mode and only the boost switch is modulated in boost mode. A disadvantage of the buck-boost topology is the need for a mode detection function. Previously, no reported CPC technique has been adapted to the present buck-boost topology and commercially control ICs are only available for UBCPC. The developed CPC technique will be described here and is shown in Fig. 3. When the converter operates as a boost converter UBCPC is used with a constant current command and without ramp compensation which means that the duty cycle is limited to 1/2. The inductor current ripple decreases to zero as the rectified voltage increases towards the dc-voltage because the on state inductor voltage becomes zero. The boost
35 1
steady-state
waveform \
r
(W+Z)T wT
T
4
t
Perturbed
Fig. 3. Simulated waveform at Vd,= 250 V. Top: rectified voltage (v,,,), dc-voltage ( v d , ) and converter mode (mode). Middle: Inductor current ( i ~ )and bottom: duty cycles.
switch duty cycle also drops to zero.
(W+i?))T wT
The average input current per switch period increases from the zero crossing towards the point where the dcvoltage and the rectified voltage becomes equal and the converter shifts to buck mode. If UBCPC is used in the buck mode then the average input current per switch period will decrease when converter shifts from boost mode to buck mode if the same current command is used which introduces low order harmonics. If DBCPC is used in the buck mode then the average input current per switch period will continue to increase as it did in boost mode. Thus, :$
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respectively and the command current is constant then the average input current per switch period will be unaffected by the topology mode shift. Fig. 3 also shows the duty cycles and it appears that the buck duty cycle decreases smoothly from unity at the topology mode shift but the buck switch duty cycle is higher than 1/2 in the entire buck range. Conventional CPC without ramp compensation becomes unstable when the duty cycle exceeds 1/2 and the next section will describe the stability in a generalized manner regardless if UBCPC or DBCPC is used.
T
Fig. 4. Definition of waveforms for a) UBCPC and b) DBCPC.
and the current at the switching instant i ~ ( w Tis)
i ~ ( u r T )= i~(O)+m,wT i ~ ( w T-) i~(0) w = m,T
.
ZL(T)
The slope before the switching instant is denoted m, and the slope after the switching instant is denoted mu and, consequently, the corresponding duration are denoted w and U respectively. Fig. 4 show the definition s of the inductor current steady state and perturbed waveforms in UBCPC (Fig. 4a) and in DBCPC (Fig. 4b).
(1) (2)
=
I
i~(urT)+m,uT
+
(3)
(4) Thus in steady state (m, = M,, U ) the volt-second balance yields 0
The stability range of CPC is generalized here and the derivations is based on the simple model as presented in [2]. This known model assumes constant current slopes and neglects the effects of the modulator. The analysis assumes that the current slopes (man, m , f f ) and the command current I , are constant during a switch period.
*
where i~(0) is the current at the beginning of the switching . . m1 . m. .. .. .. . . . . period i'he current. at. the end or the switching period becomes
mu = Mu, w = W,U =
= M,WT+M,UT
IV. STABILITY -
t
+
(5)
This equation shows the volt-second balance in steady state, where the error is zero. In the ideal case the entire range of switch duty cycle can be utilized without stability problems but these ideal considerations are not sufficient in reality because stability becomes a problem due to noise, delays and other nonideal effects. The stability will be calculated and analysed by introducing a small perturbation ~ ( 0of) the initial inductor current i~(0)(cf. Fig. 4). The current becomes
At first the ideal case is shown where the error is zero 352
iL(o) = I,(o) + E , l ( 0 )
where
JE,~(o)J
IIL(o)l (7)
Where IL(O) is the ideal steady state inductor current at the beginning and at the end of a switching switching
~
TABLE I1
STABILITY FOR UBCMC A N D DBCMC.
period. It should be noted that the error relates to the deviation from steady state operation. The current error at the switching instant and at the end Q ( T )of the switching period are
Fig. 5. Control diagram.
where G denotes the perturbed value of w. Equation (8) shows the relation between the initial error and the error after a switching period. After n-switching periods the error can be written as
where
v.
Top Inductor current Fig. 6 . Simulated waveforms at U&= 250 and the reference current. Middle: Error current and topology mode signal. Bottom: Error current to the comparator.
When n increases towards infinity the error becomes
turned on in the entire boost mode and the boost switch turned off in the entire buck mode. Fig. 6 shows simulated waveforms at v d c =250 V and fig. 7 shows measured waveforms at Vd, =250 V. The bottom
Thus, the stability is determined by the variable p which demands W < 0.5 but there has been no assumption on whether W is the switch duty cycle D or the complement of the switch duty Q = 1 - D cycle. Table I1 depicts the stability range without ramp compensation for UBCMC and DBCMC respectively. The generalized description shows that the stability range is inverted when changing between UBCMC and DBCMC. Thus, stable operation with duty cycles greater than 0.5 can be achieved without ramp compensation by using DBCMC. V. REALIZATION Fig. 5 depicts the control diagram of the developed CPC technique. The control is based on a commercial CPC control IC for dc-dc converters with limited duty cycle. In order to implement the DBCPC technique when the converter operates in buck mode the error signal and the gate signal are both inverted. The error signal is inverted in buck mode by the multiplier. The signal to the multiplier from the mode signal is unity in boost mode and is equal to -1 in buck mode. Thus the multiplier has no effect in boost mode. The logic on the output makes the buck switch
plot shows the error signal feed to the current comparator and the inversion of the error signal in buck mode is obvious. VI. RESULTS Simulation and experimental results are presented and compared. Table I11 depicts the nominal system parameter used. It should be noted that no design optimization has been done in order to select the values listed in table 111. Fig. 8 shows the inductor current, the rectified voltage, the dc-voltage and the topology mode signal. It appears how the converter shifts between UBCPC and DBCPC when the rectified voltage signal crosses the dc-voltage signal. Fig. 9 and 10 shows simulated and measured waveforms at v d c =220 V respectively, and Fig. 11 and 12 shows simulated and measured waveforms at V d c =250 v respectively. From fig. 6-12 it can be seen that simulations and measuremente exhibit similar waveforms and verifies the functionality of this CPC technique developed t o the two-switch buck-boost converter. The line current is practically unaf-
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