Customised Reconfigurable Block-based Architecture for Baseband Data Processing in Telecommunication Applications. Simon Leung1, Adam Postula1, Ahmed Hemani2 1 The University of Queensland, Department of CSEE, St. Lucia, QLD 4072, Australia.
[email protected],
[email protected] 2 Royal Institute of Technology, ESDLab, Electrum 229, 164-40 Kista, Sweden.
[email protected] the performance of the hardware. In addition, power consumption must remain comparable as today.
Abstract We carried out a detailed analysis of many circuits used in telecommunication applications and identified some common circuit structures, as well as many different unique circuit elements. Therefore, these circuits are unsuitable to be placed and routed on a homogeneous array structure. A customised programmable structure with flexible circuit building blocks is a much better approach. These blocks have special parameters for fast reconfiguration. Local reconfigurability also reduces the number of costly global connections. This architecture is suitable for systems with a clear data flow like telecom systems. Using the GSM base band signal encoders as a test case, we obtained the performance, delay and power consumption of the new blocks mapped on a generic ASIC library. The resulting circuit is reprogrammable but much smaller and more power efficient than the design mapped on field programmable gate array and digital signal processors.
Introduction The successful design for the next generation telecommunication hardware can be characterised by: • • • • •
a large increase in bit rate, a decrease in power consumption, multiple protocol support, support for future extensions, and a short product development-to-market time.
Bit rate increase is unavoidable in the migration from current 2nd generation (2G) to new 3rd generation (3G) systems. A good example is the move from 14.4kbps data service to at least 384kbps [1] to support some wireless multimedia functions, such as streaming video or real-time voice and video communication. The data rate will increase by 26 times and so should
Users expect more functionality from their handsets, such as larger screen, which consumes more power. However, they expect the standby time to increase as well. The number of channels is also increasing, hence base stations must minimise the power consumption per channel. Reducing circuit complexity is a way of lowering power consumption. Custom designed circuit carries this advantage over generic processor structures. Due to the large installed base of existing 2G hardware, current protocols are expected to be in use in 2010 with 50% market share (approximate 500 million users) [2]. The other half will be 3G hardware. 3G technology is based on many 2G technology with new protocols. All these protocols also differ around the world. Hence, the hardware must support many protocols. A good flexible hardware design is a must. New telecommunication standards emerge very often. The time needed for development must be kept as short as possible to stay competitive in the market. Currently, solutions using DSP is widely adopted because it is flexible across many standards and allows fast development. However, if a custom designed circuit can be made flexible and accommodate future telecommunication standards, then it can serve as a better alternative. Hence, a scalable parameterised custom design is very desirable. In later sections we examine a hardware architecture developed to tackle these issues. The analysis prompts for a new parameterised functional block based hardware structure. The advantages of this structure are discussed. Using an example based on GSM phase 2+ standard [3], we compare the difference in the area, delay and power consumption of the implementations with the new block structure and with commercial FPGAs.
Development of the Architecture
within these standards, for example, in the modulation radio block (see Table 2). System Modulation Scheme Other Info.
Design Methodology
Gaussian filter Root-raised DAMP π/4 DQPSK cosine filter Offset Quadrature PSK 64 Walsh IS95 functions Table 2: Radio modulation comparisons. GSM
A systematic approach was adopted in designing the reconfigurable hardware for telecommunication circuits. We began with an analysis of the system requirement of the three wireless telecommunication standards commonly used around the world: DAMP, GSM and CDMA-IS95. We found that the system architecture of the three standard can be described in Figure 1 (the data flow in the receiver chain has an opposite direction). Analog Speech
Burst Formatting
Ciphering / FEC
A/D vocoder
Interleaving
Modulation Radio
Data Coding
Channel Coding
Noisy Wireless Radio Channel
Figure 1: Architecture of a telecommunication system for transmission of one channel. We then examined each of the blocks in the three standards. Many common structures were identified in the channel coding block of the various standards, i.e. data coding, channel coding, interleaving and burst formatting. Some common functionalities are listed in Table 1 [4] [5]. System
Channel Coding
Interleaving
GSM
½ rate binary CRC fire code with multiple stage ¼ rate CRC code with multiple stage
20ms multiframes
2 frames specified by matrices ½ and ¼ rate 20ms w/ variable IS95 binary code dimension matrices Table 1: Channel coding comparisons. DAMP
Even within the channel-coding block, there are many unique structures. For example, the elements and connections needed to build CRC generator are very different to the sources needed for the interleaver. In addition, distinctly different structures are also found
0.3 GMSK
Any homogeneous array structures will need lots of extra programmable connections and functions to make up all the required functionality because of these distinct structures [6]. This will add to circuit complexity and resource wastage when the extra circuits are not utilised. Circuit flexibility is crucial in any circuit design used in telecommunication. The handsets and base stations must support many standards and modes of operation. To further complicate this matter, there are also many variations within even one single standard! This can be easily seen from an excerpt of the GSM encoding parameters shown in Table 3. Mode
Frame size
Convolution polynomials
Interleaving
Diagonal 1+ D3+D4 8 blocks 1+D+ D3+D4 EFS 1+ D3+D4 Diagonal 1+D+ D3+D4 8 blocks Diagonal HR 1+D2+ D3+D5+D6 4 blocks 1+D+ D4+D6 1+D+D2+ D3+D4+D6 Diagonal F4.8 60 bits 1+D+ D3+D4 22 1+ D2+D4 blocks 1+D+ D2+D3+D4 (1+D+ D3+D4) / h AFS 95 to Diagonal 2 4 244 (1+D +D ) / h 4 blocks bits h = (1+D+D2 +D3+D4) Table 3: Examples of GSM Phase 2+ channel encoding parameters. FS
260 bits 244 bits 112 bits
Since the flexibility of the circuit apparent, the use of digital signal processors (DSP) is currently very common among telecommunication system implementations. DSP is best handling fixed bitlength words. However, the bit-length of words varies within one standard. Operations on the unused bits are redundant. In addition, since the data flow and operations are predictable in telecommunication
circuits, the overhead associated with running a processor (e.g. instruction fetching, decoding, execution etc.) to provide flexibility is not justified. It introduces extra redundancy and leads to longer critical path, performance degrade and higher power consumption.
to bypass other functional blocks if necessary. There may be modes of operation where particular functional blocks are not needed. The data can be routed around the blocks via the programmable connections and the shared bus. A/D vocoder
We have also considered the FPGA approach: repetition of the same fine-grain cell within a structure [7]. Data paths and custom circuits can be created using reconfigurable connections and switches. Some researchers have performed statistical analysis on the resources needed in the telecommunication circuits and embedded those functions in an enhanced FPGA structure [8]. They reported only minimum improvements from this approach. An improvement on the analysis procedure is needed. We incorporate many aspects other researchers have often ignored. In addition to statistical analysis, we have examined the circuit structure and patterns of interconnections. A formal classification procedure was derived for this purpose. It covered the topology aspects of the circuit: I/O data width, storage requirements and types, data flow, connection types and arithmetic requirements. The results of the classification show that there must be large flexibility within each functional block. There is also lack of common structures between the functional blocks. This indicates the potential advantages of a scalable block design approach over structures with repetitive fine grain cells. The scalable blocks contain customised hardware so they provide any special functions needed. They can also be easily replicated to accommodate larger parameter requirements. Reconfigurable Block-based Heterogeneous Architecture The results from the analysis of the classification suggest an architecture which consists of many separate reconfigurable functional blocks interconnected by programmable connections as shown in figure 2. Every functional block contains configuration registers which accept many parameters. The register stores configurations and set the block into different modes of operation in order to provide the flexibility across different standards. The data and channel coding blocks will be examined in detail in the later sections. The architecture provides a dedicated bus for direct connections between functional blocks. This bus is short and contains one programmable connection so it can be run at a high speed. The other bus, shared between all of the functional blocks, provides a path
Ciphering / FEC Modulation Radio
Data Coding
Burst Formatting
Channel Coding
Interleaving
bus Programmable connections
Figure 2: An architectural overview of the proposed system. This structure is based on the unique characteristic of telecommunication circuits: in most cases, their data paths are defined with a clear direction of data flow. This allows such simple bus architecture to be used. The advantages of this block-based architecture are: • • • • •
•
the circuit is smaller and more area efficient than DSP and FPGA because they are custom designed, the customised structure has little overheads irrelevant to telecommunication purpose, it requires less power than generic structures; blocks can be individually improved and optimised for higher performance, the blocks are tailor made, so the functionality is clearly defined. A rapid development system can be designed to generate the parameters quickly. this approach is also suitable for other applications in which the data flow is clearly defined in one direction. The blocks can be easily changed to include other functions or processing power.
Data and Channel Encoding Blocks The structure of the data and channel encoder block is described to demonstrate the concepts used in our design methodology. Design of the block The requirements listed from Table 1 and Table 3 have shown that we need a convolution encoder which can handle multiple rate as well as many different convolution polynomials. In some instances
a double convolution is also required. Other supporting functions, such as the CRC (or parity generation), are needed for this block. From the classification results we realised both structures require bit-storage and XOR gates. They have very similar connection patterns but only parity generator needs feedback. With reference to the fundamental convolution encoder and systematic parity generator structure [9] [10], we design an element to be replicated within this block to perform convolution encoding and CRC parity generation. Characteristics of the Building Element The building element used to build the generators is shown in figure 3. The XOR gate and the connected D flip-flop contribute to the bit propagation of the encoder. There are also three bit-configuration registers per element. Since convolution encoder requires no feedback while the parity generator requires feedback specified by the polynomial, the an configuration register controls the AND gate which determines whether feedback is propagated to the XOR gate. The ln register is used to disable any unused flip-flops. The cn register controls whether the output to be passed to the XOR gate needed for the convolution output.
an
ln
cn
en
D
Figure 3: An element of the array for channel encoding. There are three inputs and outputs in the element designed to connect to the next element in a daisychain style. Special elements are needed to terminate and complete the functionality of the encoder. Characteristics of the Generator Structure To demonstrate the operations, two generator examples will be used. In figure 4, the chain is configured as a CRC parity generator with polynomial g(D)=D3+D+1. The configuration registers enable or disable the flip-flops as needed. They control the feedback path and disable the XOR path. In figure 5,
the chain is configured as a convolution encoder with polynomial G=1+D3+D4. The feedback path is disabled. The correct convolution output is obtained by selecting the desired bits via the cn register to give. Often a convolution encoder has a rate of n/k, where n is number of input bits and k is number of output bits. This can be realised by replicating the chain with different configuration bits and multiplexing the output. m ode 0 0
0
1 1
D
0
1 1
D
0
0 1
D
M e s sa g e in p u t
0
D
Figure 4: CRC Parity Generator setup.
M essag e in p u t
01 D
0
01
0
D
01 D
1
01
1
D o u tpu t
Figure 5: Convolution encoder setup. VHDL Modeling and Results The array was fully described in synthesizable structural VHDL code. 14 building elements were used in the parity generator and 8 in the convolution encoder.The behaviour was simulated and the output was verified in the ModelSim environment. It was synthesised using Synopsys design compiler maintaining the array structure. We have used the LSI 10K ASIC standard cell library for synthesis. For comparison purpose, we made a corresponding encoder structure using Altera Flex8000 CPLD. We chose Flex8000 because it has FPGA-like logic elements and high speed regular connections, similar to our architecture. This allowed us to compare the two architectures, rather than technology. The results are show in Table 4 and Table 5: Attributes
Block (LSI 10K)
Flex8000
320 NAND units 31 Flex LEs Area 17.9mW Power 8.99µW 3.26ns 3.94ns Delay Table 4: Convolution encoder with 8 building elements. Attributes
Block (LSI 10K)
Flex8000
560 NAND units 80 Flex LEs Area 29.2mW Power 17.4µW 6.45ns 18.59ns Delay Table 5: Parity generator with 14 building elements.
The block design is much smaller and more power efficient than FPGA. More recent technologies, such as LSI G12 ASIC library, can improve the performance and power of our design by at least 20 times.
10. S.B. Wicker, Error Control Systems for Digital Communication and Storage, New Jersey: Prentice Hall, 1995.
Conclusions A systematic methodology was used to develop a reconfigurable telecommunication circuit. We classified the circuits according to statistical analysis, hardware structure and interconnection patterns. It led to an architecture which is a heterogeneous composition of reconfigurable functional blocks. The design accepted parameters to support many standards. A data and channel encoding block was designed, verified in VHDL and implemented in ASIC library. The results showed much performance improvements over FPGA architecture while the required flexibility was still retained.
References 1. Universal Wireless Communications, UWC-136 Standards for IMT-2000, 1999. 2. Siemens Private Communication Systems, 1999. 3. European Telecommunications Standards Institute (ESTI), Digital Cellular Telecommunications System (Phase 2+): Channel coding, GSM05.03 version 7.1.0, EN 300 909, 1999. 4. T.S. Rappaport, Wireless Communications: Principle and Practices, New Jersey: Prentice Hall, 1996. 5. K. Feher, Wireless Digital Communications: Modulation and Spread Spectrum Applications, New Jersey: Prentice hall, 1995. 6. M.J. Wirthlin, B.L. Hutchings, K.L. Gilson, “The Nano Processor: a Low Resource Reconfigurable Processor,” Proceedings for IEEE Workshop on FPGAs for Custom Computing Machines, pp. 2330, 1994. 7. J. Rose, A. El Gamal, A. SangiovanniVincentelli, “Architecture of Field-Programmable Gate Arrays”, Proceedings of The IEEE, vol. 81, no. 7, July, 1993. 8. A. Tsutsui, T. Miyazaki, K. Yamada, N. Ohta, “Special Purpose FPGA for High-speed Digital Telecommunication Systems”, Proc. ICCD’95, pp. 486-491, October, 1995. 9. B. Sklar, Digital Communications Fundamentals and Applications, New Jersey: Prentice Hall, 1988.
Simon Leung received the B.E. (Hon) degree in Electrical and Electronic from the University of Queensland, Brisbane, Australia in 1997. He is currently working towards a Ph.D. degree at the University of Queensland. Since 1997, he has worked in the field of reconfigurable hardware platforms, with emphasis on telecommunication applications and standards. His research interests include VHDL modelling and synthesis of digital system, FPGA architecture, microprocessor, memory, RISC and DSP architecture.
Adam Postula received the M.S. degree in electrical engineering from the Warsaw University of Technology, Poland, in 1974 and the Ph.D. degree in signal processing from the Poznan University of Technology, Poland, in 1981. He was an Electronic System Designer with ABB Sweden and a Researcher with the Royal Institute of Technology, Stockholm, Sweden, from 1983 and 1992. He led the development of high-level synthesis tools at the Swedish Institute of Microelectronics and was engaged in VHDL standardisation in Europe. Since 1995, he has been a Senior Lecturer in the Department of Computer Science and Electrical Engineering, the University of Queensland, Brisbane, Australia. His research interests include digital system design methodology, synthesis of digital systems, specialised processor architectures, and VLSI signal processing.
