Data Message Performance for the Future L1C GPS

Data Message Performance for the Future L1C GPS Signal P. A. Dafesh, E. L. Vallés J. Hsu and D. J. Sklar, L. F. Zapanta, The Aerospace Corporation C. R. Cahn, Consultant to The Aerospace Corporation BIOGRAPHY Dr. Phil Dafesh is the Director of the Digital Communication Implementation Department at The Aerospace Corporation. He provides management and technical direction of staff conducting design, development, and implementation of nextgeneration software defined radio, GPS, and wireless systems. He has contributed to the development of the modernized GPS signal structure and associated receiver processing for L1, L2C and M-code signals. Dr. Dafesh received B.S. degrees from California State Polytechnic University, Pomona in Electrical Engineering and Physics. He has authored over 35 publications and five patents in GPS and related technologies. Dr. Dafesh received M.S. and Ph.D. degrees in Electrical Engineering from UCLA. He is currently a member of IEEE, ION, Sigma Pi Sigma, and Tau Beta Pi. Dr. Esteban Vallés received his B.S. degree from University of Nacional del Sur in Bahía Blanca, Argentina, his M.S. degree from University of California, Irvine, and his Ph.D. from University of California, Los Angeles, all in Electrical Engineering. His areas of interest include channel-coding applications including low-density parity-check (LDPC) and algebraic codes, hardware implementation of error correcting code decoders, joint timing and carrier recovery problems. Prior to joining The Aerospace Corporation's Digital Communication Implementation Department in February 2007, he worked as an intern for Hitachi GST, the Jet Propulsion Laboratory, and Hughes research laboratories. Jason Hsu is a member of technical staff in the Signal Processing Systems Implementation Section at The Aerospace Corporation. His current work involves the development of modernized GPS user equipment and the implementation of software-defined radios on field-programmable gate arrays (FPGAs), utilizing embedded processors. He received his B.S degree in Computer Sciece and Engineering from University of California, Los Angeles, in 2004 and an M.S. degree in Electrical Engineering also from UCLA in 2006. His research interests include the design of embedded computing systems with an emphasis on power-aware systems and wireless sensor networks. Dean Sklar is a Senior Member of the Technical Staff at The Aerospace Corporation. He supports a variety of programs in the design and performance evaluation of modulation and channel-coding techniques, including the development of high-rate turbo coding schemes for use in wideband

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communication systems. He is also involved in the analysis and simulation of various modulation formats with improved bandwidth efficiency. He has published several technical papers and has a patent pending in the area of turbo-coding. Mr. Sklar holds an MS degree in Electrical Engineering from the University of Southern California and has been with The Aerospace Corporation since 1999. Laurence F. Zapanta received his M.S. degree in Electrical Engineering from MIT in 2005 and B.S. degree from University of California San Diego in 2002. As an undergraduate, he was a research fellow in the California Institute for Telecommunications and Information Technology in channel coding applications. In graduate school, he did his research in signal processing, nonlinear dynamics and chaos in biological signals. Before joining The Aerospace Corporation, he worked as an intern for General Electric in Ultrasound Communication System Design. His interests include communication system design, signal processing, channel coding and networking. Dr. Charles R. Cahn has been an independent consultant since 1998. Participant in GPS Modernization study for JPO and definition of new L5, L2C, and L1C civil signals. Vice President Technology, PROXIM Corp, 2000 to 2002. Chief Scientist, SiRF/STS, 1995 to 1998. Independent consultant, 1990 to 1995 after retiring as Vice President and Chief Scientist, Magnavox Advanced Products and Systems Company, 1962 to 1990. Analyzed spread spectrum multiple access during two summer studies organized by IDA (1964 and 1966). Proposed pseudo noise/frequency hopping modulation schemes for ICNI during a summer study (1967) at RADC. Studied next generation satellite communications during a summer study (1971) for DDR&E. Presented lectures on spread spectrum for NATO-AGARD (1973) and to the IEEE Section in India (1980). Bissett-Berman Corporation, 1960 to 1962; TRW, 1956 to 1960; Syracuse University, 1949 to 1956. Member Sigma Xi, IEEE Fellow, Honorary Fellow, ION, NAVSTAR Hall of Fame Award, GPS JPO, The Johannes Kepler Award, ION, 2004. BEE, Syracuse University, 1949; MEE, Syracuse University, 1951; PhD in Electrical Engineering, Syracuse University, 1955.

ABSTRACT The L1 C signal is being designed to optimize performance of a variety of attributes of the modernized GPS satellites, including data demodulation. In order to provide the L1C signal with the most robust interleaving and forward error control (FEC) coding possible, a study was conducted to select an optimal interleaving and coding approach. This paper will describe the results of the L1C interleaving and coding study and the performance of the selected LDPC FEC code for L1C. The work will also describe the performance of the L1C data structure relative to other GNSS navigation signals employing convolutional coding. Lastly, the work will discuss the complexity of the LDPC coding and interleaving approaches and the combined impact of coding, interleaving, and carrier tracking on the ability to obtain the L1C GPS message in degraded signal conditions. I. INTRODUCTION The L1C signal has been developed to provide enhanced capabilities to civilian users and interoperability with Galileo’s Open Service signal [1,2]. Previous modernized civilian signals such as L2C, L5 and Galileo’s civilian signals use (plan to use) convolutional coding with no data interleaving. These signals distribute 50% of the signal power to a data component of the signal and 50% of the signal power to a pilot (i.e., carrier) component of the signal, where a pilot code was provided to enable coherent carrier tracking using a phaselocked loop (PLL). One objective of the L1C signal is to enhance tracking performance for assisted GPS receivers without appreciably degrading GPS data demodulation performance when GPS clock and ephemeris data assistance is not available. To achieve this objective the L1C signal was designed to use 75% of the signal power in the pilot (i.e. carrier) component and 25% of the power in the data component. While this power distribution provides a 1.8 dB enhancement in carrier tracking for network assisted GPS receivers with recent clock/ephemeris data, it degrades data demodulation performance by 3 dB for GPS receivers that must demodulate broadcast ephemeris, as compared to L2C, L5 and Galileo signals employing 50% of the power in the data component. In order to maintain a performance benefit for assisted GPS applications, while providing an enhanced carrier signal component, the L1C signal employs a modern error control coding scheme and a means to enhance data demodulation performance through code combining, as will be described in the next section. Two approaches that were studied for the L1C signal included turbo-coding and Low Density Parity Check (LDPC) coding [3,4]. After exhaustive simulations, it was determined that LDPC coding provided comparable performance to turbo-codes. Moreover, since the concept of LDPC coding was never patented, these codes could be implemented on the GPS III satellites without concern over intellectual property rights that have been previously asserted for turbo codes, whose intellectual property rights are owned ION GNSS 20th International Technical Meeting of the Satellite Division, 25-28, September 2007, Fort Worth, TX

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by France Telecom [5]. Moreover, LDPC coding has been proposed for use on the new 4G wireless standard, and is part of the DVB-S2 standard used for high definition video. The L1C signal therefore provides the first navigation signal using modern advanced forward error control (FEC) codes approaching the Shannon capacity limit [6]. In addition to LDPC coding, data interleaving present on the LDPC signal is employed to provide enhanced performance under fading channel conditions such as may be the case for automobile navigation applications in urban environments. Lastly, the L1C signal also employs a robust Time of Interval (TOI) encoding scheme to permit identification of the L1C data frames within a data interval, as will be described further in the next section. The clock and ephemeris data is updated every 2-hour interval periods In the following sections, we will review the data message structure, LDPC code description, TOI code description and provide performance results for LDPC coding and interleaving in additive white Gaussian noise (AWGN) and Rayleigh fading channels. We will also investigate the impact of fading on carrier tracking threshold and describe the combined effect on decoded bit error rate (BER) for the L1C signal. During this investigation, both conventional PLL based data demodulation and a new dot product automatic frequency control (AFC) demodulator will be investigated with regard to tracking performance in the presence of Raleigh fading. Lastly, since LDPC encoding and decoding represent a new implementation for GPS satellites and receivers, results of an embedded software LDPC coder and decoder implementation will be described. II. L1C DATA MESSAGE DESCRIPTION For a review of the entire L1C signal specification, the reader is referred to [1]. The data message portions are reviewed here for completeness. A. MESSAGE STRUCTURE The basic L1C data message structure is shown in Figure 1. A frame is divided into three subframes that provide time, non-variable data, and variable data. Multiple frames (i.e., a superframe) are required to broadcast the complete set of data messages.

The TOI performance is quantified by the Eb/No required per coded bit. The theoretical probability of error for TOI can be upper-bounded by the union bound when the weight distribution A ( d ) of the error-correcting code is known. Because the error-correcting code is a group code, the probability of error is the same for all transmitted TOI words. Summing the pairwise probability of error over the weight distribution, the union bound at a specified Eb/No per coded bit is bounded by Perr < ∑ A( d j )Q ( 2d j E b / N o )

(1)

j

Figure 1: Data Message Structure Each frame consists of 9 bits of TOI data – Subframe 1, 600 bits of “non-variable” clock and ephemeris data with cyclic redundancy check (CRC)– Subframe 2, and 274 bits of “variable” data with CRC– Subframe 3. The content of Subframe 3 nominally varies from one frame to the next and each Subframe 3 is also identified by a page number. The content of Subframe 2 is nominally invariant over a period of multiple frames lasting nominally 2 hours, allowing Subframe 2 symbols to be combined over multiple messages for demodulation at lower values of C / N0 . The TOI data in subinterval 1 corresponds to the time epoch at the start (leading edge) of the following frame. This TOI data, together with Interval Time of Week data in Subframe 2, specify the satellite time within a GPS week with a resolution of 18 seconds. The 9-bit TOI data is encoded into 52 symbols using Bose, Chaudhuri, and Hocquenghem (BCH) coding described below. The 24-bit CRC scheme used in Subframes 2 and 3 is the same as used for L2C, L5, and SBAS navigation data. Each of the two Subframes (2 and 3) is further encoded using LDPC FEC coding and interleaving, as described in a following section. The resulting 1800 channel encoded symbols, representing one message frame, biphase modulate the spread data component at 100 symbols per second. B. ERROR CORRECTION FOR TIME OF INTERVAL The TOI word changes every fixed message frame and is encoded for error correction separately from the other contents of the data message. Since an interval may last for up to 2 hours, or 7200 seconds, there may be up to 7200/18 = 400 frames in an interval. Hence, the TOI must be represented by nine bits. The error-correcting code for TOI should give a low probability of error at the C / N0 that allows one repetition of the fixed message to be decoded with a low message-error rate. To get a low probability of error for TOI, the errorcorrecting code must have a high redundancy. The code selected for TOI is a BCH ( n, k ) linear code with a large minimum Hamming distance. Here, n is the number of coded bits and k is the number of data bits in the block.

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where Q ( x ) denotes the probability that a zero-mean, unit-variance Gaussian variable takes on a value greater than x . Equation (1) holds under the assumption that any phase errors from tracking carrier phase have negligible effect on the soft decisions for decoding. A search of BCH codes [7] yielded an attractive candidate for the nine-bit TOI: a BCH(51,9) with minimum distance 19. A 51-bit code word is generated by the 8-stage linear shift-register generator (LSRG) defined by the polynomial x8 + x 7 + x 6 + x5 + x 4 + x + 1 . Appending an overall parity extends the BCH(51,9) code with odd minimum distance to a (52,9) code with minimum distance 20, for which the weight distribution is: A ( 20 ) = 51 , A ( 24 ) = 204 ,

A ( 28 ) = 204 ,

A ( 32 ) = 51 ,

and

A ( 52 ) = 1 . The resulting 52-bit code word occupies a

duration of 26 data bits in the message frame. Evaluation of (2) yields Perr < 10−5 at Eb/No per coded bit of –1.8 dB, which is more robust than other parts of the encoded data message, as we will see in the next section. The receiver can readily generate the replica code words using a LSRG with the requisite feedback connections. It can then perform maximum-likelihood decoding by correlating the stored received soft decisions of the coded bits against all possible candidate TOI code words. This “brute-force” decoding is relatively simple because it is done at low speed, and the decoder has to retain only the single candidate code word that produced the maximum correlation. In addition, sensitivity can be improved through code combining (summing or otherwise using repeated soft decisions) over identical TOI words received from different satellites. C. LDPC CODES AND INTERLEAVING In recent years, there has been increasing interest in highly efficient error-correction codes such as turbo codes and LDPC codes. These codes approach the Shannon channel capacity of a communication system and operate at very low symbol signal-to-noise ratios (SNRs). The LDPC codes were proposed by Gallager in the early 1960s [3]. An LDPC code is a block code whose matrix H is sparse (i.e., the parity-check matrix is primarily populated by zeros). As in the case of turbo codes, LDPC

codes belong to the class of codes that can be efficiently decoded using iterative techniques [3], [8]. In [3], Gallager introduced several decoding algorithms for LDPC codes. One of these algorithms may be represented as a special case of the Sum-Product algorithm that has since been identified for general use in factor graphs and Bayesian networks [9]. Some forms of the Sum-Product algorithm are better suited for implementation than others. Given unlimited precision, however, all of these forms yield the same a posteriori estimation and we classify them collectively as the group of Full Belief Propagation (Full-BP) implementations. Even Full-BP algorithms suffer performance degradation as compared to the optimum maximum likelihood (ML) decoder for a given code. This is due to the fact that bipartite graphs representing finite-length codes without singly connected nodes are inevitably non-tree-like. Cycles in bipartite graphs compromise the optimality of Sum-Product decoders. The progressive edge-growth code conditioning technique [10] was used to design the LDPC codes in this work. Let x be the transmitted signal corresponding to a binary codeword c using BPSK modulation: x=2c-1. Let y be the received signal equal to the sum of x and channel noise. A message passing decoder tries to solve for the value of x based on the knowledge of y. There are many ways to describe a soft-decision message passing algorithm. The one used in this work exchanges log-likelihood ratios (LLRs) of the available information. The iterative decoding algorithms used in this work are commonly known as flooding algorithms. Many of the equations in the decoding algorithm are highly non-linear and require substantial simplification [8] before mapping to hardware. The implementation techniques used in this work are explained in Section IV. An (n,k) LDPC code is typically described using a paritycheck matrix H of dimensions (n-k)×(n) where k is the number of information bits and n is the codeword length. The L1C standard specifies an irregular (1200,600) code and an (548,274) irregular LDPC code [2]. A length 1748 interleaver is also used to enhance BER performance in fading channels. Figure 1 shows how Subframes 2 and 3 of the transmitted L1C message are LDPC encoded and later interleaved. LDPC codes were selected for L1C due to their block structure, superior performance, low implementation complexity, and non-proprietary technology. Different rate-1/2 irregular LDPC codes are used for the two subframes, because of their different lengths. Subframe 2 contains identical, repeating bits for each interval (lasting up to 2 hours), while Subframe 3 can change with each message. Since Subframe 2 is encoded separately from Subframe 3, the subframe symbols, even after being dispersed by the interleaver, remain invariant over the interval. Since phase tracking of the pilot component does not have a 180o ambiguity the receiver can then readily perform code combining of Subframe 2 symbols over multiple messages to read clock and ephemeris at progressively lower values of C/No. This provides an ability to obtain clock and ephemeris data at low C/No levels, even when network assistance is unavailable. Note that such code combining may be degraded ION GNSS 20th International Technical Meeting of the Satellite Division, 25-28, September 2007, Fort Worth, TX

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in a non-AWGN channel, such as one with Rayleigh fading or when a receiver experiences uncompensated dynamics. To mitigate correlated errors within a NAV frame, the 1748 encoded symbols of Subframes 2 and 3 are combined and interleaved using a block interleaver. The block interleaver can be visualized as a two-dimensional array of 46 columns and 38 rows depicted in Figure 2. Encoded symbols are sequentially written into the interleaver from left to right starting at Row 1. After Row 1 is filled, symbols are written sequentially into Row 2 in the same manner starting from the leftmost cell. This process continues until the 1748th symbol is written into the rightmost cell of the last (38th) row. Once all 1748 symbols are written into the array, the symbols are sequentially read out of the array from top to bottom starting at Column 1. After reading out the last (38th) symbol in Column 1, the symbols from Column 2 are read out in the same manner starting at the top and moving downward. This process continues until the last symbol in the (38th) cell of the last (46th) column is read out. Since the interleaving is the same for each message, the interleaved symbols from Subframe 2 occur at the same locations for each successive subframe, thereby remaining compatible with code combining discussed previously. Additional details on the LDPC and interleaver code description for L1C are described in [2].

Figure 2: L1C Block Interleaving Structure

III. LDPC CODE PERFORMANCE IN AWGN The performance of the L1C LDPC codes using 50 iterations is shown in Figure 3 and is summarized in Table 1 for the case of AWGN channels. Table 1: LDPC Code Performance Summary for AWGN L1 C Code Subframe 2

Input Block Size (bits) 600

Eb/No for BER= 10-5 (dB) 2.1

Eb/No for FER= 10-2 (dB) 1.6

Subframe 3

274

2.7

2

performance compared to L2C/L5 signals for network assisted GPS receivers or receivers with fresh clock/ephemeris data (within the last 2-4 hours). IV. REAL-TIME SOFTWARE IMPLEMENTATION OF LDPC DECODER Since the L1C signal is intended for civilian use, it is desirable to decode and correct bit errors in received GPS data message using rather low-end receiver hardware. Data demodulation in today’s C/A code GPS receivers is conventionally done in software. It is therefore desirable to determine the compatibility of LDPC coding with software implementations.

Table 1 presents both BER and frame error rate (FER) (i.e., subframe) for Subframes 2 and 3. Note that since bit errors are correlated for LDPC encoding, it is useful to consider both FER and BER in describing the code performance summary. Subframe 2, which is longer, benefits more from the LDPC code, providing the same FER/BER at approximately 0.5 dB lower Eb/No than Subframe 3. While FER is commonly used for LDPC performance assessment, this paper will use BER in the following discussions, as BER is more commonly used in legacy GNSS systems.

Furthermore, most of today’s GPS receivers have at least one on-chip CPU that produces position, velocity, and time (PVT) solution. If the same CPU can be shared for LDPC decoding, this offers a reduced silicon complexity that translates into a smaller, less expensive chip. In order to ascertain the feasibility of software implementation of LDPC decoders, an embedded software implementation of the GPS LDPC decoder was completed and is described in this section.

Figure 3 also compares the performance of the LDPC codes used in L1C to that of the convolutional FEC used in L2C and L5.

The block diagram of the L1 LDPC proof-of-concept system is shown in Figure 4. Physically the system consists of a Nallatech BenNuey motherboard with locations for up to three daughter-boards [11]. In this particular test setup, two Nallatech BenADDA daughterboards are used to host the encoder and decoder modules separately. Each BenADDA board has a Xilinx Virtex-2 field-programmable gate arrays (FPGAs), ZBT SRAM, and I/Os pins for inter-module communication. The actual encoder and decoder software are running on processors called MicroBlaze, which are soft-core microprocessors developed by Xilinx that are embedded in the FPGA [12]. It employs a RISC architecture with 32-bits, 3-pipeline stages and variable instruction latencies from 1 to 3 cycles. The processor is user configurable, allowing for use of various interfaces and functionalities according to system needs and constraints. Amongst other featuress, hardware division, multiplication, and a floating point unit (FPU), are supported [12].

1.E-01

R1/2, K=7 Convolutional Code

1.E-02

BER

1.E-03

R1/2, LDPC Block size 600

1.E-04

2.2 dB Improvement

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1.E-05

1.E-06

1.8 dB Improvement 1.E-07 0

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Figure 3: LDPC Performance in AWGN Notice that the LDPC codes provide about a 2 dB performance improvement in terms of BER, as compared to L2C/L5 under ideal timing conditions. Since L1C was designed to provide additional power to the carrier component (75% compared to 50% for L2C/L5), the L1C data demodulation requires a net of 1 dB additional signal power than L2C/L5. This difference may be compensated by increasing the power level of L1C compared to L2C/L5, or through the use of code combining as discussed previously. Therefore LDPC coding enables L1C to have comparable or better data demodulation performance, as compared to L2C and L5, while the carrier power of L1C is increased to permit a 1.8 dB enhancement in carrier tracking ION GNSS 20th International Technical Meeting of the Satellite Division, 25-28, September 2007, Fort Worth, TX

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A. Hardware System Overview

the table. This method performs significantly faster than the original one as it only involves a few memory accesses. Since it is not practical to store the results of every possible x into the look-up table, only the first few most significant bits of x are used as the index. In this test system, a 3500 points look-up-table is used and it results in almost identical performance as the original LDPC algorithm.

FPGA 2 (Xilinx XC2V6000)

MicroBlaze Encoder + AWGN

Input

MicroBlaze

Decoder

Compute BER

C. Performance Evaluation of Microblaze Implementation

Output

Figure 4: System Block Diagram of the L1 LDPC Proof-ofConcept System. The encoder on FPGA1 and the decoder on FPGA2 communicate through the direct local bus and the input and output are buffered by the FIFO to accommodate potential speed mismatch and data bursts. At the beginning of each test iteration, the encoder first encodes a sequence of randomly generated bits into codewords, based on the given LDPC matrix H, and then AWGN noise is added to simulate the noise in the channel. The noisy codeword is then sent to the module inside FPGA2 for decoding. Once the decoding is completed, the resulting message is sent back to the encoder. Subsequently, the BER is obtained at the encoder by comparing the decoded message against the original message. The total time spent by the decoder is also recorded to compute the average decoder throughput. B. Design considerations for real-time operation Since MicroBlaze, and most of the microprocessors employed in today’s GPS receivers are less powerful than processors of the modern PCs in terms of clock speed and hardware resources, special modifications to the original LDPC decoding algorithms are needed to speed up the computation. First of all, fixed point number representations are used instead of floating-point number because floating point operations take more clock cycles to complete than integer operations. As an additional benefit, this also reduces the hardware complexity by not having to include the FPU coprocessor in the MicroBlaze system. Secondly, any computationally intensive operations in the decoding algorithm will need to be optimized for speed. After carefully examining the decoding algorithm, the function y = log [tanh(x)], used in check node weight update, was found to be the most computational intensive [8]. Computation of this algorithm involves evaluating two non-linear functions in every iteration, which is proportional to the length of code. Instead of computing the value of y in real-time, which would take thousands of clock cycles, this function is pre-computed for a finite number of different inputs to fill in a look-up table during the initialization phase. During run-time, the value of x is only used as an index to look up the closest match of y in ION GNSS 20th International Technical Meeting of the Satellite Division, 25-28, September 2007, Fort Worth, TX

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In Figure 5, the BER curves for the L1C Subframe 2 (600 bit) and Subframe 3 (274 bit) 50-iteration implementation are compared. The PC simulation computes the actual value of –log[tanh(x)], and the MicroBlaze computes the approximate value by using the look-up table. Observe that the BER curves are almost identical for both implementations and impact is greater at higher SNR for both versions of LDPC decoders. To achieve the requirement of real-time operation, the decoder must be able to decode data at a rate higher than the incoming data rate. L1C ICD specifies an incoming symbol rate of 100 bps, which translates to a 50 bps output data rate for a rate ½ code. Figure 6 shows the throughput of the decoder when it is limited to 50 iterations, and the processor is clocked at 80 Mhz. Observe that the throughput is always above the minimum 50 bps and increases as the Eb/No becomes higher. At 2 dB Eb/No, the throughput is 1200 bps for Subframe 3, and 900 bps for Subframe 2, roughly 24 times, or 18 times faster than incoming data rate for Subframes 3 and 2, respectively. The ability to decode at this throughput demonstrates the ability to decode data from up to about 10 satellites simultaneously using a single processor running unoptimized code. 0

10

Microblaze (Sf. 2) Microblaze (Sf. 3) Simulation (Sf. 2) Simulation (Sf. 3)

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Figure 5: Decoding Performance (MicroBlaze Realtime Processor vs. Simulation)

Simulations determine that the threshold of carrier tracking on the nonfading channel for the postulated constant acceleration of 12.5 Hz/sec (≈0.25g at the L1 frequency of 1575.42 MHz or ≈ 0.3g at the L5 frequency of 1176.45 MHz) is C/No_carrier ≈ 21 dB-Hz in the carrier component, using a one-sided loop noise bandwidth BL = 12 Hz. For L1C with 75% of the total power allocated to the carrier component, this tracking threshold requires to a total C/No ≈ 22.2 dB-Hz. For L5 with 50% of power allocated to the carrier component, this tracking threshold corresponds to total C/No = 24 dB-Hz, a 1 dB degradation in threshold relative to L1C.

2500

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V. PERFORMANCE OF L1C VS L2C/L5 SIGNALS IN FADING CHANNELS

With the waveform structure of L1C or L5, with separate carrier and data components subjected to identical channel fading, AFC carrier tracking is an available alternative. A suitable restoring force for the AFC loop is the cross-product of pairs of successive output samples Ik-1Qk-Ik.Qk-1[13], [14]. A first-order AFC is assumed in

This section describes the performance of L1C vs L2C/L5 signals in correlated Rayleigh fading channels, representative of a vehicular application in a heavy multipath envionment. In the previous sections, we considered the performance differences due to data message performance including data rate, data vs pilot power, and the type of FEC used and FEC complexity. In fading channels, the degradation of the carriertracking threshold provides the ultimate limit on the sensitivity of GPS data messaging in non-ideal conditions. Therefore, we will first consider approaches to track the carrier in fading channels, followed by their impact on BER.

Although the AFC carrier tracking is not phase-locked, data demodulation can be done by taking the dot product of the carrier component and the data component, where we assume that the data and pilot are on the same carrier phase, resulting in the soft decision [13] for data detection of:

Figure 6: MicroBlaze Decoder Throughput

this paper, capable of tracking acceleration dynamics. The sampling rate is 100 Hz. The AGC attempts to follow the power of the fading signal by smoothing the power of the samples with a time constant = 4 sample durations (40 msec).

SoftDecision = I Carrier .I Data + QData .QCarrier

A. Carrier Tracking Performance in AWGN This section described the performance of L1C and L2C/L5 signals in AWGN for both AFC and PLL carrier tracking implementations. Using PLL carrier tracking requires a low probability of a phase slip since phase slips typically cause decoding errors and rejection of the data message by the CRC code. A phase slip is declared in our simulations when the phase error during a data frame differs from the phase error at the start of the data frame by more than 270o. A loop bandwidth BL was used to model the minimum bandwidth (best case performance) expected in the presence of satellite phase noise. B

Data extraction of L1C on the nonfading channel normally would be done by phase-locked carrier tracking of the carrier component to reconstitute a phase reference to demodulate the data component. The restoring force for the phase-locked loop is the quadrature output Q when the phase estimated by the loop is applied to the received signal plus noise. A second order PLL is assumed in this work capable of tracking acceleration dynamics. It is iterated at 100 Hz and has an Automatic Gain Control (AGC) that attempts to follow the magnitude of the fading signal by smoothing the magnitude of the samples with a time constant = 4 sample durations (40 msec). ION GNSS 20th International Technical Meeting of the Satellite Division, 25-28, September 2007, Fort Worth, TX

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(2)

Note that if the data and pilot are in phase quadrature, the above expression must be modified slightly to account for the quadrature phase. For L1C, the soft decision of the dot-product is de-interleaved the same as the soft decision for coherent data demodulation. With AFC carrier tracking, the dot product for data demodulation requires a low frequency error to avoid significant BER degradation. Since the peak restoring force occurs for a frequency error equal to 1/4 of the sampling rate, which is 100 Hz, a frequency slip of the AFC during a data frame is declared in the simulation if the absolute value of the frequency error at the end of the data frame exceeds 25 Hz. Smoothing is performed using a single-pole low-pass filter with a time constant of 10 samples. B. Carrier Tracking Performance in AWGN in a Rayleigh Fading Channel In order to introduce time correlation in the channel, the Rayleigh fading channel model in [15] is used. In this model, shown in Figure 7, the complex channel gain is derived from the output of the cascade of two identical single-pole, low-pass filters driven by complex white

70.00 60.00 L1C No dynamics, BL= 1 Hz

50.00 Threshold C/No (db)

Gaussian noise. The time constant, τ, of the poles characterizes the fading time-constant. The resultant envelope of the channel gain has a Rayleigh distribution with an average power of unity, and the resultant channel phase shift is uniformly distributed. However, we need to simulate the channel variation with time. The assumed sampling rate of the channel fading simulation in this work uses the L1C coded bit rate of 100 bps with rate-1/2 error correction to produce decoded data rate of 50 bps.

L2C/L5 No dynamics, BL= 1 Hz

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Figure 8: Impact of Rayleigh Fading on PLL Tracking Threshold. 60.00

Figure 7: Rayleigh Fading Model Figure 8 and Figure 9 assess the impact of Rayleigh Fading on PLL and AFC tracking thresholds, respectively. As a reasonable criterion, the required probability of a frequency slip is taken as less than 0.01. Simulation results were obtained for the threshold of AFC and PLL tracking on the fading channel for various values of τ, varying C/No in 5 dB steps until the above criterion is violated. With zero acceleration dynamics, BL is given a a value of 1 Hz, easily capable of tracking satellite phase noise. With 12.5 Hz/sec acceleration dynamics, BL is set at the value of 12 Hz, found optimum on the nonfading channel.

Threshold C/No (dB)

50.00 40.00 30.00 L1C w/o dynamics, BL= 1 Hz

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Conventional PLL results in Figure 8 are shown for L1C and L2C/L5 signal power ratios. These figures show that L1C provides about a 2 dB improvement in threshold performance of, as compared to L2/L5; this benefit is consistent with the 1.8 dB enhancement of L1C carrier power, relative to L2C/L5. As seen from Figure 8, conventional PLL tracking requires C/No levels above 40 dB for correlation times, τ, less than the data message period. Note that the PLL failed to not track at all for fast fading (when τ ≤ 10 sec). Note that for the case of signal dynamics due to receiver motion (for example in automobile applications), in addition to the carrier dynamics due to fading, a severe degradation is observed and the PLL fails to provide reasonable C/No thresholds (< 45 dB) at any τ. In Figure 9, AFC carrier-tracking performance is also shown for L1C and L2/L5, as compared to Figure 8. Notice that the AFC tracking loop enables carrier tracking in fast fading conditions and provides a 16-32 dB improvement in tracking for a 10 sec correlation time. Moreover, the AFC permits good performance (threshold C/No < 30 dB) for fast fading at both low and high dynamics, which may be desirable for automobile applications.

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Figure 9: Impact of Rayleigh Fading on AFC Tracking Thresholds. C. Data Demodulator Performance with Perfect Carrier Tracking Figure 10 illustrates the performance of the L1C signal as compared to L2C/L5 in the presence of fading for the case of perfect phase tracking. As described in the last section, PLL tracking failed to provide reasonable tracking performance under fast fading conditions. Therefore, we will focus our attention on the AFC using a dot product demodulator The results in Figure 10 were obtained by performing the dot product operation (Eq. 2) at the input to the data demodulator, assuming zero frequency error (perfect tracking). This operation incurs a squaring loss noise contribution according to the ratio of the data and pilot power. For 50%/50% power splits, this squaring loss will be about 3 dB, whereas for 75 % of the power in the data component (as in L1C), the loss is about 1.3 dB. We will revisit the BER performance results using imperfect AFC carrier tracking in a subsequent section.

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As observed in Figure 10, L1C provides approximately 9-16 dB improvement over L5 and L2C for fast fading conditions with a correlation time of τ = 0.5 sec. It is interesting to note that the performance of L2C is 6 dB better than L5 for τ = 0.5 sec due to the lower data rate of L2C which provides more averaging of the Raleigh fading than does the higher data rate L5 signal (i.e. the improvement is greater than the 3 dB improvement in energy per bit, as compared to L5).

As a result, we focus our attention to the BER simulation of a combined AFC/dot product loop carrier tracker demodulator. In order to investigate the performance with imperfect tracking, Figure 11 shows bit error rate performance of the convolutional (L2C) and LDPC (L1C) codes as a function of C/No (accounting for the carrier to data channel power ratio for L1C vs L2C). For simplicity, L1C results are only shown for the 600 bit subframe 2 data. Results for subframe 3 are similar.

Results for the L2C/L5 signals are not shown for correlation times greater than 0.5 sec since the required C/No is > 46 dB to achieve BER ~ 1e-05. Notice also that the performance of L1C in presence of fast Rayleigh fading (τ = 0.5 sec ) is about 5 dB worse than without fading using the dot product demodulator.

BER performance for the AFC loop with both convolutionally encoded (C.C.) and LDPC encoded signals is shown in Figure 11. Notice that these results are in good agreement with those of Figure 10, with a slight degradation due to carrier tracking in fading channel conditions. The good agreement is due to the fact that the AFC loop tracking threshold is well below 30 dB for all cases plotted in Figure 11.

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Therefore, in the case of perfect AFC tracking (dot product with zero frequency error), the L1C coding and interleaving structure permits improved data demodulation as long as the correlation time, τ, is less than the message length (i.e., τ < 18 sec). For large correlation times, the BER performance degrades severely even for ideal tracking, as expected due to the combination of the L1C block size and interleaver length.

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Figure 11 Performance in the presence of Rayleigh Fading with Dot Product demodulation and imperfect (practical) AFC tracking. For simplicity, L1C results are only shown for the 600 bit subframe 2 data. 25

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VI. SUMMARY AND CONCLUSION

Figure 10: Performance in the presence of Rayleigh Fading with Dot Product demodulation and perfect carrier tracking (zero frequency error). D. Data Demodulator Performance with Imperfect Carrier Tracking When perfect synchronization is not assumed, Figure 8 shows that the PLL circuit is not able to track fast fading channels, which is expected to cause the decoder to fail. With AFC tracking, Figure 9 illustrates that reasonable signal tracking thresholds are possible (down to C/No ~ 30 dB and 28 dB for L2C/L5 and L1C respectively).

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In conclusion, we have reviewed the data message structure, LDPC code description, interleaver description and TOI code description for the new L1C GPS signal. We have provided performance results for LDPC coding and interleaving in AWGN and Rayleigh fading channels. In addition, the work has investigated the impact of fading on carrier tracking threshold and determined that a new dot product demodulator implementation combined with AFC tracking was essential to tracking the L1C and L2/L5 signals in the presence of fast fading. Moreover, we have determined that the L1C data structure, as compared to L2C/L5, can provide roughly 916 dB of performance advantage in fast Rayleigh fading

channel conditions, and can provide comparable data demodulation performance in AWGN channels using a PLL. This result is obtained, even with a 1.8 dB enhancement in carrier tracking threshold performance for the L1C signal, at the expense of a 3dB loss in data signal power relative to L2C/L5. Lastly, since LDPC encoding and decoding represent a new implementation for GPS satellites and receivers, we have described the first results for an embedded software LDPC coder and decoder implementation, proving that the LDPC coding on L1C is compatible with existing software data demodulation approaches in modern GPS receivers. VII. ACKNOWLEDGMENTS The authors also acknowledge the support of the GPS Wing during the course of this work. The work was supported under contract No. FA8802-04-C-0001. VIII. REFERENCES [1] J. W. Betz, M. A. Blanco, C. R. Cahn, P. A. Dafesh, et.al., “Description of the L1C Signal,” Proceedings of ION GNSS, Sept. 2006. [2] NAVSTAR GLOBAL POSITIONING SYSTEM, “Navstar GPS space Segment/User segment L1C interfaces,” Draft IS-GPS-800, Aug 04, 2006 http://www.losangeles.af.mil/shared/media/document/AFD070803-064.pdf. [3] R. G. Gallager, Low-Density Parity-Check Codes, Cambridge, MA: MIT Press, 1963. [4] T J. Richardson and R. L. Urbanke, “The Capacity of Low-Density Parity-Check Codes Under Message-Passing Decoding”, IEEE Trans. on Inform. Theory, Vol. 47, No. 2, Feb 2001. [5] France Telecom Turbocodes and Licensing document,http://www.francetelecom.com/en/group/rd/news/th ematique/dossier_mois/ddm200505/att00032001/ddm200505. pdf. [6] C. E. Shannon, “A mathematical theory of communication,” Bell Syst. Tech. J., vol. 27, pp. 379–423 and 623–656, July and Oct. 1948. [7] Peterson and Weldon, Error-Correcting Codes, 2nd Edition, The MIT Press, 1972. [8] C. Jones, E. L. Vallés, M. Smith, and J. Villasenor, “Approximate-MIN constraint node updating for LDPC code decoding,,” Proc. of Military Comm.Conf. (MILCOM), vol. 1, pp. 157–162, Oct. 2003.

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[9] J. Pearl, Probabilistic Reasoning in Intelligent Systems: Networks of Plausible Inference.1em plus 0.5em minus 0.4emMorgan Kaufmann, 1988. [10] X.-Y. Hu, E. Eleftheriou, and D.-M. Arnold, “Irregular progressive edge-growth (PEG) tanner graphs,” Proc. IEEE Intl.Symp. on Inform Theory. (ISIT), July 2002. [11] Nallatech Web Site, http://www.nallatech.com/. [12] Xilinx Inc. Microblaze Processor Reference Guide V 7.0(http://www.xilinx.com/ise/embedded/edk91i_docs/mb _ref_guide.pdf). [13] Theodore S. Rappaport, Wireless Communications, Prentice-Hall PTR, 1996. [14] Charles R. Cahn, Improving Frequency Acquisition of a Costas Loop, IEEE Trans on Comm, Vol COM-25, pp 1453-1459, December 1977. [15] Robert L. Bogusch, Digital Communications in Fading Channels: Modulation and Coding, Mission Research Corporation for AFWL, Contract F2960-82-C0023, March 1, 1987.

(c) 2007 The Aerospace Corporation