DC-Link Capacitance Estimation in AC/DC/AC PWM Converters Using ...

IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 44, NO. 5, SEPTEMBER/OCTOBER 2008

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DC-Link Capacitance Estimation in AC/DC/AC PWM Converters Using Voltage Injection Ahmed G. Abo-Khalil, Student Member, IEEE, and Dong-Choon Lee, Member, IEEE

Abstract—In this paper, a new online capacitance estimation method for dc-link capacitors in a three-phase ac/dc/ac pulsewidth-modulation converter is proposed. A controlled ac voltage with a lower frequency than the line frequency is injected into the dc-link voltage, which then causes ac power ripples at the dc output side. By extracting the ac power component on the dc output side using digital filters, the capacitance can then be calculated using a support vector regression method. A function that defines the relation between a given capacitor power and its corresponding capacitance is determined using a set of training data. This function is then used to predict the output for the given input which is not included in the training set. The proposed method can be simply implemented with only software and no additional hardware. Experimental results confirm that the estimation error is less than 0.15%. Index Terms—Electrolytic capacitors, estimation, pulsewidthmodulation (PWM) converters, support vector regression (SVR), voltage injection.

I. I NTRODUCTION

A

LARGE number of power electronic systems, such as mill drives, elevators, uninterruptible power supplies, etc., employ three-phase ac/dc/ac pulsewidth-modulation (PWM) converters. The power converter technology has matured from the viewpoint of both circuit topology and control strategy. Electrolytic capacitors are commonly used in power converters as an energy buffer since they have a high energy-storage capability for their size and low price [1]. The aluminum electrolytic capacitor is composed of an anode and a cathode foil and a separator plate wound together and impregnated with an electrolyte, as shown in Fig. 1. The electrolyte contains a solvent and a solute such as ethylene glycol and ammonium borate, respectively. An increase in internal temperature accelerates the evaporation of the electrolyte of the capacitor. Therefore, the volume of the electrolyte is reduced so that the etched tunnels are not fully filled with the electrolyte. The reduction of the effective surface area, which acts as an IPCSD-07-126, presented at the 2006 Industry Applications Society Annual Meeting, Tampa, FL, October 8–12, and approved for publication in the IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS by the Industrial Power Converter Committee of the IEEE Industry Applications Society. Manuscript submitted for review July 30, 2007 and released for publication January 18, 2008. Current version published September 19, 2008. This work was supported by the Korea Research Foundation under Grant KRF-2005-041-D00305, funded by the Korean Government (MOEHRD). A. G. Abo-Khalil is with the Department of Electrical Engineering, Assiut University, Assiut 71516, Egypt (e-mail: [email protected]). D.-C. Lee is with the Department of Electrical Engineering, Yeungnam University, Gyeongbuk 712-749, Korea (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TIA.2008.2002181

Fig. 1. Structure of electrolytic capacitor.

electrode, decreases the capacitance. At a high temperature, the evaporation process is more accelerated. As a result, the lifetime of the electrolytic capacitor is further shortened [2]. The electrolytic capacitor usually has the shortest lifetime in power electronic circuits, which influences the total system lifetime. The nominal lifetime of electrolytic capacitors is typically 1000 to 10 h, not long enough for most applications [3]. Unfortunately, there is little information available on technical evaluations of electrolytic capacitors in PWM converters [4], [5]. Therefore, the deterioration diagnosis of the electrolytic capacitor needs to be investigated for the maintenance of the converter. Several methods to estimate the deterioration status of the electrolytic capacitor have been proposed; some methods are based on the fact that the loss of the electrolyte results in a decrease of the capacitor weight [5], and others are based on the claim that the wear-out mechanisms of the capacitor increase its internal equivalent series resistance (ESR) [6], [7]. The former methods are inherently inconvenient to use since the capacitors need to be removed to perform the test. The latter methods are also inconvenient to apply since either frequency analyzers or RLC meters are needed to measure the ESR. Both methods require removing the capacitors from the power circuit, which makes them unsuitable for online applications. Nevertheless, the methods based on the ESR variations are acceptable for estimating the lifetime of electrolytic capacitors [8]. On the other hand, Lee et al. [9] presented an online method to estimate the capacitance value in ac/dc/ac PWM converters without disconnecting the capacitor. Although disconnecting the capacitors from the system is unnecessary, it requires measuring or, at least, calculating the dc-link current and the dc-link voltage for applying the recursive least-squares (RLS) method. In this paper, a novel online capacitance estimation method for the ac/dc/ac PWM converter systems is proposed. This method involves injecting an ac voltage component into the dc

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link and then processes the ac power component of the capacitor using the support vector regression (SVR). The capacitor power can be calculated from the input power of the lineside converter and the output power of the load-side converter. The input and the output of the SVR estimator are chosen as the capacitor power and the capacitance, respectively. Through offline training, a particular model which relates the inputs to the output is obtained. Then, the capacitance can be calculated online with the input of the capacitor power. In addition, capacitance estimation by the RLS method is investigated, of which performance is compared with that of the SVR method. The effectiveness of the proposed capacitance estimation algorithm is verified by experimental results. This comparison indicated an estimation error of less than 0.15% in the case of the SVR method. II. I NJECTION OF AC V OLTAGE TO THE DC L INK A. AC Voltage Injection The dc-link voltage in ac/dc/ac PWM converters is constant in steady state except for switching-frequency-related ripple components. For the purpose of parameter estimation, it is difficult to extract effective information of the system with the constant voltage signal. Therefore, it is necessary to inject some exciting signal into the system. In this system, an ac voltage component at 30 Hz is added to the dc-link voltage reference as ∗ vdc,ripple

= Vac sin ωin t

(1)

where Vac = 10 V and ωin = 2πfin = 2π · 30 rad/s. If the frequency of the added ac voltage is higher, the current corresponding to this frequency becomes higher, and the bandwidth of the dc-link voltage controller needs to be higher, too. In the opposite case, measured signals are weak for acquisition. B. Design of a DC-Link Voltage Controller Considering that the precision of the capacitance estimation depends on the control performance of the injected ac voltage, the dc-link voltage should be controlled precisely. For this purpose, the dc voltage controller needs the feedforward compensation term together, as well as the feedback controller. If the converter loss is neglected, the instantaneous capacitor power pcap can be expressed as [9] pcap = pin − pout =

2 C dvdc 2 dt

(2)

where C is the dc-link capacitance, νdc is the dc-link voltage, pin is the input power of the line-side converter, pout is the output power of the load-side converter, and  3 e e vd id + vqe ieq 2  3 e e e e vds ids + vqs = iqs 2

pin = pout

e are the load-side d–q-axis voltages, and ieds and ieqs are the vqs load-side d–q-axis currents. ∗ If ied = ied = 0 at a unity power factor control in the line side, then

pin =

3 ee v i . 2 q q

(5)

Neglecting the voltage drop in the line-side input impedance pin =

3 e Ei 2 q

(6)

where E is the magnitude of the source voltage. From (2) and (6), the q-axis current reference for feedforward compensation is obtained as   ∗2 C dvdc 2 ∗ iqe,ff = + pout . (7) 3E 2 dt The dc-link voltage reference with an injected term in (1) is given by ∗ ∗ vdc = Vdc0 + Vac sin ωin t

(8)

∗ where Vdc0 is the dc component of the dc-link voltage reference. Differentiating the square of (8) and considering ∗  Vac Vdc0 2

∗ dvdc ∗ = 2ωin Vdc0 Vac cos ωin t. dt

(9)

Substituting (9) into (7), the feedforward compensation term is expressed as i∗qe_ff =

2 ∗ (ωin CVdc0 Vac cos ωin t + pout ) . 3E

(10)

Fig. 2 shows a control block diagram of the three-phase ac/dc/ac PWM converter with a capacitance estimation block. This block consists of a dc-link voltage control loop and two d–q current control loops. The d-axis current in a synchronous reference frame is controlled to zero for a unity power factor operation on the line side, whereas the q-axis current is controlled to keep the dc-link voltage constant. The instantaneous power of the dc-link capacitor can be calculated from (2). Applying the bandpass filter to both sides of (2)   2 1 dvdc (11) BPF[pcap ] = C · BPF 2 dt where BPF[·] means the bandpass-filtered quantity. III. S UPPORT V ECTOR M ACHINE FOR R EGRESSION

(3) (4)

where vde and vqe are the line-side d–q-axis voltages. The e and variables ied and ieq are the line-side d–q-axis currents, vds

A regression method is an algorithm for estimating the relationship between the system input and output from the samples or training data. An SVR is a new classifying theory which has been used in the field of pattern recognition, data mining, and, recently, motor condition prediction in [10]. In this section, the principle of the SVR is described briefly [11].

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ABO-KHALIL AND LEE: DC-LINK CAPACITANCE ESTIMATION IN AC/DC/AC PWM CONVERTERS

Fig. 2.

Fig. 3.

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Control block diagram of ac/dc/ac PWM converters for capacitance estimation.

Feature map from input to higher dimensional feature space.

Let us consider a set of training samples {(y1 , x1 ), . . . , (yn , xn )}, where xi and yi denote the input and output spaces, respectively, and n is the dimension of training data. The idea of a regression problem is to determine a function that can identify unknown parameters accurately [12]. The general SVR function for estimation takes the form of

The constraints include ε which specifies a permissible estimation error. The value of ε influences the number of support vectors used to obtain the regression function. As ε is lager, the support vectors selected are fewer. With a reasonable choice of γ, a tradeoff between minimizing the training errors and minimizing the model complexity term w2 is accomplished. The key idea to satisfy these constraints is to determine a Lagrange function from the objective function in (13) and the corresponding constraints in (14) using Lagrange multipliers αi and αi∗ associated with each sample as n 1 Γ (f (xi ) − yi ) L = w2 + γ 2 i=1 + αi (yi − w · Φ(xi ) − b − ε − ξi ) i

f (x) = (w · Φ(x)) + b

(12)

where w is a weighting matrix, b is a bias term, Φ denotes a nonlinear transformation from an n-dimensional space to a higher dimensional feature space (as shown in Fig. 3), and the dot represents the inner vector product. To calculate w, the following cost function should be minimized [13], [14]:

 n 1 2 Γ (f (xi ) − yi ) (13) Min w + γ 2 i=1 which is subject to |yi − w · Φ(xi ) − b| ≤ ε + ξi ,

i = 1, 2, . . . , n

ξi , ξi∗ ≥ 0 (14)

where ε is the permissible error and γ is a prespecified value that controls the cost incurred by training errors. The slack variables ξi and ξi∗ are introduced to accommodate the error on the input training set.

+



αi∗ (−yi + w · Φ(xi ) + b − ε − ξi∗ )

(15)

i

which is subjected to αi , αi∗ , ξi , and ξi∗ > 0. Now, (13) has to be minimized with regard to the primal variables (w, b, ξi , and ξi∗ ) and maximized with regard to the Lagrange multipliers αi and αi∗ . Therefore, by setting the gradient of L with respect to the primal variables to zero [14] ∂L =0 → w = (αi − αi∗ ) Φ(xi ) ∂w i ∂L =0 → (αi − αi∗ ) = 0 ∂b ∂L = 0 → γ = ξi∗ ∂ξi∗ ∂L = 0 → γ = ξi . ∂ξi

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(16) (17)

(18)

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TABLE I INPUT DATA FOR TRAINING

If the constraints in (16)–(18) are included in the Lagrange function in (15), an optimization problem is then obtained as Max −

n   1 (αi − αi∗ ) αj − αj∗ K(xi , xj ) 2 i,j=1

+

n

yi (αi − αi∗ ) − ε

i=1

n

(αi + αi∗ )

(19)

i=1

subject to n

(αi − αi∗ ) = 0, αi , αi∗ ∈ [0, γ]

i=1

where K represents the kernel matrix [11], which is defined as K(xi , xj ) = Φ(x) · Φ(xi ).

(20)

The optimization problem in (19) can be transformed into the final form as f (x) =

n

(αi − αi∗ ) · K(xi , x) + b

(21)

i=1

which is subject to 0 ≤ αi ≤ γ

0 ≤ αi∗ ≤ γ.

Fig. 4.

SVR model for capacitance estimation.

Fig. 5.

Flowchart for capacitance estimation using SVR.

The bias term b in (21) is expressed as a function of Lagrange multipliers and the kernel  n ∗ b = mean {yi − (αi − αi ) K(xi , xj )} . (22) i=1

Only the training samples whose corresponding Lagrange multipliers are nonzero are involved in the solution, and these training samples are called as support vectors. Several choices for the kernel are possible, which reflect the special properties of the following approximating functions [13], [14]: 1) polynomial kernel function K(xi , x) = [(xi , x) + 1]q where q is the polynomial degree; 2) radial basis function (RBF)

 |xi , x|2 K(xi , x) = exp − σ2 where σ is the Gaussian width. IV. C APACITANCE E STIMATION B ASED ON SVR In order to find the coefficients in (21), the parameters γ and ε should be known. These parameters are usually selected based on a priori knowledge and/or user expertise (γ = 400 and ε = 0.000005). Moreover, an RBF with σ = 20 is used as a kernel. Applying the SVR to estimate the unknown capacitance, the training data for input and output should first be specified.

In this model, the SVR input is the filtered capacitor power ˆ BPF[pcap ], and the output is the estimated capacitance C. An appropriate amount of input and output data is collected and then utilized in the training process to obtain the relation between the input and output. Let us consider the dc capacitor bank which is composed of five branches, i.e., four parallel-connected capacitors of single 500 μF and one branch of two series connections of 3900 μF. The nominal capacitance of the bank is 3950 μF, which corresponds to case A in Table I. It is assumed that the capacitance can be reduced to 1950 μF for offline training. The input data for training are listed in Table I. Fig. 4 shows the SVR model for the capacitance estimation. Here, the solid line and the cross and circled points represent the trained model, the unused training data, and the support vectors, respectively. Each vector in Fig. 4 corresponds to the data in

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ABO-KHALIL AND LEE: DC-LINK CAPACITANCE ESTIMATION IN AC/DC/AC PWM CONVERTERS

Fig. 6.

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System hardware configuration.

Table I. During offline training, the kernel function K(xi , xj ) is calculated for all support vectors. Fig. 5 shows the flowchart of the proposed method, which is described to: 1) collect enough set of training data (xi , yi ) and specify ε, γ, and σ; 2) compute the kernel function K(xi , xj ); 3) determine the Lagrange multipliers by maximizing the quadratic function in (15). 4) calculate the bias term b; 5) calculate the output of the estimator using (21) and (22) for any input x of the capacitor power. V. RLS A LGORITHM The SVR is an artificial intelligent estimation algorithm based on the offline training of data. While it gives an accurate estimation output, which is insensitive to noise, this method needs a preprocess of offline training. On the other hand, the capacitance can be estimated by the RLS method, of which application was described in detail in [9]. The RLS algorithm minimizes the least-square cost function iteratively, allowing for the estimated parameter of the system to be updated at each sampling interval whenever new data become available. The RLS estimation algorithm has the advantages of simple calculation and fast convergence performance [15]. However, it is not easy to determine a forgetting factor. Aside from this, the execution time may be long, depending on the window size for a high accuracy. In [9], where the input current injection rather than the dclink voltage injection was employed, the second-order bandpass filter was used to extract the dc-link current and voltage ripple components. Its transfer function is expressed as   2 KBS s2 + ωBS (23) HBS (s) = 2 2 s + (ωBS /QBS )s + ωBS where KBSF is the gain, QBSF is the quality factor, fBSF is the cutoff frequency, and ωBSF = 2πfBSF . In this paper, KBSF = 1, QBSF = 2, and fBSF = 30 Hz.

TABLE II SYSTEM PARAMETERS

ˆ can The RLS update of the capacitance to be estimated C[n] be written as   2 ˆ + 1] = C[n] ˆ + μ[n]BPF 1 dvdc [n] C[n 2 dt 

  2 1 dvdc ˆ × BPF[Pin − Pout ][n]− C[n]BPF [n] 2 dt (24) where μ[n] is an adjustment gain and is selected as a constant (9.5 × 10−13 ) by a trial-and-error method. The initial value of ˆ can be set as either the estimated capacitance from the last C[0] capacitor diagnosis or the nominal value of the capacitor bank. VI. E XPERIMENTAL R ESULTS AND D ISCUSSION To demonstrate the performance of the capacitance estimator, the experiment was carried out. Fig. 6 shows the hardware configuration of the experimental system. The converter parameters are listed in Table II. A high-performance DSP chip TMS320VC33 was used as a main controller, which operates at a 33.3-MHz clock frequency and is capable of 32-b floatingpoint operation. The sampling rate of the current control loop is double the PWM frequency, i.e., the sampling period is 100 μs. The calculation time of the SVR estimation algorithm is less than 1 μs. The space-vector modulation with symmetrical switching patterns was employed as a PWM strategy. Fig. 7(a) shows the dc-link voltage with its reference of ∗ = 340 + 10 sin(2π · 30t)[V ], where the dc-link voltage is νdc

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Fig. 10. Capacitance estimation at an abrupt variation of C. (a) Estimated 2 /dt]. capacitance. (b) BPF[pcap ]. (c) BPF[0.5dνdc

Fig. 7. (a) DC-link voltage, (b) q-axis current, and (c) d-axis current of the line-side converter.

Fig. 11.

Capacitance estimation at an abrupt variation of C using RLS. TABLE III CAPACITANCE ESTIMATION ERRORS

Fig. 8. Capacitor power. (a) [pcap ]. (b) BPF[pcap ].

Fig. 12.

Fig. 9.

Harmonic spectrum corresponding to Fig. 8. (a) [pcap ]. (b) BPF[pcap ].

well controlled. The control performance of the d- and q-axes currents is shown in Fig. 7(b) and (c), which is also satisfactory. Fig. 8 shows the capacitor power, where Fig. 8(a) is the measured waveform and Fig. 8(b) is the bandpass-filtered one. The corresponding harmonic spectra without and with filtering are shown in Fig. 9(a) and (b), respectively. It is seen that frequency components other than 30 Hz are completely eliminated after filtering through the BPF.

Capacitance variation versus electrolyte temperature [16].

Fig. 10(a) shows the estimated capacitance during the transition to case E from case D in Table I. In case D, the estimated capacitance is 2397 μF, which has only a +0.14% error compared with the measured value in Table I. Moreover, the estimation speed is shown to be fast for an abrupt change of the capacitance. Fig. 10(b) and (c) shows the variation of the filtered capacitor power and the filtered derivative term of the squared dc-link voltage. It coincides with (2) that the capacitance is reduced because BPF[pcap ] is decreased while 2 /dt] is kept constant. BPF[0.5dνdc

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ABO-KHALIL AND LEE: DC-LINK CAPACITANCE ESTIMATION IN AC/DC/AC PWM CONVERTERS

Fig. 11 shows the capacitance variation in a similar case to Fig. 10(a) with the RLS method. The transient performance is also as fast as in the SVR method. Table III shows a comparison of the estimated and measured data for the different capacitances of the dc-link capacitor bank. The estimation errors are less than 0.15% with the SVR method and 0.4% with the RLS method. Fig. 12 shows the capacitance variation based on the electrolyte temperature [16]. The estimated capacitance value needs to be modified considering the temperature effect if it is to be used for better predicting the deterioration of the capacitor. VII. C ONCLUSION This paper has proposed a novel method for capacitance estimation of the electrolytic capacitor for the three-phase ac/dc/ac PWM converter system, based on SVR. Only the ac component of the capacitor power due to the injected ac voltage in the dc link is required to find the identification model from the offline training. With this model, the capacitance can be calculated in real time with the input data of the capacitor power. From this paper, some remarks can be stated, as follows. 1) The voltage injection method is simpler than the current injection since the former requires only the capacitor power, without information of the dc-link current. 2) Online capacitance estimation is possible without the disconnection of the capacitor from the circuits. 3) It gives a high estimation accuracy and a fast estimation speed. 4) The deterioration level of the capacitor can be predicted with the proposed algorithm.

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[7] M. L. Gasperi, “Life prediction modeling of bus capacitors in AC variablefrequency drives,” IEEE Trans. Ind. Appl., vol. 41, no. 6, pp. 1430–1435, Nov./Dec. 2005. [8] V. A. Sankaran, F. L. Rees, and C. S. Avant, “Electrolytic capacitor life testing and prediction,” in Conf. Rec. IEEE IAS Annu. Meeting, Oct. 1997, vol. 2, pp. 1058–1065. [9] D.-C. Lee, K.-J. Lee, J.-K. Seok, and J.-W. Choi, “Online capacitance estimation of DC-link electrolytic capacitors for three-phase AC/DC/AC PWM converters using recursive least squares method,” Proc. Inst. Elect. Eng.—Electr. Power Appl., vol. 152, no. 6, pp. 1503–1508, Nov. 2005. [10] Y. Li and H. Yu, “Three-phase induction motor operation trend prediction using support vector regression for condition-based maintenance,” in Proc. WCICA, Jun. 2006, vol. 2, pp. 7878–7881. [11] A. J. Smola and B. Schölkopf, “A tutorial on support vector regression,” Stat. Comput., vol. 14, no. 3, pp. 199–222, Aug. 2004. [12] K. R. Muller, A. Smola, G. Ratsch, B. Scholkopf, J. Kohlmorgen, and V. Vapnik, “Predicting time series with support vector machines,” in Proc. ICANN. New York: Springer-Verlag, 1997, vol. 1327, pp. 999–1004. [13] V. Cherkassky and F. Mulier, Learning From Data Concepts, Theory, and Methods. Hoboken, NJ: Wiley, 1998. [14] V. N. Vapnik, “An overview of statistical learning theory,” IEEE Trans. Neural Netw., vol. 10, no. 5, pp. 988–999, Sep. 1999. [15] S. Haykin and B. Widrow, Least-Mean-Square Adaptive Filters. Hoboken, NJ: Wiley, 2003. [16] A. Fraioli, “Recent advances in the solid-state electrolytic capacitor,” IRE Trans. Compon. Parts, vol. 5, no. 2, pp. 72–75, Jun. 1958.

Ahmed G. Abo-Khalil (S’06) was born in Egypt in 1969. He received the B.S. and M.S. degrees in electrical engineering from Assiut University, Assiut, Egypt, in 1992 and 1996, respectively, and the Ph.D. degree in electrical engineering from Yeungnam University, Gyeongbuk, Korea, in 2007. Since 2007, he has been with the Department of Electrical Engineering, Assiut University. His research interests are power electronics, energy conversion, power quality, and control.

R EFERENCES [1] P. Venet, F. Perisse, M. H. El-Husseini, and G. Rojat, “Realization of a smart electrolytic capacitor circuit,” IEEE Ind. Appl. Mag., vol. 8, no. 1, pp. 16–20, Jan./Feb. 2002. [2] S. G. Parler, Jr., “Improved Spice models of aluminum electrolytic capacitors for inverter applications,” IEEE Trans. Ind. Appl., vol. 39, no. 4, pp. 929–935, Jul./Aug. 2003. [3] M. Shoyama, F. Deriha, and T. Ninomiya, “Steady-state characteristics of resonance switched capacitor converters,” JPE KIPE, vol. 5, no. 3, pp. 206–211, Jul. 2005. [4] F. D. Kieferndorf, M. Forster, and T. A. Lipo, “Reduction of DC-bus capacitor ripple current with PAM/PWM converter,” IEEE Trans. Ind. Appl., vol. 40, no. 2, pp. 607–614, Mar./Apr. 2004. [5] E. Aeloiza, J.-H. Kim, P. Enjeti, and P. Ruminot, “A real time method to estimate electrolytic capacitor condition in PWM adjustable speed drives and uninterruptible power supplies,” in Proc. IEEE PESC, 2005, pp. 2867–2872. [6] K. Harada, A. Katuski, and M. Fujiwara, “Use of ESR for deterioration diagnosis of electrolytic capacitor,” IEEE Trans. Power Electron., vol. 8, no. 4, pp. 355–361, Oct. 1993.

Dong-Choon Lee (S’90–M’95) received the B.S., M.S., and Ph.D. degrees in electrical engineering from Seoul National University, Seoul, Korea, in 1985, 1987, and 1993, respectively. He was a Research Engineer with Daewoo Heavy Industry from 1987 to 1988. For one year, he was with the Research Institute of Science Engineering, Seoul National University, where he was a Postdoctoral Fellow. Since 1994, he has been a Faculty Member of the Department of Electrical Engineering, Yeungnam University, Gyeongbuk, Korea, where he is currently a Professor. As a Visiting Scholar, he was with the Power Quality Laboratory, Texas A&M University, College Station, in 1998; the Electrical Drive Center, University of Nottingham, Nottingham, U.K., in 2001; and the Wisconsin Electric Machines and Power Electronic Consortium, University of Wisconsin, Madison, in 2004. His research interests include ac machine drives, control of power converters, wind power generation systems, and power quality.

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