IET Power Electronics Research Article
DC-link voltage control strategy for reducing capacitance and total harmonic distortion in single-phase grid-connected photovoltaic inverters
ISSN 1755-4535 Received on 15th June 2014 Revised on 20th December 2014 Accepted on 16th January 2015 doi: 10.1049/iet-pel.2014.0453 www.ietdl.org
Yihua Hu 1, Yang Du 2 ✉, Weidong Xiao 3, Stephen Finney 1, Wenping Cao 4 1
Department of Electronic & Electrical Engineering, The University of Strathclyde, Glasgow, UK Department of Electronic and Electrical Engineering, Xi’an Jiaotong-Liverpool University, Suzhou, People’s Republic of China 3 Department of Electrical Engineering and Computer Science, Masdar Institute of Science and Technology, Abu Dhabi, United Arab Emirates 4 School of Electronics, Electrical Engineering and computer Science, Queen University, Belfast, UK ✉ E-mail:
[email protected] 2
Abstract: High-volume capacitance is required to buffer the power difference between the input and output ports in singlephase grid-connected photovoltaic inverters, which become an obstacle to high system efficiency and long device lifetime. Furthermore, total harmonic distortion becomes serious when the system runs into low power level. In this study, a comprehensive analysis is introduced for two-stage topology with the consideration of active power, DC-link (DCL) voltage, ripple and capacitance. This study proposed a comprehensive DCL voltage control strategy to minimise the DCL capacitance while maintaining a normal system operation. Furthermore, the proposed control strategy is flexible to be integrated with the pulse-skipping control that significantly improves the power quality at light power conditions. Since the proposed control strategy needs to vary DCL voltage, an active protection scheme is also introduced to prevent any voltage violation across the DCL. The proposed control strategy is evaluated by both simulation and experiments, whose results confirm the system effectiveness.
1
Introduction
Single-phase utility-interactive photovoltaic (PV) systems are mainly for low-power residential applications, which can be classified into two categories: single-stage and two-stage in terms of their number of power stages [1]. A typical single-stage system is shown in Fig. 1a, of which the inverter is controlled to achieve maximum power point tracking (MPPT) and other grid-tied functions. Fig. 1b illustrates a two-stage interfacing topology involving a DC-link (DCL). The high capacitance of the DCL decouples dynamic interaction of the DC/DC and DC/AC converters. Therefore the control of the DC/DC converter is mainly for maximum power injection. The second-stage regulates the DCL voltage and performs the functions of power quality assurance, monitoring and protection to meet the grid requirement. The single-stage PV system generally shows the advantage of high conversion efficiency [1, 2]. However, the topology requires a significant value of capacitance to connect across the PV array terminals for module integrated converters, resulting in slow MPPT dynamics and low life expectancy [3]. A recent study promotes the use of two-stage or multi-stage systems with a DCL, which are flexible to control the power generation, size the capacitance and mitigate the harmonic injection to grids [3–5]. In single-phase PV applications, DC–AC converter requires a significant energy buffer to produce the AC output waveform from a DC source [6]. Aluminium electrolytic capacitors are widely employed for managing the power difference between the input and output ports in the single-phase grid-connected PV inverter (SPGCPVI) applications, which are featured with a high capacitance per unit volume. However, they are costly and susceptible to temperature degradation, which have become an obstacle to high system efficiency and long device lifetime [7–9]. Therefore it would be advantageous to minimise the capacitance value and replace the electrolytic capacitors with long-life capacitors, such as film capacitors [10].
There are several approaches to minimise such a capacitance. A modified modulation technique is introduced to reduce the DCL capacitance but maintain high-quality output voltage profile [6]. In [11], an adaptive droop-based controller is developed to minimise the DCL capacitor. One is to introduce power interfaces between the capacitor bank and DCL. A synchronous buck converter [12, 13] or an H-bridge [14, 15] can be used as the power interface for the capacitor bank. Alternatively, a switch can be added between the capacitor bank and DCL to adjust a high voltage and voltage ripples across its terminals [16]. A pseudo-DCL topology is proposed in [7] for PV micro-inverter applications. Another effective method is connect a H-bridge voltage source converter between the DCL capacitor and the second-stage inverter [17]. However, extra circuitry and control arrangements [18] are required to generate a counteracting voltage to compensate the double-line frequency ripple. The circuitry increases the system complexity and cost. An issue of SPGCPVI arises at light load conditions when the PV systems have low power quality and efficiency [19]. Typically, a pulse-skipping control strategy is introduced to improve the efficiency and power quality under these conditions. When the grid power injection stops, the PV energy is accumulated at the DCL capacitor to increase the voltage. When this voltage rises to a certain threshold, the energy is discharged through the grid current injection. This method improves the conversion efficiency and reduces the total harmonic distortion (THD). It also gives rise to voltage fluctuation across the DCL capacitor [20], which may cause a voltage violation issue. The proposed control strategy with active voltage protection can prevent voltage violation under pulse-skipping control. Power generated by the PV panels can vary dramatically in very short period of time [21] caused by scenarios such as fast moving clouds. However, the inverter output current adjusts only once per line cycle to ensure power quality [22]. Therefore a significant power mismatch between the two stages can occur to alter the
IET Power Electron., 2015, Vol. 8, Iss. 8, pp. 1386–1393
1386
& The Institution of Engineering and Technology 2015
Fig. 1 Classification of SPGCPVIs a Single b Two stages
DCL voltage, which requires a large DCL capacitance. The proposed variable DCL voltage control scheme can provide larger buffer for the unexpected power variation. Therefore the required DCL capacitance can be reduced. This paper proposes a variable DCL voltage control strategy integrated with a pulse-skipping control scheme. The DCL voltage is regulated as per the PV power, which varies with the solar irradiance and PV cell temperature. An active over-voltage protection scheme is also developed to prevent the inverter from significant solar irradiation variations. The proposed method does not need any extra circuitry and can be implemented by digital controllers. This paper is organised as follows. Section 2 analyses the DCL voltage variation in SPGCPVI systems. The proposed variable DCL voltage control strategy is introduced in Section 3. The active over-voltage protection and the integration of pulse-skipping control are provided in Section 4. Section 5 demonstrates simulation and experimental results to verify the validity of the proposed method, followed by a short conclusion in Section 6.
Fig. 2 Waveforms of output power and DCL voltage within one line period a PV power and output power b DC-link voltage c Grid voltage
Thus, sizing the DCL capacitance can be determined by the active power, the line frequency, the DCL voltage and the amplitude of the voltage ripple [4, 23] CDC =
2
DCL voltage variation
2.2 DCL voltage ripple
The AC power is composed of two components: DC and double-line-frequency AC. The DCL capacitance CDC provides an energy buffer to manage the power form difference. The double-line-frequency oscillation of the output power appears on the DCL voltage. Fig. 2 presents the output power and DCL voltage in one line period. When the instant power of PAC is higher than PPV, CDC is discharged to compensate the power deficit, as shown in Fig. 2a. When PAC is lower than PPV, the capacitor stores the extra energy generated by the PV generator. The charge/discharge operation results in variation of DCL voltage with the same double-line frequency, as shown in Fig. 2b. Therefore the DCL voltage can be decoupled into two parts [22], namely DCL voltage ripple Vrip and average DCL voltage VDC. As the reference signal, the line voltage waveform is provided in Fig. 2c. When power loss is not considered, the energy balance through the capacitor-based DCL can be expressed as 1 C (V 2 2 DC rip
2 H − Vrip L ) =
3p/4vf p/4vf
[PAC (t) − PPV ] dt
(1)
where Vrip H and Vrip L are the upper and lower boundaries of the voltage ripple. The amplitude of the double-line-frequency voltage ripple can be calculated by 1 C (V 2 2 DC rip
H
(3)
where
In a two-stage single-phase inverter, the inherent DC power on the generator side is transferred to the AC grid side via the power interface. A capacitor is used to balance the power difference between the input and output, a double-line frequency voltage ripple appears across DCL. 2.1
PPV vf VDC 2Vrip
2 − Vrip L) =
PPV vf
IET Power Electron., 2015, Vol. 8, Iss. 8, pp. 1386–1393 & The Institution of Engineering and Technology 2015
(2)
Vrip = (Vrip
H
− Vrip L )/2
(4)
VDC = (Vrip
H
+ Vrip L )/2
(5)
DCL voltage fluctuations
The DCL voltage variations include DCL voltage ripples and DCL voltage fluctuations [8], as illustrated in Fig. 3a. The voltage fluctuation ΔVflu results from the power mismatch between the input port and output port of SPGCPVI, which is introduced by the variation of solar irradiance. As the MPPT controls the PV power output from one state to another, in order to regulate DCL voltage, the output AC current will be adjusted accordingly. The control of DC/DC converter should have a high bandwidth; hence, the input power is adjusting almost simultaneously with the solar irradiation variation. The output current of the PV inverter is adjusted accordingly to the input and output power balances. The current reference of the DC/ AC inverter is commonly adjusted once per line cycle, which is much slower than the first stage. Increasing the reference adjust rate can cause unacceptable low-order harmonics in the output current. The power difference charges/discharges the capacitor before the power is re-balanced, and a voltage change ΔVflu is made to the DCL. The power mismatch within one line period Tac is considered to be the value of ΔP. The following equation can be obtained 1 2 ] Tac DP = CDC [(VDC + DVflu )2 − VDC 2
(6)
For a certain ΔVflu, the capacitance can be calculated by the following equation CDC ≥
2Tac DP (2VDC + DVflu )DVflu
(7)
1387
Fig. 4 Input power variation under the conventional instantaneous power control method
3.1
Fig. 3 Bus energy decoupling a DCL voltage ripple and fluctuation b Bus energy varying with bus capacitor and bus voltage
Equation (7) indicates the capacitor’s low limit value for dealing with the power mismatch problem. The simulation result has been used to illustrate the impact of the bust voltage variation on the energy storage, as shown in Fig. 3b, where E represents the bus capacitor storage energy. It is clear that the higher the bus voltage indicates the higher energy storage at the DCL. Therefore the variation of bus voltage keeps the same buffering performance but reduce the required capacitance of the DCL. 2.3
Voltage violation of the DCL
In nature, the capacitance of a capacitor reduces as it ages [24] and this may cause another power mismatch problem. The voltage violation results from the DCL voltage ripple and fluctuation, which are discussed as follows. Fig. 4 demonstrates a simulated case of a SPGCPVI with undersized DCL capacitance (CDC = 300 μF). The DCL voltage is specified as 374 V with a physical voltage limit of 450 V for the components. The over-voltage fault in the DCL is simulated by a DC power step from 80 to 500 W at 0.4 s, as shown in Fig. 4. Clearly, the capacitance is not great enough to buffer the suddenly increased energy. The over-voltage fault occurs when the DCL voltage exceeds 450 V. It took two line cycles for the DCL voltage to return within the normal operating range. In this paper, a novel DCL voltage control strategy is proposed to tackle this problem without over-sizing DCL capacitor.
3
DCL voltage reference
This paper proposes a variable DCL voltage control strategy, which is adaptive to the change of PV power levels. The control diagram is shown in Fig. 5a, where the DCL voltage is determined by the power level, PPV. The function of the bus controller is to decide the proper reference for the DCL voltage regulation. For example, the highest DCL voltage reference results from the highest PV generation. Meanwhile, the DCL voltage reference is set to be low when the PV system is affected by low solar irradiance. This provides a safety margin to avoid the DCL voltage violation, which has been demonstrated in Section 2.3. Moreover, it can be seen from (3) that a higher DCL voltage is required to limit the DCL voltage ripple amplitude in the case of a high power output. To illustrate the proposed control strategy, a three-level variable DCL voltage reference is designed and illustrated in (11)
Vref
⎧ ⎨ Vref H , = Vref M , ⎩ Vref L ,
[70%Prate ≤ PPV ≤ 100%Prate ] [40%Prate ≤ PPV ≤ 70%Prate ] [10%Prate ≤ PPV ≤ 40%Prate ]
(8)
where Prate refers to the rated power of the SPGCPVI. There are three operation states: high power (70–100%), medium power (40–70%)
Variable DCL voltage control
The grid injection of active power can be represented by the grid current since the grid voltage is assumedly steady at the point of common coupling. The variation of the DCL voltage determines the power balance between the solar power generation and grid current injection. In conventional SPGCPVI systems, the DCL voltage is controlled to follow a fixed reference, which allows the grid current injection to follow the PV power generation.
Fig. 5 Proposed control scheme and designed voltage references a Block diagram b Designed voltage reference
IET Power Electron., 2015, Vol. 8, Iss. 8, pp. 1386–1393
1388
& The Institution of Engineering and Technology 2015
and low power (10–40%). When the input power is lower than 10% of the rated power, the operational status is considered to be a light load, where the pulse-skipping control strategy is automatically activated. 3.2
DCL capacitor and boundary voltage
Fig. 5b illustrates the DCL voltage set points and related voltage boundaries. Vmax and Vmin represent the highest and lowest voltages for the SPGCPVI. To avoid over-modulation conditions, the bus voltage should be higher than the line voltage Vgrid. Given the voltage drop on the inductor and switching devices, a 10% voltage drop is considered. The lower limit can be found by Vmin = Vgrid (1 + 10%)
(9)
between 374 and 401.3 V. For the same amount of power variation, the required minimum capacitance is 567 μF. It can be seen from this case study that the variable DCL voltage control strategy can reduce the DCL capacitance by as much as 48%. When the PV generation is low, the relative low DCL voltage reduces the switch losses, and provides the voltage buffer for the potential power increase. 3.4
As shown in Fig. 5b, the medium voltage level can be designed by the electron transition process. As the DCL receives equal amount of energy, the voltage move up to a higher level, according to (1), the Vref M can be calculated as 2 Vref
According to the physical voltage constraints of the inverter a 10% of redundancy should be considered. The upper limit voltage Vmax can be calculated as Vmax = Vlimit (1 − 10%)
Vref Vref
H L
= Vmax − Vrip = Vmin − Vrip
the DCL capacitance can be sized according to Prate, Vref CDC =
CDC =
(11)
H
Prate vf Vref H 2Vrip
To extract the maximum amount SPGCPVI has a very high control mismatch in (7) during one line allowable fluctuation voltage range Substitute the parameters into (7)
2 Vref
and Vrip
(13) L
Solving (11)–(13) for a 50 Hz line frequency, the ripple voltage can be expressed as Vrip = 0.5398Vmax + 0.0398Vmin 2 2 + 108.5V + 0.0199 635Vmax max Vmin + 104.5Vmin 3.3
2 − Vref
Vref
M
(14)
Case study of capacitance minimisation
2 2 M = Vref M − Vref 2 2 Vref H + Vref L = 2
(16)
L
(17)
Following the case parameters and (17), Vref M is calculated as 416 V. Depending on the power change direction, the DCL controller will adjust the voltage reference from either high to low or low to high. Selecting the middle point allows a smooth transition for the set point and system status. Multiple levels can also be defined to achieve a smoother transition. To differentiate the energy distribution equally among each voltage level, the multiple voltage set points can be assigned by 2 Vref
(12)
of power, the first stage of bandwidth. ΔP is the power cycle (Tac). The maximum is between Vref H and Vref L .
2Tac DP 2 H − Vref
H
(10)
The bus voltage reference lies between Vmin and Vmax. Owing to the ripple effect, a safety margin should be introduced as
Variable voltage references
3.5
H
2 − Vref
M1
2 = Vref
M1
2 − Vref
M2
···
(18)
Active voltage protection
The variation scheme of the DCL voltage is designed to minimise the DCL capacitance and to reduce the risk of over-/under-voltage violation. A specific protection strategy is introduced in this section to further prevent any over-voltage risk that is caused by extreme variation of PV power. To maximum power harvest of solar energy, the trend of MPPT in two-stage conversion topology shows a higher bandwidth than the line frequency. In one line cycle, the input power can be updated several times in response to the action of MPPT and varying solar irradiance. Fig. 6 illustrates an example that the power extraction from DC/AC lags behind the power variation by four cycles. The symbol ‘T’ represents the time period of the AC line frequency. The power extraction can only be updated in every T period. The power difference from the instant active power is marked by the shadow part. The proposed scheme is to deviate the operating point from the maximum power point when the VDC is higher than the predefined upper bound Vmax. The control of DC/DC stage will be switched to VDC regulation or simply turning off the DC power injection.
Take a typical SPGCPVI as an example, the voltage limit and the grid peak voltage are 450 and 311 V, respectively. On the basis of (9) and (10), Vmax is 405 V and Vmin is 342 V. Following (14), Vref H is calculated as 400.9 V and Vref L is 346.1 V, and Vrip is 4.11 V. For the rated power of 500 W, the required minimum capacitance can be calculated as 293 μF from calculations. This is a conservative design which can handle the instant power change from 0 to 60% of the full load condition, which ΔP = 0.6Prate. For the same boundary voltage, the conventional method which typically applies a fixed voltage reference at the middle of the voltage boundary, which is VDC = 374 V. Under the power variation, the voltage can only fluctuate from the fixed voltage 374 V to Vmax − Vrip. Similarly, the equation can be written as 2 + 104.5V 2 Vrip = 0.519Vmax + 0.019 631Vmax DC
(15)
Hence, the ripple voltage is 3.7 V, the DCL voltage can fluctuate
Fig. 6 Power difference between input power from PV module and averaged output power
IET Power Electron., 2015, Vol. 8, Iss. 8, pp. 1386–1393
& The Institution of Engineering and Technology 2015
1389
Table 3 Specifications of experiment setup Components and parameters
Value
Part number
rated power for DC/DC converter rated power for DC/AC inverter bus capacitor
500 W 600 W 100 μF × 3 600 V
TMDSHVMPPTKIT TMDSHV1PHINVKIT EKXG401ELL101MMN3S
2.5 mH 20 kHz N/A
N/A N/A TMS320F28035
insulated gate bipolar transistor voltage limit each AC filter inductance, L switching frequency microcontroller
Fig. 7 DCL voltage and grid current waveform for the pulse-skipping control
Table 1 Specifications of simulation converters Component
Value
rated power bus capacitor physical voltage limit switching frequency AC filter inductance, L line frequency line voltage
500 W 300 μF 450 V 20 kHz 20 mH 50 Hz 220 V
3.6
IRG4PC30FDPBF
Pulse-skipping control
Under a low illumination condition, the output current from the PV inverter is low, which results in a low system efficiency and high distortion of the grid-injected current [25]. When the THD is higher than the grid code, the grid-tied function should be disabled; therefore the available solar energy is compromised. Together with the proposed DCL voltage variation scheme, the pulse-skipping control can be employed to capture solar energy
Fig. 8 Simulation results of the conventional control method with 700 μF bus capacitor
Table 2 Specifications of the control parameter Designed parameters Vmax/Vmin Vref H /Vref section 1 section 2 section 3
M /Vref L
Value 405 V/342 V 401 V/374 V/346 V 50–200 W 200–350 W 350–500 W
Fig. 9 Simulation results of the proposed control method at an input energy transient
When the VDC is lower than Vref H , the DC/DC stage is back to the MPPT operation.
a Case 1 b Case 2
IET Power Electron., 2015, Vol. 8, Iss. 8, pp. 1386–1393
1390
& The Institution of Engineering and Technology 2015
Fig. 10 Simulation results of pulse-skipping control and active voltage protection a Without skip control b With skip control c Sudden power step up d With active voltage protection
during a low power condition. This allows the SPGCPVI to deliver the maximum available solar power but reduces the power loss resulted from switching operations. When the input power reaches a lower threshold (e.g. the predefined 10% of the rated power), the control algorithm of the DC/AC inverter will switch to the pulse-skipping mode. The grid power injection is turned off by switching the current reference |Iref| to zero when the DCL voltage drops below the pre-designed value of Vref L .This allows the input energy from PV module to charge the DCL capacitor. When VDC reaches the upper limit of the voltage reference, Vref H , the energy is discharged by the resumption of AC current injection. This maintains relatively high amplitude of the injected AC current because of the reduction of injection cycles. The potential violation of DCL voltage is avoided by the proposed scheme and the protection strategy. Fig. 7 illustrates the operation of the pulse-skipping control based on the pre-determined voltage limits calculated in Section 3. However, during the capacitor charging time tcharge, the DCL voltage keeps increasing. There is a chance that the solar irradiation resumed to a high level. As shown in Fig. 7, the voltage is approaching to the maximum value, and there is little
IET Power Electron., 2015, Vol. 8, Iss. 8, pp. 1386–1393 & The Institution of Engineering and Technology 2015
room for further increase. As a result, an over-voltage fault will occur if no action is taken. Fortunately, with an active over-voltage protection scheme, DCL voltage is controlled to be in the safe operation range so that the inverter safety can be guaranteed.
4
Simulation and experiment
A two-stage grid-connected PV inverter with the proposed control strategy is simulated by using PSim software. The system parameters are shown in Table 1. Fig. 8 is the simulation results of conventional DCL control scheme with 700 μF bus capacitor. In the progress of input power transient, the bus voltage ripple is increased and 10 V voltage deviation in input transient progress. Compared with Fig. 4, the over-voltage phenomena are limited by increasing bus capacitor. 4.1
Variable DCL voltage
Fig. 9 presents the simulation results of the proposed DCL voltage control strategy with input power step changes. Three operating
1391
sections and corresponding reference voltages are shown in Table 2. The same capacitor (300 μF) as in Fig. 4 is used to illustrate the effectiveness of the proposed control method. It can be seen from Fig. 9(a), the DCL voltage varies according to the input power level. Given the DC power step from 80 to 500 W, the bus voltage varies from Vref L to Vref H .With the proposed multi-bus reference control method, the maximum voltage of the bus capacitor is
