Low Noise Front-End Amplifier Dedicated to Monitor Very Low Amplitude Signal from Implantable Sensors Yamu Hu , M. Sawan École Polytechnique de Montréal, Department of Electrical and Computer Engineering P.O.Box 6079, Station "Centre-Ville", Montreal (QC), Canada H3C 3A7 Email: huyamu |
[email protected]
Abstract This paper describes a low-noise, low-power and lowvoltage analog front-end amplifier integrated in implantable electronic devices and dedicated to very low amplitude signal acquisition. Low noise and low DC offset are obtained by means of Chopper Stabilization (CHS) technique. In addition, due to adding a rail to rail input stage, low power supply (1.8V) and wide common mode input range (0-1.8V) are achieved also. It features a gain of 51dB and a bandwidth of 4.5 kHz. The equivalent input noise is about 56nv/ Hz .
I. Introduction A large number of applications require an ultra lowamplitude signal measurement module, such as implantable sensors in biomedical applications intended to monitor several neuromuscular activities. Among these devices, bladder controller that allows to measure volume of the urine and adjust stimulation parameters when necessary, is an important rehabilitation application, as shown in figure 1 [1]. Its analog front-end interface, Volume-Monitoring Device (VMD) is used to sense the nerve signal that contains the volume information of the bladder.
instrumentation amplifier (IA) which amplifies the signal with a programmable gain and rejects the common mode signal. For electronic implantable system applications, the dominant noise source is often the 1/f noise component of the differential input stage. The use of increased processing steps and reduced gate dimensions associated with scaling generally leads to increase the 1/f noise level. CHopper Stabilization (CHS) technique is well-known for reducing the 1/f noise and DC offset. The low-noise amplifier circuit implementation based on chopper technique had been reported in [2]. However the circuits discussed in previous papers all worked under at least 4V supply voltage and the signal bandwidth was limited in few hundred Hz. As in the implantable system applications, the main energy is transmitted from outside the body through the skin, thus the supply voltage and power consumption of system should be minimised. In addition, the bandwidth of nerve signal can be up to 10 kHz, the signal bandwidth of the analog frontend in the VMD should be improved also. In this paper, we present a complete analog front-end system which works well under single 1.8V supply voltage and realizes a wide common mode input range by using a rail-to-rail low noise amplifer. And since the implantable system should be fully integrated, the modulating clock signal is generated on-chip by a voltage controlled oscillator. The organization of the paper is as follows: Section II describes the proposed low-voltage low-noise CHS amplifier circuit. The measurement results of the prototype chip and conclusion are given in sections III and IV respectively.
Bladder
II. Circuit Implementation 1. Block diagram
Figure 1. Block diagram of the global system dedicated to bladder control Nerve signal Vn, of which the amplitude is very low and generally ranged from 1 to 10 mV, will be submerged in noise of the conventional CMOS two stages topology Opamp. Hence, it needs to be first weakly amplified by a Low Noise Amplifier (LNA) to overcome 1/f noise and to rise the needed signal above the noise level of the following
The block scheme of the system is shown in figure 2. The selective amplifier is composed of two stages, a rail-torail low-noise preamplifier and a bandpass filter. There are two advantages of this structure: first, a wide common mode input range can be achieved by the rail to rail amplifier, without impairing the linearity of Gm-C filter. Second, the input transconductance value in BPF does not need to be very high to realize a high DC gain, thus it is not necessary to compensate the offset which comes from high transconductance value of input pairs.
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Chopper stabilization amplifier
Matching Oscillator
that little gain and phase distortion will be introduced to the system.
Bias circuit
A. Rail to Rail OTA The rail-to-rail input stage is realized by placing two N- and P-type differential pairs in parallel. Constant gm is fchop fchop obtained by means of two maximum current select (MCS) Rail to rail 2nd order Demodula Lowpass Instrumentation circuits, which are made of transistors from MP09 to MP20 Vin Modulator Vout Preamplifier Gm-C BP filter tor Filter Amplifier in figure 4. The MCS circuit compares two input currents , eg. in1 and ip2, that come from N-pair and P-pair input stage Figure 2. Block diagram of analog front-end system (not given out in figure 4) respectively, and output the larger one. This is feasible because the two different input currents will lead to either current source (MP09 , MP10) or 2. Rail-to-rail Modulator current sink (MN11, MN12) lost their saturation region, and The input modulator can be realized by simple passive not act as a constant current source again. Thus as long as modulators which is composed of four cross-coupled the input pairs are tuned with an equal gm, the gm value of analog switches that are controlled by two non-overlap the OTA will be universal constant. Another advantage of clocks having frequency. In order to guarantee an the MCS circuit is that it outputs a stable DC operation adequately low switch resistance in a low voltage current no matter which region the input pairs locate on. environment, a bootstrapped switch that inspired from [3] This makes the common mode feedback (CMFB) circuit can be used. The switch is conceptually a single NMOS that is necessary for the full differential system working transistor, as shown in figure 3. well. During the off phase, f is high. The switch S3 bp! discharges the gate of M1 to ground. Meanwhile, VDD is applied across capacitor C by the switches S1 and S2. And the switches S4 and S5 isolate the transistor M1 from C cp! in1 in2 while it is charging. In the f phase, the switches S1, S2 and S3 are off while the switches S4, S5 are on. The VoVo+ capacitor C whose voltage has been charged to VDD on the previous phase behaviors as a battery across the source-gate of the transistor M1 during this phase. It turns on transistor ip1 M1 and enables gate of M1 to track the input voltage shifted ip2 cn! by VDD, keeping the gate-source voltage unchanged regardless of the input signal. The clock double circuit that bn! consists of two transistors M2 and M3 and capacitors C1 and C2 are added to operate the switches S1 to S5. Vctl
V-I Converter
MP09
MP10
MN13
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CMFB
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Figure 4. Maximum current select and summing circuit
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Figure 3. Bootstrapped switch 2. Low Noise Preamplifier The preamplifier consists of a rail-to-rail OTA followed by a transimpedance stage. As the power supply is only 1.8V, in order to improve signal dynamic range and common mode input range, a rail-to-rail input stage is used. The DC gain of the amplifier equals to Gm1/Gm2, where Gm1 and Gm2 are the transconductance value of the rail to rail OTA and the transimpedance stage respectively. The bandwidth of the amplifier should be high enough to ensure
B. Noise consideration System noise performance will mainly depend on the output noise of the preamplifier. It is determined by several critical transistors in the circuit, such as input pairs and current mirrors. To decrease their noise, two aspects should be considered. First it is necessary to enlarge their dimension both on width and length to decrease their 1/f noise. Only when the 1/f noise is decreased, the corner frequency that thermal noise equal 1/f noise can be as small as we expected , say arround 10k Hz. Second, since the output noise will be eventually determined by their thermal noise, it is needed to reduce the thermal noise by increasing their carrying DC current and transconductor value. 3. Bandpass filter & Matching Oscillator The second stage of the selective amplifier is built with a 2nd order Gm-C biquad filter to reduce the system residual offset that stems from charge injection of input
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modulator. Its block scheme is present in figure 5(a). Due to lack of virtual grounds and low impedance nodes, the gm-C filter are sensitive to parasitic capacitors. Therefore, we should add a automatic tuning circuit in the BP filter to lock its center frequence fc with fchop. The automatic tuning methods in continuous time filter have been discussed in many papers. But for the CHS amplifier, the deviation of fchop itself will not introduce significant impacts on the performance of CHS. The critical point of tuning in CHS is to make fc tracking with fchop, rather than fix it with a reference clock. Thus we can use an on-chip oscillator which uses the same resonator structure with the BPF as shown in figure 5 b). The tuning error will only come from mismatching rather than the parasitic parameters. This structure reduces the complexity of the whole system. It is especially important in this application whose modulator clock should be generated on-chip. The GNL (Non-linear Conductance) is used to guarantee oscillation and regulate amplitude[4]. +
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gm
gm1
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Figure 6. Die photo of the prototype chip
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gm4
gm
CMFB
to reduce the low frequency noise and DC offset in CMOS opamp. The low supply voltage and wide common mode input range are realized by using a rail to rail low noise preamplifier This amplifier was originally designed for biomedical applications, however it can be used for any low frequency applications to monitor ultra low amplitude signal.
CMFB
Vout
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R a il - t o - r a i l G m 30
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(b) Figure 5. a) Block scheme of 2nd BP filter scheme of matching Oscillator
The experimental chips have been fabricated in CMOS 0.35 mm technology. The layout is shown in figure 6. Its core area size is around 0.52 mm2. The measured gain of the rail-to-rail input amplifier is shown in figure 7. The variation of gain is smaller than 5%, better than the conventional rail-to-rail amplifiers. The DC gain of the low noise preamplifier equals to 26dB and the –3dB frequency is about 1.2 MHz, much larger than fchop (40 KHz in our case). The measured oscillator Chopper frequency (fchop) and center frequence (fc) are around 37 KHz. Quality factor Q is specified at 4, thus the signal bandwidth can be up to 4.5 KHz. The simulated input referred equivalent noise is 56nv/ Hz . The static power consumption of the total acquisition front-end is only 775mW. CONCLUSION
A fully integrated low-voltage analog front-end dedicated to implantable monitoring applications is presented. The chopper modulation technique was chosen
0
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0.6 0.8 1 1 .2 C o m m o n M o d e V o lta g e
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Figure 7. Measured gain of rail to rail OTA
b) Block
III. Simulation & Experimental Results
IV.
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Acknowledgement The authors would like to express their thanks to NSERC, Canadian Microelectronics Corporation (CMC), Micronet and Goal Semiconductor Inc. for their support during this project. REFERENCE [1]. M. Sawan, K. Arabi and B. Provost, "Implantable volume monitor and miniaturized stimulator dedicated to bladder control", Artificial Organs, Vol. 21, No. 3, 1997, pp. 219-222. [2]. C.C. ENZ, G. C. TEMES, “Circuit Techniques for Reducing the Effects of Op-Amp Imperfections: Autozeroing, Correlated Double Sampling, and Chopper Stabilization”, Proceedings of the IEEE. Vol. 84. pp. 1584-1614 November 1996 [3]. T.B. Cho, Paul R. Gray, "A 10b, 20 M sample/s, 35mW Pipeline A/D Converter", IEEE J. Solid-State Circuits,, vol. 30, pp. 166-172, March. 1995 [4]. F. Krumenacher, N.Joehl, "A 4-MHz CMOS Continuous-Time Filter with On-Chip Automatic Tuning", IEEE J. Solid-State Circuits,, vol. 23, pp. 750758, June.1988
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