Defect Engineering for Carrier Lifetime Control in High Voltage GaAs Power Diodes their spatial distribution in the power diode base layers greatly affect such critically important dynamic and static diode structure characteristics as turn-on and turn-off time via their direct interrelation with the carrier lifetime, switching energy loss, and static I-V characteristics.
V.A. Kozlov Semiconductor Research and Development Department FID Technology Ltd. & Power Semiconductors Ltd. Saint-Petersburg, Gzhatskaya 27, 195220, Russia
[email protected]
Electrically active defects are always related to the existence in the device crystal of a certain ensemble of its crystalline structure defects. To control the charge carrier lifetime in active operating layers of power semiconductor devices, introduction of certain point defects playing the role of recombination centers is usually used. Such point recombination centers are deep-level traps located in the semiconductor bandgap. Their parameters and properties in, e.g., silicon-based devices are well known and thus may be simulated quite accurately.
F.Yu. Soldatenkov, Centre of Nanoheterostructure Physics Ioffe Institute Saint-Petersburg, Polytekhnicheskaya 26, 194021, Russia Semiconductor Research and Development Department Power Semiconductors Ltd. Saint-Petersburg, Gzhatskaya 27, 195220, Russia
[email protected]
Techniques of controllably introducing linear defects (e.g., dislocations) into device crystals are used to control carrier lifetime much less. Semiconductor dislocations can also have intrinsic electrical activity and, along with point defects, can exhibit a quite high recombination activity. Studies of power device dislocations are the subject of many papers whose data are rather discrepant. Therefore, due to great diversity of properties of "dislocations - point defects" complexes depending on their introduction technique and environment in the semiconductor device crystal, the dislocation introduction techniques are used quite limitedly to control carrier lifetimes in fabricating power devices.
V.G. Danilchenko, V.I. Korolkov Centre of Nanoheterostructure Physics Ioffe Institute Saint-Petersburg, Polytekhnicheskaya 26, 194021, Russia
[email protected],
[email protected]
I.L. Shulpina Division of Physics of Dielectrics and Semiconductors Ioffe Institute Saint-Petersburg, Polytekhnicheskaya 26, 194021, Russia
[email protected]
At present, the techniques of introducing more complex (three-dimensional) crystal defects in producing state-of-theart power devices are barely used. Earlier the techniques of forming three-dimensional crystal defect complexes were used, for instance, to increase the carrier lifetime in semiconductors. This was achieved via gettering of uncontrolled and residual impurities-contaminants to the defect complexes which act as point defect sinks,.where neutralization of the point defect recombination activity took place. Since the three-dimensional crystal defect complexes in power device crystals cause most often the considerable reduction of the crystal electrophysical parameters uniformity, which affects the power device service life and reliability, these techniques were eliminated from practical use.
Abstract—The paper considers the physical basis for the technique of controllable defect formation at heterointerfaces and in the bulk of epitaxial GaAs layers in the process of isovalent doping. Results of studying crystal defects and their rearrangement depending on the isovalent doping modes in the process of epitaxial growth are presented. The main aspects of the defect influence on the charge carrier lifetime as well as on the diode structure blocking voltage are analyzed. Particular cases of the developed technique application for controllable defect formation in fabricating such GaAs-based devices as Hyper Fast Recovery Epitaxial Diodes and Drift Step Recovery Diodes are considered. Keywords— gallium arsenide, liquid phase epitaxy, crystal defects, charge carrier lifetime, isovalent doping, turn-off time, fast recovery epitaxial diode, rise time, step recovery diode.
I.
Thus, the methods for semiconductor defect control are not only the foundation of all the techniques for semiconductor device structure formation, but also determine their reliability and efficiency.
INTRODUCTION II.
The intentional defect introduction and defect control in a semiconductor crystal enable variation of its main electrical properties: conductivity type, majority carrier concentration and mobility, as well as minority carrier lifetime. This is just the way we interpret the concept of "Defect Engineering" in this paper. Electrically active deep-level crystal defects and
978-1-4799-3944-2/14/$31.00 ©2014 IEEE
SPECIFIC FEATURES OF CARRIER LIFETIME CONTROL METHODS IN GAAS POWER DEVICES
Note that the charge carrier lifetime effect on dynamic power device characteristics is qualitatively opposite to that on static characteristics. Therefore, in fabricating state-of-the-art power device structures, not only the mean value of this
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voltage GaAs p-n junctions able to block the voltage of Ub = 2000 V. In this work we used p-GaAs (111) substrates doped with zinc to (2-10) ·1018 cm-3. The epitaxial growth installation and boats were able to grow epilayers on 2" and 3" GaAs substrates. The structures were grown from limited In-Ga-As melt in the hydrogen atmosphere in quartz or graphite cassettes-boats at the crystallization onset temperature of 900 ºC with subsequent cooling to the room temperature.
parameter in the power diode base layers is controlled, but also special techniques for obtaining nonuniform spatial distributions of carrier lifetimes in device crystals are applied. The most common technique for creating such lifetime profiles is irradiating the device structures with protons or other energetic ions [1, 2]. This technique possesses a number of undoubtful advantages and is based on radiation-induced creation of point defects in local layers of semiconductor device structures almost on full completion of all the growth processes and post-growth operations necessary for the device fabrication. Sometimes, along with the radiation-induced defect formation technique for the lifetime control, methods of deep level impurity diffusion are used. These methods create crystal defects with pronounced recombination properties in the device [3]. However, they are considerably more complicated and less reproducible; therefore, these methods are not widely used in power device fabrication technology.
In this growth method, the electrically active defect content in the epilayer is controlled by the content of residual (background mainly) impurities in the melt and growth system, temperature and duration of the melt preannealing, hydrogen flow rate and humidity inside the reactor for epitaxial growth; it also depends on the epitaxial film crystallization mode with forced cooling of the system. When growing p-i-n structures by the LPE method, it is possible to obtain thick i-layers of weakly-doped GaAs or InGaAs with the free carrier concentration n of about 1013 cm-3 or lower; this allows getting Ub of up to 2000 Volt level. Typical depth profiles of the free charge carrier concentration in GaAs and InGaAs p-i-n structures fabricated via LPE process were presented in [4]. To correctly compare the results, we studied p-i-n structures with different isovalent doping levels but with almost the same base layer thickness (50 to 65 μm).
All the above-mentioned techniques for controlling the power device crystal defects also belong to the "Defect Engineering" technology and can be applied to correct the semiconductor power device characteristics. This technique is also applicable for GaAs diodes. However, in this paper it is not considered since the technique of proton modification and deep level impurity diffusion used to control carrier lifetime in GaAs power devices is much more complicated than that used for Si and Si-based devices. Development of this technique needs additional investigations and will be the subject of our studies in the near future.
IV.
MEASUREMENT PROCEDURES AND RESULTS
A. InAs distribution in the InxGa1–xAs epitaxial layers The InAs content in the InGaAs solid alloy epilayers was measured by using the X-ray spectral microanalysis in a “Camebax” setup. Fig. 1 presents the InAs distribution across an InxGa1–xAs layer in which elastic strains were partially relaxed. Note that earlier (in [4]) we determined the epilayer solid phase compositions by calculations based on the measurements for layers with low InAs content (x < 1.0 %). When the same calculations were performed for layers with high solid phase content, the effect of elastic strains caused by the layer/substrate lattice mismatch appeared to be estimated improperly. The calculation procedure [6] used in [4] was
This paper generalizes the main results of studying and developing the methods for controlling carrier lifetimes and distribution profiles only by using the technique for controlling intrinsic crystal defects arising in crystals in the process of heterostructure epitaxial growth. This technique is based on the method of GaAs isovalent doping designed to control lifetime of non-equilibrium charge carriers in diodes based on the GaAs–III-V heterostructures. This approach to the power diode carrier lifetime control was proposed and tested for the first time for the InGaAs-GaAs heterostructures in [4] and then expanded to other GaAs–III-V systems, e.g., to the GaAs-GaAsSb heterostructures [5]. In this paper we have shown that controllable creation of an ensemble of intrinsic recombination defects makes it possible to reduce the non-equilibrium carrier lifetime to units of nanoseconds without considerable degradation of I-Vcharacteristics. This is achieved through optimization of the lattice mismatch in heterostructures like GaAs-III-V and thickness of the solid III-V solution epilayer on the GaAs substrate The technique of defect control in forming heterojunctions in various parts of diode structure layers also allows to vary the distribution of minority carrier lifetime across the thickness of semiconductor structure layers, which is very useful in various practical applications.
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Epilayers of the InxGa1–xAs solid solution with the InAs content x of up to 5% were grown on GaAs substrates by liquid-phase epitaxy (LPE). LPE is the simplest, efficient and, perhaps, the only possible today's method for producing high-
Figure 1. InAs distribution x across the thickness of thick InxGa1–xAs layer.
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screen with a slot for transmitting the reflected beam was set between the sample and photosensitive element.
correct in the selected range of epilayers thickness only for compositions characterized by x < 1.5 mol. %. Later we revealed that during the growth of layers with high x, a partial relaxation of elastic strains takes place. This generates misfit dislocations (see below) while the solid alloy composition itself may be almost equilibrium. This was confirmed by Xray topography measurements on InxGa1–xAs samples with a layer composition that causes a partial removal of elastic strains and formation of a linear dislocation grid.
The layers of device structures with different isovalent doping levels exhibited dislocation structures of two types: a grid of rectilinear misfit dislocations (Fig. 3, a) and a grid of "cellular" dislocations (Fig. 3, b). The studies showed that the occurrence of a quasi uniform and symmetrical in the (111) plane misfit dislocation grid (see Fig. 3, a) is typical for InxGa1–xAs layers with the x range of 1.5 mol. % to 3 mol. % and the above-mentioned InxGa1–xAs layer thickness range of 50-65 μm. The dislocation density typical for such grids is about 150 cm-1. We assume that the occurrence and evolution of crystal defects of this type cause the lifetime reduction and gradual decrease in the InGaAs/GaAs diode heterostructure blocking voltages Ub (Fig. 4); this is caused by gradual increase of the dislocation grid density with increasing x.
B. Determination of minority carrier effective lifetime τeff The minority carrier effective lifetime (τeff) in the base areas of diodes was determined by measuring the transient response of a diode during disappearance of the charge accumulated in the base layers at the inversion of voltage applied to the diode (the so-called Lax method [8]), as well as by measuring the post-injection electromotive force voltage drop (the so-called Gossik method or Open Circuit Voltage Decay method [9]). Fig. 2 presents the τeff values obtained for structures with different InAs contents in the base areas. Fig. 2 shows that isovalent doping can significantly (up to 100 times) decrease the effective lifetime in the vicinity of the heterointerface of a such p-n diode structure as compared with p-n diodes based on GaAs homo-junction structures. Such a decrease in τeff is observed when the rated critical thickness of the plastic deformation onset hC is exceeded (the calculation was performed according to the procedure described in [7]). Accordingly, the recovery times of the diodes can also decrease with τeff from several hundred nanoseconds to several nanoseconds.
It was found that in InxGa1–xAs layers with even higher isovalent doping level x (i.e., in the case of more significant layer/substrate lattice mismatch), a "cellular" dislocation structure (Fig 3, b) with different cell sizes and dislocation boundary densities is formed instead of a linear grid of rectilinear dislocations. The typical dislocation density within the boundaries in the layers with "cellular" grids of this type varies from 106 to 107 cm-2 depending on the layer thickness and composition, while the cell size ranges from 100 to 50 μm. Optical microscopy studies of samples with a high doping level (x > 4 mol. %) revealed characteristic growth patterns
C. Studying the crystalline structure of the GaAs-III-V heterostructure layers The real crystalline structures of the GaAs-III-V heterostructure epilayers were studied by the back-reflection X-ray diffraction topography [10, 11]. For this purpose, the CuKα radiation and asymmetric reflections (422, 533, 331) at different information layer depths through scanning the sample and photosensitive detector were used. An opaque 1 mm а
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Figure 2. Effective lifetimes of nonequilibrium carriers in the vicinity of a p-n junction in InxGa1–xAs structures grown on GaAs substrates as a function of InAs content (τeff was measured by OCVD - method).
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A. Fast Recovery Eepitaxial Diodes (FRED) for Pulsed Power and High Friquency Applications Diodes of this type are very widely used in power electronics equipment such as PFC, UPS, High Friquency DCDC Converters and Power Suppliers etc. Static and switching losses of the FRED diodes should be extremely low; along with this, these diodes should exhibit relatively soft character of blocking capability recovery in switching from the conductive to blocking state. The GaAs-based FRED diodes have undoubtful advantages over silicon-based ones, mainly due to a higher mobility of charge carriers and large band gap. These GaAs material properties result in lower switching losses and higher power density of GaAs diodes vs. Si-chips [4, 5, 13].
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Usually, to raise the operational frequency, as well as to decrease the switching losses and switching time of FRED bipolar diodes, it is necessary to reduce the carrier lifetime in base layers of the devices without loss of blocking voltage capability and without noticeable increase in the forwardvoltage drop Uf. Numerous attempts have been made to decrease the switching time for high voltage power Si and GaAs diodes down to a nanosecond level (see, e.g., [13, 14, 15]). However, despite a certain success, the results reached in improving the switching speed for power diodes based on Si or GaAs “homojunction” structures fail to fully satisfy the upto-date power electronics needs. The minimal switching time of about 30-50 ns was demonstrated for diodes with blocking voltage Ub of about 400-600 V [13-16].
Figure 4. Breakdown voltage Ub of InxGa1–xAs/GaAs base heterojunction diodes versus InAs content (Ub was measured at leakage current Ir = 0.1 mA, S = 0.02 сm-2 and T = 25 oC).
combining, typically, several dislocation cells at once on the epitaxial layer surfaces. The growth patterns are well identifiable also in the X-ray topographs in reflections with small X-ray incident angle (reflections 331 as compared with reflections 422 or 533). Their presence evidences a high content of crystal defects in the InGaAs epitaxial film. We relate the drastic stepwise decrease of Ub in diode heterostructures with a high InAs content (Fig. 4, x > 3.5 mol. %) to a qualitative modification of the InxGa1–xAs layer dislocation structure, namely, to a qualitative transition from the uniform rectilinear dislocation grid with the (111) symmetry to the "cellular" dislocation structure with a very high dislocation density at the cellular grid boundaries and formation of growth patterns on the epilayers surface. Such a conclusion on the dense dislocation walls effect on the reduction of the p-n junction blocking capability fits well (both qualitatively and quantitatively) the results of studying dislocations in silicon epitaxial structures of power devices [12].
Using the results of our studies, we applied the isovalent doping technique to control the defect formation in fabricating FREDs based on InGaAs/GaAs heterostructures. The growth modes were selected in a way to ensure the carrier lifetime τeff in the vicinity of the diode p-n junction tp be about several nanoseconds. For comparison, Fig. 5 shows typical switching dynamics oscillograms for diodes from “Power Semiconductors Ltd.” with two different base layers: heterostructure GaAs-III-V diode (curve 1) and homostructure GaAs diode (curve 2).
Note that almost all the samples with x > 1 mol. % investigated by the X-ray topography exhibited residual bending of structures, which most probably was caused by an incomplete relaxation of elastic strains in dislocation generation. V. METHODS FOR CONTROLLING THE GROWTH DEFECT GENERATION IN FABRICATING POWER GAAS DIODES OF VARIOUS TYPES
1
The results of our investigations of regularities in growth defect generation in the process of growing GaAs-III-V heterostructures with different isovalent doping levels enabled us to use these methods to optimize the fabrication procedures for various power diodes. These approaches are partly described in our papers [4, 5]. In this paper we will not dwell on all the potential fields of these methods application in producing power electronics devices. Here we present only two characteristic cases concerning power GaAs diodes designed for electrical circuits requiring either fast and soft or step recovery of the power diode blocking capability.
2
Figure 5. Waveforms of 4 A current turn-off switching for GaAs-III-V heterojunction diode (blue curve 1, τrr = 8 ns) and GaAs homojunction diode (green curve 2, τrr = 60 ns) with identical emitter areas S = 0.02 сm-2 and Ub = 500 V (If = 4 A, dI/dt = -0.5 A/ns, Ur = 250 V, T = 25 oC). The time scale is 20 ns/div. The current scale is 1 A/div.
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2 1
Figure 6. Waveforms of 1A-current turn-off switching for a InGaAs/GaAs heterojunction diode (blue curve 1, Qrr = 0.65 nQ) and SiC Schottky diode CSD01060 from “Cree” (green curve 2, Qrr = 0.3 nQ) with identical current ratings and Ub = 600 V. The time scale is 10 ns/div. The current scale is 250mA/div.
Figure 7. Waveforms of voltage pulse recovery for two different chips of GaAs-III-V DSRD from one wafer with blocking voltage Ub = 450 V. The time scale is 200 ps/div. The voltage scale is 50 V/div.
DSRD based on GaAs-III-V heterostructures fabricated by using isovalent doping to control lifetime profile in the device layers have switching times of 70 to 200 ps for devices with Ub of 100 to 600 V, respectively [19, 20]. The switching time for GaAs–DSRD opening switches is much lower compared to SiDSRD switches with the same voltage rating [18, 19]. GaAs switching DSRD-diodes are able to work at switching frequencies of up to 50 MHz and in a wider current density range than silicon DSRD.
Comparative tests of such device structures showed that the technique for heterostructure growth with controlled defect formation using isovalent doping method ensures production of Hyper Fast Recovery Epitaxial Diodes with a record-low level of accumulated charge and turn-off time τrr, as well as a record-low turn-on and turn-off switching losses in the whole class of currently existing Si and GaAs bipolar diodes. With respect to the combination of their dynamic characteristics, these diodes are slightly worse than SiC-based Schottky diodes (Fig. 6). In addition, compared to SiC-based Schottky diodes, they can work at frequencies in a MHz level and crystal temperatures of up to 250 °C, with lower losses in significantly larger safe operation area.
VI.
CONCLUSION
As the main result of this study, the possibility of an effective carrier lifetime reduction down to the nanosecond level in power GaAs-III-V heterostructure diodes has been demonstrated without significant decrease in the device breakdown voltage. These results became possible due to the technique for controllable defect formation at the GaAs-III-V heterointerfaces and in epitaxial layers, which involves the GaAs isovalent doping.
Forward voltage drops Uf for InGaAs/GaAs diodes with Ub = 500 V and reverse recovery time τrr = (8-10) ns are about (2.0-2.1) V measured at the current density j = 150 A/cm2, If = 4 A, dI/dt = -0.5 A/ns, Ur = 250 V, T = 25 oC. The diode capacity C0 weakly depends on voltage. Its magnitudes are C0 ~ 18 pF/mm2 without bias and C200V ~ 3 pF/mm2 at Ur = 200V.
The obtained results were used to fabricate hyper fast GaAs–III-V pulsed power diodes with the blocking voltage Ub = 600 V and nanosecond switching time. Diodes were able to switch power of up to 10 kW with switching time τrr less than 10 ns (Fig. 1) at Uf < 2 V and current density of 150 A/cm2.
B. Drift Step Recovery Diodes (DSRD) DSRD is a special type of fast switching diodes used as “opening” switches in circuits with inductive energy accumulation [17, 18]. These devices are designed to generate short electrical pulses with the sub-nanosecond rise time and are widely used in ultra-wide-band signal generation equipment [17, 19]. Contrary to the FRED diodes requiring soft recovery, diodes of this type need a sharp current drop during turn-off switching and extremely fast blocking capability recovery. Fig. 7 shows pulses that were generated by single GaAs DSRD opening switch connected in parallel to a 50 Ohm load [17]. The rise time of the pulses is 200 ps that is the time duration of voltage restoration process onto DSRD p-n junction during switching from conduction state to the blocking state.
In terms of the switching speed, power density rating, efficiency and reliability at high operating temperatures, the high-voltage pulsed power GaAs-III-V diodes fabricated by the proposed technique, surpass all the existing analogues, including SiC and GaN Schottky diodes, currently available on the market. ACKNOWLEDGMENT The authors are grateful to V. Voitovich and “Clifton AS” company for presenting GaAs diode samples for comparative analysis.
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[11] I.L. Shulpina, T.S. Argunova, “Detection of dislocations in strongly absorbing crystals by projection X-ray topography in back reflection,” J. Phys. D: Appl. Phys. vol. 28. pp. A47-A49, 1995. [12] I.L. Shulpina, V.A. Kozlov, “X–ray topography study of defects in silicon multilayer epitaxial power devices,” The 11-th Biennial Conf. on High Resolution X-Ray Diffraction and Imaging “X-TOP 2012”, S.Petersnurg, Russia, Sept. 15-20, Book of Abstracts, pp. 182-183, 2012. [13] J. Kowalsky, T. Basler, R. Bhojani, J. Lutz, V. Dudek, D. Opalnikov, V. Voitovich, “GaAs pin diodes as possible freewheeling diodes,” PCIM2013 Conference, Nuremberg, Germany, May 14-16, Conf. Rec., pp. 975-981, 2013. [14] G. Ashkinazi, M. Leibovich, B. Meyer, M. Nathan, L. Zolotarevski, O. Zolotarevski, “Process for fabricating intrinsic layer and applications,” U.S. patent No 5733815, 1998. [15] L.S. Berman, V.G. Danilchenko, V.I. Korolkov and F.Yu. Soldatenkov, “Deep-level centers in undoped p-GaAs layers grown by liquid-phase epitaxy,” Semiconductors, vol. 34, pp. 541-544, 2000. [16] V. Voitovich, T. Rang, G. Rang, “LPE technology for power GaAs diode structures,” Estonian Journal of Engineering, vol. 16, pp. 11-22, 2010. [17] A.F. Kardo-Sysoev, “New semiconductor devices for generation of nano- and subnanosecond pulses”, chapter 9 in the book “UltraWideband Radar Technology,” Ed. by D. Taylor, Boca Raton, London, N-Y, Washington D.C., CRC Press, pp. 205-290, 2001. [18] V.A. Kozlov, I.A Smirnova, S.A. Moryakova, A.F. Kardo-Sysoev, “New generation of drift step recovery diodes for subnanosecond switching and high repetition rate operation,” 25-th Int. Power Modulator Conf. Record, Hollywood, CA, USA, pp. 441-444, 2002. [19] A.V. Rozhkov, V.A. Kozlov, “Picosecond high-voltage drift diodes on gallium arsenide base,” Semiconductors, vol. 37, pp. 1425-1427, 2003.
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