samples per packet, needs approximately 16 reads/writes from/to USRP. ⢠Thread priority: ... X310. PCIe. 79. Intel i7-6700 3.4GHz, NI PCIe x4 card. X310.
Demo: Packetized-LTE Physical Layer Framework for Coexistence Experiments
Felipe Augusto Pereira de Figueiredo
Packetized-LTE physical layer: Overview Upper Layers (e.g., MAC) Messages created with protobuf
0MQ PDSCH eNodeB
PDSCH UE
Spectrum Sensing (LBT)
User Space Host PC
Streamer #1
Streamer #1
UHD Driver
Kernel Space
Communication link (USB, PCIe, Ethernet 1/10 Gbps)
USRP Hardware
Radio #0
Radio #1
(RF, DDC, DUC, LNA, etc.)
(RF, DDC, DUC, LNA, etc.)
TX0
RX0
TX1
RX1
Demonstration: setup TX
Radio 1
Stage 1: Single link App
PDSCH eNodeB
Two link, LBT disabled App
PDSCH eNodeB
Two links, LBT enabled App
RX
PDSCH UE
TX
RX
collision
TX
RX
PDSCH eNodeB PDSCH UE
TX
RX
TX
RX
App
Radio 2
PDSCH eNodeB PDSCH UE
PDSCH UE
Radio 1
Stage 3:
PDSCH eNodeB
PDSCH UE
Radio 1
Stage 2:
Radio 2
App
Radio 2
PDSCH eNodeB PDSCH UE
App
Demonstration: stages
No competition for channel access Channel is busy, collision
Ready to Tx, but channel is busy Channel is clear, start random wait period Done waiting, starting Tx
Channel clear, start Tx
COT busy
Tx
Radio 1
wait
...
CCA
Radio 2 Tx 1st stage: RX only 2nd stage: no contention mechanism
3rd stage: LBT contention mechanism enabled
LBT time-based frame structure CCA
CCA
t Channel Occupancy Time
Idle Period
Variable or Fixed Frame
Parameter
Value
Clear channel assessment (CCA) time
Minimum: 16 [us] Maximum: 190 [us]
Channel ocuppancy time (COT)
Minimum: 1 [ms] Maximum: configurable (tested until 30 [ms])
Idle period
Variable. Can be adjusted to comply with 3GPP’s specifications.
Fixed/Variable frame period
COT + idle period. Differently from LAA we can have varibale frame periods for different loads and chanel usage.
Impact of SW latency on throughput Coding time: PDSCH + OFDM Transfer time: PHY -> UHD -> FPGA
Transfer time: FPGA -> UHD -> PHY Decoding time: peak detection+OFDM+ PDSCH
Subframe = 1 ms time Subframe is timestamped.
Time subframe is really transmitted, i.e., start of air time.
Some parameters that have direct impact on the throughput: •
• • •
Number of samples per packet, if small too many reads/writes (incurs in addtional latency) to have a buffer with subframe size or to transfer all the IQ samples to the USRP. • Example: 5 MHz BW -> subframe 5760 IQ samples -> 1 Gpbs interface -> 364 IQ samples per packet, needs approximately 16 reads/writes from/to USRP. Thread priority: uhd_set_thread_priority(1.0, true); CPU power: with more cores and hread priority/affinity TX and RX processses can run indepentendly. SW LBT procedure: it imposes addtional latency as it needs to read samples, i.e., packets, from the USRP and measure signal power before allowing transmissions.
SW-based LBT FSM Wait for subframe
Idle
yes
Subframe available for TX Measure power for CCA
Medium Busy?
yes
Measure power for CCA
Medium Busy? no
no
TX subframe
Decrement backoff
no
Backoff == 0?
yes
• Based on 3GPP’s LBT specficiations. • Implementation keeps track of channels’ occupancy statistics (usage). • Statistics can be used to find the optimum channel to be used.
Standard vs. proposed frame structure Standard Subframe #0
Subframe #1
Subframe #5
Subframe #N-1
...
... Proposed Subframe #0
Subframe #1
Subframe #5
... • • • •
Subframe #N-1
...
Data transfer does not need to start at subframe boundaries (bursty transmissions). Does not use revervation signal, which reduces radio resources utilization efficiency. eNodeB does not need to inform Channel Occupancy Time (COT) Might provide better synchronization and less subframe losses.
USRP latency Round trip latency between UHD and USRP device. USRP type
Link type
RTT Latency (us)
Host computer configuration
X310
PCIe
79
Intel i7-6700 3.4GHz, NI PCIe x4 card
X310
10 Gbps Ethernet
106
Intel E5-2650 v4 2.2GH, Qlogic 57810 Eth
X310
1 Gbps Ethernet
101
Intel i7-6700 3.4GHz, Intel i219-v Eth
B210/200mini
USB 3.0
66
Intel i7-6700 3.4GHz, Intel controller
N210
1 Gbps Ethernet
103
Intel i7-6700 3.4GHz, Intel i219-v Eth
Backup
Channel is busy, collision
Ready to Tx, but channel is busy Channel is clear, start random wait period Done waiting, starting Tx
Channel clear, start Tx
COT busy
Tx
LTE
wait
...
CCA
WiFi Tx No contention mechanism
LBT contention mechanism
Channel is busy, collision
Ready to Tx, but channel is busy Channel is clear, start random wait period Done waiting, starting Tx
Channel clear, start Tx
COT busy
Tx
LTE
wait
...
CCA
WiFi Tx No contention mechanism
LBT contention mechanism
No competition for channel access Channel is busy, collision
Ready to Tx, but channel is busy Channel is clear, start random wait period Done waiting, starting Tx
Channel clear, start Tx
COT busy
Tx
LTE
wait
...
CCA
WiFi Tx st
1 Stage: only WiFi
nd
2 Stage: no contention mechanism
rd
3 stage: LBT contention mechanism enabled
Channel is BUSY.
LTE
Channel is FREE.
Tx
WiFi Tx Minimal time between BUSY, FREE and TX states.
LTE is in TX state.
Demonstration setup
Radio 1
PDSCH UE App PDSCH eNodeB
RX
TX
TX
RX
Radio 2
PDSCH eNodeB App PDSCH UE
