Dependable Testing of Compactor MISR: an Imperceptible Problem? Andrzej Hlawiczka, Michal Kopec Institute of Electronics, Silesian University of Technology Akademicka 16, 44-100 Gliwice, Poland
[email protected] Abstract This paper shows that current techniques that use BIST’s for testing CUT’s often make impossible to distinguish which one is faulty: a CUT or a MISR. The paper shows a number of additional benefits following from making use of BIST to testing chips, FPGA circuits etc., if the only effect were that the testing of a MISR would confirm credibly the correctness of this latter. Furthermore, the paper proposes such modification of the MISR compactor structure that it makes possible to obtain reliable results of testing. Additionally, an effective technique of testing such compactor is presented and a minimal number of test clock cycles that is required for full testing its correctness is determined.
1. Introduction. Self-testing of digital circuits by built-in testers BIST (Built-In Self-Test) solves nowadays a number of problems related to testing [9]. However, efficient checking correctness of BIST before its application to self-testing of circuits is often a marginal and imperceptible problem. Such approach is characteristic, for example, for self-testing of a chip and is related in particular to the testing of a compactor. In the case of making use of BIST equipped with a compactor in the form of MISR register (Multi-Input Signature Register), the information contained in the signature determines whether the circuit under test (CUT) along with its compactor is correct or faulty. It is impossible to distinguish whether CUT is correct and MISR is faulty and vice versa without reliable results of preliminary MISR-based compactor testing. Fault localisation is unimportant when the possibility of replacement of either a chip or the whole IC exists. Thus, is the information about compactor MISR correctness necessary? Let’s take the process of verification of a chip prototype (eg. failure analysis, silicon debug). During prototyping, the information that MISR is correct would allow to localise faulty blocks of the CUT. Information contained in the signature of a correct MISR would be credible and extremely valuable for verification of the prototyping process. Nowadays, with the development of the deep submicron technology, it is possible to implement complex circuits. An example are the SoCs (System on Chip) integrated in one chip`. In order to achieve a suitably high-yield, some redundant blocks are capable of replacing defective area of the chip [11]. The decision on performing soft repair (replacing faulty blocks with correct ones) is based on the result of final testing. The
decisive influence on the efficiency of this testing has the correctness of the MISR compactor and possibility of obtaining high test speeds. Another example is the restructuring process of wafer scale systems (WSI), which requires correctness of MISR [10] [1]. Information confirming correctness of MISR is important while seeking to increase the yield when each identical chip must be independently tested at the wafer level [10, 13]. A faulty signature produced by faulty MISR causes the whole chip to be rejected although the function realised by the chip may be correct. Preliminary testing of MISR in this situation would allow to make another attempt of testing the same chip with another method and to get it back for the final yield. Another example of usefulness of determining MISR correctness can be functional testing of programmable FPGA circuits [5, 6]. Information that MISR is correct would considerably shorten execution time of the diagnostic procedure. The above examples of MISR applications confirm that the problem of testing MISR compactor which determines unambiguously whether it is correct or faulty is crucial. It has been solved in this paper.
2. Previous work. Compactors used in BIST circuits can be connected to CUT in many ways. They can be insulated from CUT or they can be directly connected to the outputs of CUT. The examples of the first manner are compactors presented in [8]. However, the most important example is a MISR register used in BILBO (Built-In Logic Block Observer) [7]. In many BIST circuits [2, 4] MISR compactor is directly connected to CUT without the need of AND cutting gates. Below, the current techniques of preliminary MISR register testing will be analysed for both manners of connecting it to CUT. In the first case, MISR can be a part of a scan path which can both serve to scan in the initial state of MISR and scan out the collected signature after completing the compaction. In both above cases MISR works as a shift register. The diagram of such compactor with its feedback described by the polynomial p(x) = 1 + p1x + p2x2 +...+pi-1xi-1 +...+pn-1xn-1+xn is shown in Fig.1. The AND gate with the control signal c1 breaks the feedback line, while AND gates at the inputs of MISR controlled by the signal c2 insulate MISR from CUT. Thus, the shift mode requires that c1c2=00. Then the serial input SI can be driven by the signal 00110011...0011, which checks all flip-flops of the register. The correct result of this
procedure collected at output SO confirms a correct functioning of MISR in shift register mode. However, the above test does not check correctness of the feedback line and AND gates insulating CUT from the compactor MISR. If the said MISR compactor is used to test CUT then a faulty signature indicates fault in CUT or in feedback line or in the above mentioned AND gates. Thus, the information about faults contained in the signature is unable to localise faulty block.
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Another disadvantage of the compactor shown in the Fig.1 is the presence of AND gates at its inputs. They slow down testing speed that is necessary for detecting dynamic faults. Additional problem, less important, is the cost of the excessive hardware and the extra control line c2. In the case of connecting MISR compactor directly to the outputs of CUT (i.e. without cutting gates) its inputs are continually stimulated and disturbed by the output vectors of CUT that change due to TPG (Test Pattern Generator). This is shown in Fig.2. Including such MISR compactor in the scan path is senseless. Thus both shifting in a desired initial state and serial reading out the signature is impossible by traditional means and must be replaced with an another technique. In addition, also an another technique of verifying MISR correctness must be used. The papers [2,4] have proposed a solution to these problems. Among all, they propose an idea of testing MISR compactor by the vectors that appear at the CUT output in response to a serial seeding of TPG. The advantage of this approach is making use of time destined for seeding generator TPG to concurrent testing of MISR compactor. However, this approach has essential disadvantage. It does not guarantee that all potential faults of MISR will be detected. It results from the fact that the vectors at CUT output are side effects of TPG seeding and are not intended for MISR testing. In fact, they can miss some MISR faults. Therefore, the result of testing may be unreliable. Unknown vectors testing MISR in the case when CUT is faulty creates another disadvantage. That can also be the cause of unreliable result of MISR testing.
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Fig.3. MISR-NOT compactor.
Fig.1. MISR compactor linkable into scan path.
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will justify that obtaining reliable results of MISR testing requires modification of MISR’s structure. With this end in view let’s assume a register with internal exclusive-or feedback path. The main modification consists in including a NOT gate in the main feedback just after the output Qn of the last flip-flop. The example of such modification of feedback is given in Fig.3. Further, such compactor will be denoted MISRNOT.
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Fig.2. MISR compactor that cannot be linked into scan path. This paper presents a new method of MISR compactor testing which detects all its faults and determines unambiguously whether the compactor is correct or faulty. We
This approach can be applied to both cases: the case when AND gates cuts MISR-NOT from CUT (Fig.1) and the case when the output of CUT directly drives the input of MISR (Fig.2). In the last case, the compactor cannot work in shift register mode and what follows, it is impossible to link it into a serial scan path. Instead of this, possibility arises to test CUT with full speed necessary for detecting dynamic faults (delay faults). In the first case, AND gates together with CUT will be treated as one block denoted as TUC-AND. We assume that the faults at the inputs of a compactor connected to CUT (CUT-AND) will be detected during testing of CUT (CUTAND). It will be proved that a fault in CUT has no influence on the results of testing MISR. In chapter 3, we will present a general outline of the proposed idea of MISR-NOT compactor testing. Chapter 4 will study properties of MISR-NOT register, which allow obtaining reliable information about MISR-NOT compactor correctness. The next chapter 5 will give results of test experiments of MISR-NOT registers for all primitive polynomials of degree n
