Description and Implementation of a Single Board Computer for ...

Description and Implementation of a Single Board Computer for Industrial Control by J. Piecha

Eindhoven University of Technology Research Reports EINDHOVEN UNIVERSITY OF TECHNOLOGY Department of Electrical Engineering

Eindhoven

The Netherlands

DESCRIPTION AND IMPLEMENTATION OF A SINGLE BOARD COMPUTER FOR INDUSTRIAL CONTROL

By

J. Piecha

EUT Report 81-E-120 ISBN 90-6144-120-X

Eindhoven June 1981

- i -

Piecha, J. DESCRIPTION AND IMPLEMENTATION OF A SINGLE BOARD COMPUTER FOR INDUSTRIAL CONTROL. Department of Electrical Engineering, Eindhoven University of Technology, 1981. EUT Report 81-E-IZO

Abstract. The report contains a description of a single board computer based on the Intel 8085 microprocessor. It includes the features: 4K bytes uv erasable programmable read-only-memory, which can be extended to 8K bytes, 8K bytes of random-access-memory, two full duplex serial interfaces, parallel interface (48 lines), programmable timers, programmable interrupt controller and keyboard/display controller. The debug monitor program was also elaborated and a short description of this program is presented in this report.

Present address of the author: Jan Piecha, Uniwersytet Sl.ski, Katowice,

Poland

- ii -

Acknowledgements The author would like to thank the members of the Digital Systems Division of the Electrical Engineering Department of Eindhoven University of Technology for their kind help in realisation of this project, especially Ir M.P.J. Stevens, Ir H. Kemper and lng. C.H. Van Hooidonk. The help of Professor A. Heetman in organizing the autor& study is also greatly appreciated.

- iii -

Table of contents 1. 2. 2.1 2.2 2.3

Introduction General description of the computer The block diagram comments Memory and I/O addressing Components specification

3. 3.1

Specifications of single board computer Serial communication

3.2 3.3 3.4 3.5 4. 4.1 4.2 4.3 4.4 4.5 4.6 5. 6.

I/O addressing Interface compatibility Connector assignment Jumpers configuration Description of the debug monitor program Capabilities of the program Monitor commands I/O devices, drivers System initialisation The RAM storage and interrupts location Specifications of routines accessible for the user Conclusion References

Page 1 2 2 4 7 10 10 11 11 11 13 18 18 18 19 19 20 21 25 26

Single Board Computer

Jan Piecha

1.

1. Introduction The single board computer described in this report has been built and tested by the author during his SmIs.%arl.~. in the Electrical Engineering Department of T.R. Eindhoven.The configuration and main set of components have been defined in the Digital Systems Division. This computer vas placed on a single printed circuit assambly with an optional Keyboard/Dis play board. The board of the computer includes a 8085 processor (CPU), 4K bytes (2716) or 8K bytes (2732) EPROMs, two serial (8251) and six parallel (2x 8255) I/O ports, a Programmable Timer (8253), a Programmable Interrupt Controller (8259) and a Keyboard/Display Controller (8279).The debug monitor program, which can be placed in 2K bytes of EPROM, vas elaborated for this system. The block diagram of this computer was presented in Fig.1 •


Jan Piecha

2.

2. General description of the computer 2.1 The block diagram comments The microcomputer mentioned in Fig.1 is composed of the folloving main parts : - 8085 microprocessor (CPU), - ROM 2716 or 2732 and RAM 8185, - serial I/O interface 8251, - parallel I/O interface 8255, - programmable timer 8253, - programmable interrupt controller 8259, - keyboard/display controller 8279. The control, data and address lines are connected as follovs: - RD and WR lines of the processor are connected with every component via line drivers, - data bus of the computer is driven by the drivers 8286, the transmission direction of 8286 is controlled by the data bus drive 10 gic, - lover bus address of the processor is externally latched in the 8282 Ie, - interrupt inputs : TRAP, RST 7.5, RST 6.5, RST 5.5 of the processor are connected vith jumpers in interrupt matrix, - interrupt input INTR of processor is connected vith interrupt controller 8259, - the address lines are used to select a cell of the memory or I/O interface (memory mapped I/O), - address lines AO,A are also used as control lines for every pro1 grammable block, - the standard clock cristal 6.144 MHz vas applicated in this system. The chip select block is controlled by A15~ ~ and A ,A ,A address 6 5 4 lines.Fulldeecription of this selection is presented in the next chapter. The ROM block contains tvo 2716 (4K bytes) or tvo 2732 (8K bytes) chips. Tvo different capacities of the ROM are available by the jumpers used in this computer (compare Table 12). The RAM block hae the capacity


Jan Piecha

3.

of 8K bytes and is composed of eight 8185 chips. Both ROM and RAM chips are selected by CS and R/w lines. The Programmable Timer 8253 can be software programmed to a fev modes [2) • Its three otputs (02 ,0 ,00) of three counters can be used as a clock 1 control lines for TxC and RxC inputs of 8251 and to generate the one-shot pulse for a single step procedure. The jumpens installed on the board give the possibility to choose the most convenient version of these controls. Tvo 8255 IC allov the user to connect to the computer 48 parallel I/O lines, which can be individually software programmed (2)'. Lines PC and O PC of both 8255 can be programmed to interrupt the work of the computer. 3 The interrupt version can be chosen by the set of jumpers installed on the board (compare tables 13, 14 and 18). Lines PCi of the 8255-0 can be used as a programmable clock for the timer and as a programmable gate enable signals for GO and G of the timer. The ring indicator and data carry de1 tect can be detected on the PC lines of the 8255-1. i The serial I/O communication can be done by two 8251 chips. The jum pars installed on the board and the timer allow the user to choose the most covenient version of the serial I/O communication. The frequencies of RxC and TxC of both serial I/O interfaces can be different and can be programmed by the timer or forced externally. Lines RxRDY and TxRDY of both 8251 can be used to provide the interrupt signal to the interrupt controller.

The computer contains Keyboard/Display controller 8279 which allows the user to connect the Keyboard/Display board. This board allows simple commands and datas to be entered in the computer, to test the resuls of the computer work, etc. Multi-level priority interrupts are available in this computer not only by the facilities of the TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR of the 8085 3 but due to Programmable Interrupt Controller which is also installed on the board (2) •

-------------


\

Jan Piecha

4.

2.2 Memory and I/O addressing The presented computer is designed to satisfy a variety of applioations.Therefore the user needs to install only those components which are necessery in his particullar configuration. The address of the system vas devided into three parts: ROM, RAM and I/O interfaces. The space OOOOH to OFFFH vas reserved for EPROM, 2000H to 3FFFH for RAM and 400xH to 407xH for I/O interfaces. The last part of the address space is unused. Each of these blocks is., divided into a few integrated circuits. As it is shown in Table 1. EVe~ Input/Output data transfer is realised by a memory Read/Write command (memory-mapped I/O). Each chip is selected as follows: a) Group Selection A14 A13 0 0 0 1 1 0 1 1

(GS)

GS ROM RAM I/O free space

b) ROM address space

4K blocks (2732) , CS - chip select (active) A12 = 0 , CSO= 0 (active)

o - lov level (positive logic) , 1 - high level vhere: CSO= A14v A13 v A12

- lover 4K

CS1= A14 v A13 v A12 2K blocks (2716) ,

- higher 4K


Jan Piecha

Table 1 Address Assignments Memory,Interface

Address Space

EPRCM 2716 - 0

000 0

o7 FF 2716 - 1

080 0

OFFF

EPRCM 2732 - 0

0000

2732 - 1

OFFF 1 000 1 F F F

RAM

8185 - 0

,

20 0 0

23F1 8185 - 1

240 0

2 7 F F

8185 - 2

2 80 0

25FF 8185 - 3 8185 - 4 to 7

2 COO 2 F F F 3 0 0 0 3 F F F

8251 - 0

400 x

- 1

401 x

8255 - 0

402 x

- 1

403 x 40 4x 40 5 x

8259 8253 8279 n.e.

406x

407 x

5.

Single BOard Computer

6.

Jan Piecha

vhere: CSO= A'4 v An v A"

- lover 2K

CS,= A'4 v An v A;, - higher 2K c) RAM address space A12A11A10 0 0 0 0 1 1

1 1

0 0 1 1 0 0 1 1

0

CS - 8,85 0

1

1

0 1 0 1 0 1

2 3 4 5

each chip lK byte (~.;.

Aa)

6

7

d) 1/0 space ~ A5 A4 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1

0 1

0 1 0 1 0

CS for interface 8251 8251 8255 8255 8259 8253 8279

-

0 1 0 1

1

Full address of interface device is Bupplemented by AO,A address line va1 lues, vhere: 8251 - 0 is addressed: 4000 - Data 4001 - status, Control 8251 - 1 4010 - Data 4011 - StatuB, Control 4020 - Port A (1) 8255 - 0 4021 - Port B (2) 4022 - Port C (3) 8255 - 1

4030 4031 4032 -

" II· II

(4) (5) (6)

8259

4040 4041

8253

4050 - Counter 0 4051 4052 4053 - Mode

1 2


8279

Jan Piecha

is addressed

7.

4060 - Data 4061 - Command/Status

These section blocks have been built on OR gates (chip A9) and demultiplexers 8205 (chips A15 and A16) and are mentioned on sheet No.2 of Fig.2 • The complete schematic diagram of the computer is presented on five sheets of Fig.2 and includes: - Central Processor Unit, - Memory and Chip Select, - Serial Interface, Timer and Interrupt Controller, - Parallel Interfaoe, - Keyboard/Display Controller. Sixth sheet contains scme of external board - Keyboard/Display Unit ( Fig • .3 ). Grid references to each part of diagram consist of four alphanumeric characters. For example 2ZB1 signifies sheet 2 zone B1. 2 • .3

Components specification

All the components used in the computer are listed in Tables: 2, .3, • •• , 7 mentioned below • Table 2 Parts list for CPU block (sheet 1) Chip Assignment

Function

Type

No.of campon.

1

2

.3

4

A0

microprocessor

8285

1

A7 A8 A .39 A 47 A 48

8282

-

address bus latch system clock drive driver driver data bus driver cristal capacitor

1 1 4/6 .3/4 1 1 1 2

-

resistor

-

" "

7474 7404 7408 8286 6.144 4.7 uF/50V 20 pF/25V 2.2k/0.1W 470 ohm/ 1/4 W

4 1

Jan Piecha


8.

Table 2 Continued 2

1

-

diode (LED) diode

3

4

MV5153 1N914

1 1

Table 3 Parts list for memory, Chip select block (sheet 2) 2

1 A 1, A 2 A 3, A 4, •• , A7 A 15, A 16 A9 A 39 B1

..

EPROM RAM

Demultiplexers OR gate Invertor Jumper

3

4

2716 or 2732

2

8185 8205 741S32 7404

-

8 2 3/4 1/6 1

Table 4 Parts list for Serial I/O, Timer, Interrupt Controller (sheet 3) 1 A10,A11 A 12 A 19 A 20, A 21, A 23, A 24 A 22, A 25

A 38

B 2, B 3, B 6, B 7 A 39

2 Serial I/O Programmable Timer Programmable Interrupt Controller Data Receiver Data Tranemitter NOise Capacitor OR gate NOise Capacitor Jumper driver

3

4

8251 8253

2 1

8259

1

1489 1488 390 pF 7432 220 pF

4 2 6 1/2 S

7404

4 1/6


Jan Piecha

Table 5 Parts list for Parallel

1

block (sheet 4)

2

A 13, A 14 14 pin 80Ckets for interface driver B 4, B 5

Table 6

r/o

Parallel

3

r/o

Jumper Resistor

Parts list for Keyboard/Display block

1 A 17 A 40, A 41

9.

8255 undefined drivers

4 2 12

-

2 1

2.2kjO.1W (sheet 5)

2

3

4

Keyboard/Display Driver

8279 7407

1 2 1/6

A42 The jumpers are installed to allow.the user: - to select 2716 or 2732 EPROMs, - to choose a covenient configuration of interrupts, - to select a suitable baud rate, aerial clock -to select an actual combination of serial and parallel r/o ports - to select timer/counter functions. A fuJldescription of the jumpers is presented in the next chapter of this manual.


Jan Piecba

10.

3.Specifications of single board computer 3.1 Serial communication Two serial I/O devices can be connected with the computer. The I/O devices can work in two different modes : - synchronous : 5,6,7 or 8 bit characters, 1 or 2 SYNS characters , automatic SYNS insertion , - asynchronous :5,6,7 or 8 bit characters, brake character generation , 1,11/ ,2 stop bits, 2 false start bit detection. Different frequencies of the serial transmission are programmed with the interval timer l8253). Sample baud rates for synchronous and asynchronous tr8.B8ll1sPOIl are presented in 1:able 8. The system clock fr_ quency is equal to 3.072 MHz while the input frequency of the interval timer is 1.536 MHz. Table 8

Sample Baud Rates for serial transmission

Frequency kHz (software selectable)

153.6 76.8 38.4 19.2 9.6 4.8 2.4 1.76

Baud Rate [Hz] Asynchronous Synchronous

·38400 19200 9600 4800 2400 1760

Frequency factor 16 x

64 x

9600 4800 2400 1200 600 300 150 110

2400 1200 600 300 150 75

-

Jan Pieoha


11.

3.2 I/O addressing Communication with Parallel and Serial Ports, Timer, Interrupt Controller and Keyboard/Display Controller is via memory read/write commands ( Mn.lR, Mn.lW ) !'rom the CPU. 3.3 Interface compatibility Parallel

48 programmable lines (6 ports), IC sockets included for user instalation; as port interfaces. Serial I/O: serial ports, EIA standard RS232C signals provided and supported:Receive Clock, Transmit Clock, Receive Data, Transmit Data, Request to Send, Clear to Send, Data Set ieady, Data Terminal Ready, Cl!rier Detect, Ring Indicator.

3.4 Connector assignment The PC board of the computer is connected with external devices by connectors mentioned in table 9. Table 9 Connectors" Connector type

Assignment

0.1

Flat Crimp

J1,J2

:0/26

0.1

Flat Crimp

J3,J4

25/50

0.1

Flat Crimp

J5

4

-

Mollex

P1

Function

No. of Pairs/Pins

Inches

Parallel I/O Connector

25/50

Serial I/O Connector Keyboard/ Display Power supply

*

.

The transmition path !'rom SBC to the I/O source is limited to 3 meters (1)


Jan Piecha

12.

Connector.T1 ( and J2 ), parallel I/O Pin numbers : 2,4, ••• , 16 are connected to the 8255 port 2 (5); pins 7,6, ••• , 0 18,20, ••• ,32 3 (6)* n 1(4) 34,36, ••• ,48

"

All Odd-numbered pins are on the component side of the board and are grounded. Pin 1 is the right most pin, seen from the computer side of the board with the connectors at the top. The description of connectors J3 ( J4 ) and J5 is presented in Tables 10 and 11 respectively. Pins 2 of J3 (.T4 ) and 1 of.T5 are the right most pins seen from the components side of the board, with connectors J1 and J2 at the top - compare assignment on layout mentioned in Pig.4. Table 10 Connectors J3 ( and J4 ) assignment, serial I/O Pin No.

4 6 8 10 12 14 16

-

• •

•

-

..

Assignment

-

Transmitted Data Received Data Request To Send Clear To Send Data Set Ready GND Reg. Line Sig.Dat.

-

• • •

-

Pin No.

3 5 7

-

13

17

• •

•

-

Assignment

Trans.Sig.Ele.Timing Sec. Rec.Data Rec.Sig.Ele.Timing

Data Terminal RDY

-

Ring Indicator

• •

•

-

The port 3 and 6 can be rearanged using jumpers 52 and B3

Jan Piecha

Single Board Computer Table 11

Connector J5 assignment, Keyboard/Display

Pin No. 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Assignment RLO

RL1 RL2 RL3

RL4 RL5 RL6 RL7 S10 SL1 SL2 313 BO B1 B2

B3 AD A1

Assignment

Pin No.

A2

37 39 41 43 45 47 49 2 4 6 8

10 12

A3 RESET IN READY

,

SHIFT CNTL TEST IN BD GND GND

•

• •

• •

50

• GND

Connector P1 , Mollex Power supplies : + 12 V, - 12 V and + 5 V DC voltage are connected \lith the board using a connector, the Mollex type, as follows : pin numbers voltage Pin number 1 of board, \lith the

- 1 2 3 4 - +5V,+12V,-12V, GND P1 is the right most seen from the components side of the connector J1 and J2 at the top.

3.5 Jumpers configuration The jumpers installed on the board allo\l the user to choose the most convenient configuration of baud rates , interrupts, serial and parallel

•

13.

Jan Piecha


rio. The main set of jumper connections is presented in tables 12 to 18. Other possibilities are also available. Table 12 Jumpers B1 Numbers of shorted pins

Function

1 4

3 6

Selected EPRS SUfi

A 1 -:- Ao

INTR

8282

8085

LATCH

CPU

8

2

RST 7.'

rr-INTI!:R.~1,T)I,R ,Rll'R

'RST 6.'

~ INTeA..I),

FIST

C5 ALE

8

LOGIC

~ 'EXT. INTER.

r- TRAP

1

ts.5

INTER1WPT

f-

~ INTER·!Sl

I-- I>lT,0..78

MATRIX

~

RD WR

e /

DATA BUS DRIVE LOG.

R/W DRIVER

r---

INT

82B6

I

2

7

BUS DRIVER

B

I

PyW

CO NTROL DATA BUS C5 CO NTRDL

~

C5

DATA

1\/W

CS

DATA

C5

8255-1

8255-0 f-INT

DATA 11./101 82~-O

CS

1\/W

DATA

825H

RxD T",D lI.. e/A.e

bli TiD

RJ6

I

PORT 5

R

I GND

I I BIT7

~.,

P

8.. 'ZC5 I RQS5'/P 3ZAIt

PORT2

R&

0' 2%"'2-

I I

A30

8255-1 T 4 A14 c~ •7

I~:

/lIT 7·

,•.sk~.,

!

ro

RT1

PORT :'J

t

~7

o

BIT ()

~,= ;;

~ ~

"e

. _

~7-t'COUNT

0

~

Pi

Al?

7; I~ 5 I~ •

t "" "

UM

Ii IS-O/O 'UA.

4

"1...,

I~' ~&

"

.

l~o.OII-ol'

A37

A

I

81T 7 -t Prlilloc«.n PIN"7eND

ALL 0 00 PIN NUMBERS

FIG.Z PARALLEL I/O

~"EET"

D

IRQ711

.

4 1%

_v

1$ 1
OARD/

IDI&PLAY

-

(E.t."~ .. l

!>OClr!' 74(11

,'i

Mt.

,.--

P.."I

_.IN-fi-

TaT IN

:lI

B

SHIFT CNTL

IV

t::I Ir.I

~D

t-t--

I' J6

~£VE.ftN' 5Kc.LUDINI 1.-4-6-8 .,. Vc!'.5V PINS '15-47-'t9

L..L.C)-'

TESTI~

~()-< --'"

RES.'&.TI

, 0-.• ~

RaAt1