2.4 A Practical Techniques in High-Speed PCB Layout . ...... 8 MB Quad SPI and 512 kB program flash. ⢠32 MB SDRAM, 96 kB SRAM, 4 kB ... memory, up to 96 kB of SRAM data memory, up to 4032 byte of EEPROM data memory,. External ...
Design and Implementation of a High Precision Instrumentation System Artem Sadula June 2016
Submitted to the Institute of Electrical and Electronics Engineering in partial fulfilment of the requirement for the Bachelor of Engineering (Honours) in Electronics and Control Engineering
Declaration of Authenticity
I, the undersigned, declare that the thesis entitled
Design and Implementation of a High Precision Instrumentation System
This dissertation is based on the result of research carried out by myself, is my own composition, and has not been previously presented for any other certified or uncertified qualification.
This research was carried out under the supervision of Ing.Clive Seguna
Signed___________________________Date___________
Copyright statement
In submitting this dissertation to the MCAST Institute of Engineering and Transport I understand that I am giving permission for it to be made available for use in accordance with the regulations of MCAST and the College Library.
Signed___________________________Date___________
Contact address (Artem Sadula, 38B Charivnaya Street, fl. 32, 69076, Zaporozhye, Ukraine)
Acknowledgements
Ing. Clive Seguna, who supported me during my dissertation work as my tutor.
Table of Contents
Table of Contents............................................................................................................................. 5 Abstract ............................................................................................................................................ 7 Introduction ..................................................................................................................................... 8 2.0 Literature review........................................................................................................................ 9 2.1 Definition of Measurement Terms ............................................................................................ 9 2.2 Signal-to-Noise Ratio (SNR) to Effective Number of Bits (ENOB)....................................... 11 2.3 Noise Reduction with Filtering................................................................................................ 12 2.4 Filter for Noise Reduction ....................................................................................................... 13 2.3 Alternative oscilloscope architectures ..................................................................................... 15 2.3.1 FPGA Versus ASIC .............................................................................................................. 15 2.3.2 Using FPGAs and the IEEE1451.0 for designing alternative embedded instruments ......... 17 2.4 A Practical Techniques in High-Speed PCB Layout ............................................................... 20 2.4.1 Power Supply........................................................................................................................ 20 2.4.2 Rails to Ground Technique ................................................................................................... 20 2.4.3 Rail to Rail Technique .......................................................................................................... 22 2.4.4 Parasitic Effect ...................................................................................................................... 22 2.5 Challenges of High-Speed DSP Design .................................................................................. 25 2.5.1 General Challenges ............................................................................................................... 25 2.5.2 Transmission Line (TL) Effects ........................................................................................... 28 2.5.3 Transmission Line Theory .................................................................................................... 28 2.5.4 Practical Considerations of Transmission Line Theory ....................................................... 31 2.5.5 Ground Grid Effects on TL .................................................................................................. 31 2.6 Oscilloscope probes ................................................................................................................. 33 2.6.1 Loading Effect and the Oscilloscope .................................................................................... 34 2.6.2 Probe Compensation ............................................................................................................. 34 2.7 Calibration System .................................................................................................................. 35 2.7.1 Step Response Calibration Architecture ............................................................................... 36 2.8 The Main Board ....................................................................................................................... 37 2.8.1 The Main Core on the Board ................................................................................................ 38 2.8.2 32-bit Multiply-Accumulate (MAC) Unit ............................................................................ 38 2.8.3 Floating Point Unit (FPU) .................................................................................................... 39 5
2.8.4 Comparisons between Cortex-M3 and Cortex-M4 .............................................................. 39 2.8.5 SPI interface. ........................................................................................................................ 40 2.9 Software ................................................................................................................................... 41 2.9.1 MBED Online Development Platform ................................................................................. 41 2.9.2 Keil MicroVision - ARM Development Tools ..................................................................... 42 2.9.3 LPCXpresso – Development Tools from NXP Microcontrollers ........................................ 43 3.0 Methodology............................................................................................................................ 44 3.1 Hardware construction ............................................................................................................. 46 3.2 Display module ........................................................................................................................ 49 Table 2: LCD Input Signal Definitions ......................................................................................... 49 3.2.1 Mechanics of an LCD Panel ................................................................................................. 50 3.4 Independent Power Supply Circuit .......................................................................................... 53 3.4.1 TP4056 Lithium Polymer Battery Charging Module ........................................................... 54 3.4.2 MT3608 DC to DC Boost Converter .................................................................................... 54 4.0 Software Implementation ........................................................................................................ 54 4.1 Main.cpp .................................................................................................................................. 55 5.0 Testing ..................................................................................................................................... 56 6.0 Conclusion and Future Work ................................................................................................... 66 6.1 Frame-Based Processing.......................................................................................................... 66 6.2 High speed ADC ...................................................................................................................... 67 6.3 Using FFT instead of DFT....................................................................................................... 67 6.4 Power Supply........................................................................................................................... 67 6.5 Conclusions ............................................................................................................................. 68 7.0 References ............................................................................................................................... 69 Appendix A (Main Program Flowchart) ....................................................................................... 70 Appendix B (Main.cpp) ................................................................................................................. 71 Appendix C (Display.h) ................................................................................................................. 75 Appendix D (Display.cpp) ............................................................................................................. 76 Appendix E (EaLCDBoardGPIO.h) .............................................................................................. 79 Appendix F (EaLCDBoardGPIO.cpp) .......................................................................................... 80 Appendix G (Discrete Fourier Transform Function) ..................................................................... 82
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Abstract Modern instrumentation systems are largely based on digital technology. Digital instruments are developed by using dedicated ICs, microcontrollers and microprocessors that give them flexibility in information handling, networking and data communications. In manufacturing industry, processing plants, control and automation, and in other industrial applications, many instruments are used together to form very large instrumentation systems. These large systems can only be handled by a computer, or a number of computers. This proposal discusses microprocessor and computer-based instrumentation systems. Therefore, a large proportion is dedicated to the basic principles of digital systems and digital process controllers. Today, many advanced instrumentation systems are available, mainly directed at improving the productivity of industry and product quality. In many applications, instrumentation systems are custom-designed to meet specific process requirements. At the same time, instrumentation systems may have high initial costs, and in some cases they may lead to a loss of flexibility in production. Since the mid-1980s, many large firms have invested heavily in the procurement of hardware and software, creating extensive demand and accelerating research and development related to instrumentation and instrumentation systems. This project was chosen because while studying at the Malta College of Arts, Science and Technology, Electronic Engineering Institute, various electronic equipment were built, keeping in mind that they may be useful in the near future. The project entails the following tasks. A very good research is needed to understand the operation of a High Precision Instrumentation System. Then the project needs to be divided into three parts. Analog part will include the power supply circuit and offset circuit. Digital part includes theory of how the signals transferred through microprocessor component parts. A software part is the toughest task of the project. A part will help in the research of the processor architecture and introduces the reader to my way of project realization. Finally, the testing and calibrating of the High Precision Instrumentation System will be done.
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Introduction The purpose of this project is to implement data acquisition system to measure voltages in the ranges for example 10 µV to 50V and currents ranges 10 µA to 3A respectively with a 7 or 8 digit measurements. The system includes a high-performance microcontroller for example LPC4088 based on the Cortex-M4F core and a 4.3–inch color display. The main components of the system are shown in Figure 1. The measured signal applied to an analog-to-digital converter (ADC), it is quantized, converted into a stream of digital data and memorized in a special memory unit inside LPC4088. These preliminary operations are referred to as data collection. The data are processed, formed recording waveforms and frames, and they are displayed on the LCD display.
Figure 1: Block Diagram of an Instrumentation System An important parameter is the speed of a digital oscilloscope and waveform update rate on the screen. It ranges from a few thousand Hz to hundreds kHz. To increase the speed waveform update data collection is transferred directly from the memory device via a high-speed bus to the LCD screen, it uses a large amount of high-speed memory. It contains an external probe, input terminal, switch the input type (open, closed, grounded) plug 50 ohm termination resistor, the input divider (attenuator), amplifier and low-pass filter. Analog block parameters largely determine the parameters of conventional digital oscilloscope: band frequencies studied, zero drift, the offset and sensitivity vertically. The device is to be developed allowing for a more accurate investigation of data and to facilitate troubleshooting of integrated circuits at the same time without taking up a lot of space, with high autonomy and quality matrix LCD. The main reason I chose this project is that the project covers almost all aspects of analog and digital circuitry and allows in practice apply the knowledge in programming, it also unite the acquired knowledge. This project helps me in a deeper understanding of the basic problems encountered in electrical engineering analysis.
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2.0 Literature review The introduction in design and implementation of a high precision instrumentation system (HPIS) is increased necessity for more in-depth signal analysis in different areas of science and technology; where it is often required recognize multilevel signals. To make an accurate measurements the HPIS must obtain the voltage during the off and on times within the same waveform. The ADC needs more dynamic range than the 8 bit resolution can provide, since the voltage difference can be more than hundreds of volts. When evaluating a high precision oscilloscope for different applications, its vertical resolution is becoming a key criterion to look at, besides standard parameters such as sample rate, memory depth or bandwidth. The vertical resolution regulates how precise signal details can be shown on the oscilloscope screen and how accurate these details can be measured and analyzed. The main component of a digital oscilloscope with regard to vertical resolution is the analog to digital converter. It converts the analog signal at the input channel of the oscilloscope into time and value discrete samples that can be processed and stored in the device memory. The time resolution between the samples is given by the analog to digital converter’s sample rate. The number of A/D converter bits determines the nominal vertical resolution. Digital oscilloscopes typically use 8 bit analog to digital converters. Usually specialized oscilloscope models offer much more than 8 bits of vertical resolution. One of the opportunities to achieve that is to use analog to digital converters with more than 8 bits. Another approach is to apply DSP techniques in the acquisition path to gain additional resolution. In one and the other cases must take into account that the number of bits specification analog to digital converter is a theoretical value. The resolution called the effective number of bits (ENOB) below the nominal value due to incorrect sources, such as noise, non-linearity and distortion. Furthermore, when assessing the dynamic characteristics of the oscilloscope front end to other components such as an amplifier , a filter and parasitics must be taken into consideration , not only an analog- digital converter.
2.1 Definition of Measurement Terms Acquisition of knowledge of how to use an oscilloscope involves learning the measurement and performance terms of an oscilloscope. Understanding the terms help us better understand research.
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Among the important performance terms and considerations are bandwidth, rise time, sample rate, waveform capture rate, record length, effective bits, sweep speed and gain accuracy. One of the important terms is bandwidth; this specification represents an oscilloscope’s fundamental ability to measure a signal, and indicates the frequency range that it can actually measure. Without sufficient bandwidth, high-frequency changes and details will be lost. The oscilloscope cannot resolve high-frequency changes if it does not have sufficient bandwidth. Edges will vanish, while amplitude will be distorted and details may be lost. Without sufficient bandwidth, the oscilloscope’s features will mean nothing. Describing the oscilloscope’s useful frequency range, rise time measurement is critical in the digital world. It is an important performance consideration when measuring digital signals, such as steps and pulses. The oscilloscope must have adequate rise time to capture the details of rapid transitions accurately. Another important parameter is sample rate which specified in samples per second (S/s).It is the number of times an ADC takes a sample of the signal. The higher the sample rate (i.e., the faster the oscilloscope samples), reduces the chances of losing critical information or events, while offering the displayed waveform more detail and resolution. Minimum sample rate is important when viewing slow changing signals over longer periods of time. Generally, changing the horizontal scale control will also alter the displayed sample rate.
The following are the parameters that are decisive in high precision systems:
Waveform Capture Rate—specified as waveforms per second (wfms/s). Refers to how quickly an oscilloscope acquires waveforms.
Record Length—express the amount of data that can be captured from oscilloscope input channel.
Effective Number of Bits – a measure of a digital oscilloscope's ability to accurately reconstruct a sine wave signal’s shape. This measurement compares the oscilloscope's actual error to that of a theoretical “ideal” digitizer.
Sweep Speed – oscilloscope circuitry that controls the timing of the sweep. The time base is set by the seconds/division control.
Gain Accuracy - an indication of how accurately the vertical system attenuates or amplifies a signal, usually represented as a percentage error. For an oscilloscope the hardware architecture determines the nominal precision. The
systematic errors of the hardware implementation, like noise and dynamic non-linearity, define 10
the resolution and the random errors of the system, like offset and static nonlinearity, characterize the bias. Different components contribute to these different errors, not only the A/D converter. (Standardization, 1994) Commonly oscilloscopes use analog to digital converters with 8 bit numerical precision. Some specialized oscilloscopes use analog to digital converters with 10 up to 12 bit or higher nominal resolution or precision. If an oscilloscope has a good accuracy and resolution, then, and only then, an increase in precision will improve the resolution and consequently the accuracy of the measurement by a finer vertical granularity. The next chapter will show how digital signal processing can achieve an increase in resolution and precision.
2.2 Signal-to-Noise Ratio (SNR) to Effective Number of Bits (ENOB) Various errors analog-to-digital converter limits the accuracy of the oscilloscope. Therefore, it is important to understand the relationship between the resolution and the precision of the oscilloscope expressed in bits. The precision of the ADC is not equal to the effective resolution of the oscilloscope. To characterize the effective resolution oscilloscope, the signal-tonoise ratio is measured (Society, 2001). Using the signal-to-noise ratio, the effective number of bits will be derived as a measure for the effective resolution. For an ideal analog to digital converter the relation between the calculated signal to noise ratio represented in db (𝑆𝑁𝑅𝑑𝐵) and the resolution is given in several references (John G. Proakis, 2007) and equation 1 is represent this expression: 𝑆𝑁𝑅(𝑑𝐵) = 6.02 ∙ 𝑁 + 1.76
(1)
An oscilloscope with a real world ADC has the noise, non-linearity and distortion. To relate the real world analog to digital converter with the ideal ADC, the root mean square (or RMS) quantization error of an ideal ADC is set equal to the noise of RMS and distortion of the high precision instrumentation system. Using the measured signal to noise ratio (𝑆𝑁𝑅.𝑀𝑒𝑎𝑠), the effective resolution in bits can be determined. In equation 2 are shown the expression between those terms. The resolution is representing as bits of an ideal A/D converter, which is not necessarily an integer, and is called effective number of bits (ENOB). 𝐸𝑁𝑂𝐵 =
SNR.Meas – 1.76 6.02
(2)
For oscilloscopes with real analog to digital converters the effective number of bits will be lower than the precision expressed in NOB due to noise and distortion.
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2.3 Noise Reduction with Filtering Trends in the area of analog-to-digital development (Walden, 1999) show, that the sample rate of new AD converters designs increases over time, because the resolution of the analog-to-digital converter designs are almost constant. With this trend in mind, techniques have been developed, which can improve the resolution of an analog-to-digital converters in the digital domain, like the one which represented in this section. These techniques change sample rate with vertical resolution for oversampled signals. One of example is the 1-bit sigma-delta analog-to-digital converter in 24-bit audio applications. The noise of an ideal analog-to-digital converter is identical as high quality real analogto-digital converter can be regarded as white noise (John G. Proakis, 2007). White noise is evenly distributed in the spectrum, means that in the interval [−𝑓s⁄2 ≤ 𝑓 ≤ 𝑓s⁄2] the noise spectral density (𝑓) is constant. The magnitude of the noise spectral density in this case equals the total RMS noise power 𝑃𝑛 divided by the sampling frequency 𝑓s. It represented in expression (3). In case of oversampling, means the bandwidth of the signal (𝑓) is much smaller than the sampling frequency 𝑓s. This section presents a rectangular filter (𝑓) with a cut-off frequency 𝑓c. This is shown in Figure 4. From the figure, it becomes obvious that the total noise power is reduced by the ratio of sampling frequency 𝑓s to cut-off frequency 𝑓c. The signal-toquantization-noise ratio in decibels is expressed in equation (4) and the over-sampling ratio in equation (5). pN(f) =
𝑃𝑛 𝑓𝑠
(3)
Figure 4: Reduction of Noise Power by Filtering.
𝑆𝑄𝑁𝑅𝑜𝑣𝑒𝑟𝑠𝑎𝑚𝑝𝑙𝑖𝑛𝑔 = 𝑆𝑄𝑁𝑅𝑛𝑦𝑞𝑢𝑖𝑠𝑡 + 10𝑙𝑜𝑔/𝑂𝑆𝑅
(4)
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Where, 𝑓𝑠
𝑂𝑆𝑅 = 2∗𝑓𝑐
(5)
This shows that SQNR can be improved by 3 dB for OSR=2 while eliminating out of band noise. This result is true for any quantizer. (John G. Proakis, 2007)
2.4 Filter for Noise Reduction The previous sections showed the difference between the accuracy and resolution, and how the resolution can be corrected by using low pass filter. This section will explain how the filter will bound the bandwidth and raise the precision, so that the profit in resolution can be displayed with satisfactory precision. A few types of low pass filter are possible to limit the bandwidth, but in this section the focus is on a moving average filter. A moving average filter determines the arithmetic average for every output value 𝑦𝑛 out the most recent M samples 𝑥𝑛 … 𝑥𝑛−𝑀+1. In this condition the parameter M is called the filter length. For the arithmetic average, the mathematical explanation requires a division by the filter length M, which establishes that the average signal power of the filter output is equal as of the original input signal. Equation (5) defines this relation. Under the assumption above, the moving average filter sums up the two most recent samples and divides these by two, 𝑦𝑛 = (𝑥𝑛 + 𝑥𝑛−1 )/2. The result of the sum (𝑥𝑛 + 𝑥𝑛−1) for this 8 bit example is in the range of −256 … 254, because the input values are in the range of −128 … 127. Using fixed point arithmetic, the result of the sum requires 9 bit precision to display the 511 possible output values. Definitely there is a gain in precision of 1 bit compared to the 8 bit input values and with the fixed point arithmetic this gain can be preserved also after the following division, in this example by 2. This example can be established to any filter length M using fixed point arithmetic, with M being a positive integer number. For a random filter length, the gain in precision is the logarithm to the basis 2 of the filter length of the MAV filter. In case the filter length equals the power of two (2, 4, 8, 16…) the gain is an integer number (1, 2, 3, 4…). For all other MAV filter lengths, the gain in precision is a fractional number, and the fixed point arithmetic will cut the result to the hardware precision. In my analog to digital converter (AD9966) the hardware precision is 16 bit. The introduced error due to truncation is negligible. 𝑀−1
1 𝑦𝑛 = ∑ 𝑥𝑛−𝑖 𝑀
(5)
𝑖=0
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The section 2.3 shows the noise reduction in relation to the applied filter bandwidth. This section will show the increase in precision. The relationship between precision, filter bandwidth and basically the resolution is shown. The pulse response 𝑦𝑛 of a MAV filter is a discrete rectangular-function (see Figure 5). The transfer function (𝑓) in the frequency domain of this filter is the TDFT of this pulse response.
Figure 5: Pulse Response and Bandwidth of a Moving Average Filter with a Filter Length of M=5 (John G. Proakis, 2007) The pulse response given in equation (6) shows the magnitude of the TF |(𝑓)| in the frequency domain for a MAV filter. The frequency 𝑓 is increasing the sampling frequency 𝑓s and represented in the range from −0.5 to 0.5. The filter cut-off frequency 𝑓c, in which the signal is attenuated of -3 dB or 0.7 related to the pass band, depends on the M filter length. It is not possible to derive the 𝑓c in a closed form. |𝐻(𝑓)| =
sin(𝜋 ∗ 𝑀 ∗ 𝑓) 𝑀 ∗ sin(𝜋 ∗ 𝑓)
(6)
As shown in example of a moving average filter of the filter length of 5, the 3 dB bandwidth calculated as 0.09 ∙ 𝑓s, the gain in precision became 2.3 and the SQNR result is 7.4 dB according to equation (4). (Hellwig)
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2.3 Alternative oscilloscope architectures
2.3.1 FPGA Versus ASIC In the mid-1980s, Application-Specific Integrated Circuit (ASIC) companies brought a product to the electronics market: the built-to-order custom IC. By the 1980s, several companies were selling ASICs, and in the hot competition, the winning features were low cost, has a good capacity and high speed. After the Field Programmable Gate Arrays appeared, they poorly compared on all of these measures. It happens because the Application-Specific Integrated Circuit functionality was determined by custom mask manufacturing. ASIC customers should paid for those masks by non-recurring engineering (NRE) charge. They had no custom tooling and Field Programmable Gate Arrays reduced the up-front cost and risk of building custom digital logic. Producing one custom device that could be used a lot of customers, the FPGA vendor amortized the NRE costs over all customers, resulting in no non-recurring engineering charge for any one customer, while increasing the single unit chip cost for all. The up-front non-recurring engineering cost ensured that Programmable Gate Arrays were more cost effective than Application-Specific Integrated Circuit at some quantity (S.Trimberger, 1994). FPGA companies touted this in their ‘‘crossover point’’, the number of units that justified the higher non-recurring engineering spending of an ASIC. In Figure 6, the lines show the total cost for a number units purchased. An Application-Specific Integrated Circuit has an initial cost for the non-recurring engineering, and each unit adds its unit cost to the total. An Field Programmable Gate Arrays has no NRE charge, but each unit costs more than the functionally equivalent Application-Specific Integrated Circuit, hence the steeper line. The two lines meet at the crossover point. If you want fewer products then the FPGA solution is much cheaper; more than that number of units indicates the Application-Specific Integrated Circuit has lower overall cost.
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Figure 6: FPGA versus ASIC Crossover Point. Graph shows total cost versus number of units. (Trimberger, Three Ages of FPGAs: A Retrospective on the First Thirty Years of FPGA Technology, 2015) The disadvantage of the FPGA per-unit cost premium over ASIC diminished over time as NRE costs became a larger fraction of the total cost of ownership of Application-Specific Integrated Circuit. The dashed lines in Figure 6 show the total cost at some process node. Solid lines show a situation for the next process, increasing the cost of the NRE, but a lower cost per chip. Both FPGA and ASIC benefited from lower production costs, while the cost of ASIC NRE continues to rise, pushing the point of intersection above. In the end, the point of intersection has grown so high that for most customers, the number of units is no longer justified by the ICU. Custom Silicon justified only for very high performance or very high volume; the rest could use programmable solution According to Moore's Law (Moore, 1979), ultimately the ability to lead the movement in the FPGA to meet the requirements of ASIC, is a fundamental understanding of the earliest in the programmable logic business. Today the cost of the device is less than the driver in FPGA solution compared to the ASIC, than productivity, time to market, power consumption, I / O capacity and other features. A lot of ASIC customers using older process technology, reducing their cost NRE, but reducing the price advantage per chip. Not only is the FPGA to eliminate the upfront cost of masking and reduce storage costs, but also reduces the cost of design by eliminating whole classes of design problems. These problems have included designing transistor design level, testing the integrity of the signal crosstalk, I / O design and distribution of 16
the clock frequency. As important as low initial cost and a simple structure were the main FPGA benefits were instantly available and limited visibility of failure. Since FPGA can be reworked for a few minutes, FPGA design without any delay Time length for error. As a result, the check cannot be complete. '' Of Self-emulation ", colloquially known as the '' boot-on-and-try it'', can replace extensive simulation. Finally, there is a specific integrated circuit manufacturing risk: ASIC company made money only when the design of your customer went into production. In the 1980s, due to the changing demands in the process of development, product failures or outright errors of design, only about one-third of all the designs actually went into production. Two thirds of the projects lost money. Losses have been made not only to ASIC customers and ASIC suppliers whose NRE cost rarely cover their actual costs and never covers the cost of missed opportunities in their rapidly depreciating manufacturing facilities. On the other hand, programmable logic companies and customers can still money to a small volume, and a small mistake can be corrected quickly, without expensive masks making (Trimberger, March 2015).
2.3.2 Using FPGAs and the IEEE1451.0 for designing alternative embedded instruments The processing required to handle samples in digital instruments, in particular in an oscilloscope, may be implemented using several devices, such as microprocessor, microcontroller, FPAAs or FPGAs. Although the two last allow the reconfiguration of the hardware, FPAAs still have a limited number of analogue components in their core, does not provide the same flexibility as FPGAs, which contain a lot of digital blocks. Therefore, FPGAs are preferred for implementing a part or the entire architecture of one or more tools, because they are reconfigurable hardware using standard hardware description language (HDLs), and they can work several hardware units in parallel. This parallelism offered by FPGAs simplifies the implementation of specific numerical algorithms necessary for processing samples of a particular oscilloscope, and allows you to run more than one device in the same core. Although most of the processing performed in the digital form (for example, methods of interpolation filter implementations, etc.) that provides flexibility in the design of a particular instrument, they should provide interfaces to analog domain. Thus, analog-digital conversions are required, as well as power drivers’ interfaces to combine the circuit under text. For this purpose, the use of FPGA-based boards to accommodate the entire oscilloscope architecture, or any other 17
instrument, is an interesting solution. The core of the device can be integrated into an FPGA, while other issues, such as memories, the gain/attenuation of signals, among others, can be supported by the surrounding devices available on those boards, as shown in Figure 7.
Figure 7: Example of a typical FPGA-based board. Since FPGA kernel is reconfigurable, it is easy to change the functionality of a particular instrument by reconfiguring the hardware modules described in HDL. In contrast to the use of microprocessors or microcontrollers, whose programming depends of the assembly language provided by the manufacturer, FPGAs can use the same code HDL reconfigure various tools. Despite the Verilog and VHDL are standard HDLs, they do not guarantee the regular access to specific tools embedded in the FPGA. To this end, using the IEEE1451.0 Std. is a solution, as it it describes a specific architecture for managing the so-called intelligent transducers architecture can be taken to develop the integrated tool, and, in particular, an oscilloscope. Some specifications IEEE1451.0 Std. can be taken to identify and control the all oscilloscope behavior, namely the use of a TEDS and instruction set. The oscilloscope may also be implemented in FPGA-based board from Xilinx (starter kit XC3S700AN) for receiving signals from a CUT (a traditional emulation function generator), and using an internal ADC. Through an RS-232 connection, an oscilloscope connected to a computer that is running the interface developed in JAVA. This interface allows users to access and control all the functionalities of an oscilloscope.
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The oscilloscope may be implemented using sensors at the remote access by transducer channels (TC) within a transducer interface module (TIM) extends within the FPGA. TIM and the related TC operate using modes as defined in IEEE1451.0 Std. TIM may initialize or operate in active mode, while the TC can be operated in an initialization mode or inactive. Transactions between different operating modes are set by internal operations of an oscilloscope or with the commands issued by the users. The TIM is a basic unit of the oscilloscope which implemented in hardware blocks described in the Verilog HDL. As shown in Figure 8, it is divided into three main modules: i)
a Central Processing Unit (CPU);
ii)
a Transducer Channel (TC);
iii)
a Communication Module (CM).
iv)
a Circuit Under Test (CUT)
v)
a Transducer Interface Module (TIM);
vi)
a Transducer Electronic Data Sheet (TEDS).
Figure 8: Architecture of FPGA XC3S700AN oscilloscope. The CPU is the unit that handles all samples used to display in the computer interface the measured signal. As represented in Figure 9, after sampling the signal, the CPU defines the coupling mode (AC or DC) and implements interpolations and triggering methods to fill-in a data set with some amount of samples used to represent the signal. The number of samples can be tuned in order to get a good visual representation of the signal.
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Figure 9: Picture of how the FPGA oscilloscope processing signals. The coupling allows removing (or not) the continuous component of an analog signal by selecting the DC or AC modes. This functionality can be implemented by using a digital high pass band Finite Impulse Response (FIR) filter. This filter can be projected by using the Matlab software. (Ricardo Costa, February 2015)
2.4 A Practical Techniques in High-Speed PCB Layout Despite its critical nature of high-speed circuits, printed-circuit-board (PCB) layout is often one of the last steps in the design process. There are many aspects to the high-speed PCB layout; Volumes have been written on this topic. This section describes high-speed layout from a practical perspective. Here are the key areas that can have the greatest benefit in improving the performance scheme, reduces development time and minimizing the cost of changes of time. Themes and methods discussed herein, generally refers to the arrangement of most high-speed analog circuits. When the op amps or the ADC operates at high RF frequencies, circuit performance largely depends on the board layout. Circuit design of high-performance look good “on paper” can render mediocre performance when hampered by a careless or sloppy layout. Thinking about the future and to pay attention to important details throughout the layout process will help to ensure that the circuit is working as expected.
2.4.1 Power Supply Bypassing the power supply at the amplifier’s supply terminals to minimize noise is a critical aspect of the PCB design process for high-speed op-amps and any other high-speed circuit. There are two commonly used configurations for bypassing high-speed op-amps.
2.4.2 Rails to Ground Technique
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This method, which works best in most cases, uses multiple parallel capacitors connected from the op amp’s power pins directly to ground. As a rule, two parallel capacitors are sufficient, but some circuits may benefit from additional capacitors in parallel. Parallel various capacitor values helps ensure that the power terminal pins see low ac impedance over a wide frequency range. This is especially important at frequencies where the op-amp power supply rejection (PSR) is rolling off. The capacitors help to compensate for the reduction of amplifier’s PSR. Maintaining a low impedance path to ground for many decades of frequency will help ensure that unwanted noise doesn’t find its way into the op-amp. Figure 10 shows the benefits of multiple parallel capacitors. At lower frequencies, large capacitors provide a low impedance path to ground. Once those capacitors reach self-resonance, the capacitive quality diminishes and the capacitors become inductive. That is why it is important to use multiple capacitors when the frequency characteristic of the capacitor will be rolling off, the other becomes significant, thereby maintaining a low AC impedance for decades of frequency.
Figure 10: Changing Capacitor Impedance against Frequency. (Ardizzoni, 2005) Running directly at the op-amp’s power-supply pins the capacitor with the smallest value and smallest physical size to be placed on the same side of the board as the op-amp and as close as possible to the amplifier. GND side of the capacitor must be connected to the ground plane with minimal lead- or trace length. This ground connection should be as close to the load of the amplifier to minimize disturbances between the rails and ground. Figure 11 illustrates this technique.
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Figure 11: Parallel Capacitor Rails-to-Ground Bypassing. (Ardizzoni, 2005) This process should be repeated for the next higher capacitor value. A good place to start is with 0.01 µF for the smallest value, and a 2.2 µF (or higher electrolytic with low ESR) for the next capacitor. 0.01 µF capacitor in case size 0508 offers low inductance and excellent highfrequency performance.
2.4.3 Rail to Rail Technique An alternate configuration uses one or more bypass capacitors tied between the positive and negative supply rails of the op-amp. This method is commonly used when it is difficult to get all four capacitors in the circuit. A disadvantage of this approach is that the size of the capacitor case may become larger, so as the voltage across the capacitor is doubled as compared with the method of single-supply bypassing. The higher voltage requires a higher breakdown rating, which is reflected in a larger case size. This option, however, may offer improvements to both PSR and distortion performance. Since each circuit and layout is different; on the configuration, the number and value of capacitor are determined by the actual requirements of the scheme.
2.4.4 Parasitic Effect Parasitic negatively affects into the PCB and wreak havoc in the circuit. It is the hidden stray capacitors and inductors which infiltrate high-speed circuits. Parasitic include inductors formed by package leads and excessive trace lengths; pad-to-ground, pad-to-power-plane, and pad-to-trace capacitors; interactions with vias, and many more features. Figure 12(a) is a schematic view of a typical non inverting op-amp. If parasitic elements were to be taken into account, however, the same circuit will appear as shown in Figure 12(b).
22
Figure 12: Typical Op-amp Circuit, as Designed (a) and with Parasitics (b). (Ardizzoni, 2005) In high-speed circuits, it does not take much to affect the circuit performance. Sometimes just a few tenths of a pF is enough. Illustrative example: if only 1 pF of additional stray parasitic capacitance present at the inverting input, this can lead an almost 2 dB peaking in the frequency domain (Figure 13). If sufficient capacity is present, it may cause instability and oscillations.
Figure 13: Additional Peaking Caused by Parasitic Capacitance. (Ardizzoni, 2005)
23
A few basic formulas for calculating the size of the parasitic effects can come be useful looking for the sources of the parasitic problematic. Equation (7) is the formula for a parallelplate capacitor (also see Figure 14)
𝑘𝐴
𝐶 = 11.3𝑑 𝑝𝐹
(7)
C is the capacitance, A represents the area of the plate in 𝑐𝑚2 , k is the relative dielectric constant of board material, and d is the distance in centimeters between the plates.
Figure 14: Capacitance Between Two Plates. (Ardizzoni, 2005)
Strip inductance is another parasitic to be considered, as a result of the excessive trace length and lack of ground plate. Equation (8) shows the formula for trace inductance. See Figure 15. 2𝐿
𝐼𝑛𝑑𝑢𝑐𝑡𝑎𝑛𝑐𝑒 = 0.0002𝐿 [𝑙𝑛 (𝑊+𝐻) + 0.2235 (
𝑊+𝐻 𝐿
) + 0.5] 𝜇𝐻
(8)
Here W- trace width, L is the length of the trace, and H is the trace thickness. All measurements are in millimeters.
Figure 15: Inductance of a Trace Length. (Ardizzoni, 2005) The oscillation in Figure 16 shows the effect of path trace length of 2.54-cm at the noninverting input of a high speed op-amp. The equivalent parasitic inductance is 29 nH, enough to cause a sustained low-level oscillation that persists throughout the period of the transient response. The figure also shows how using a ground plane mitigates the impact of parasitic inductance.(Ardizzoni, 2005)
24
Figure 16: Pulse Response with, and Without Ground Plane.
2.5 Challenges of High-Speed DSP Design Modern digital signal processors (DSPs) typically operate at 1GHz, the internal clock rate transmit and receive signals to and from external devices operate at rates more than 200MHz. These fast switching signals generate a significant amount of noise and radiation, which reduces performance of the system and creates electromagnetic interference (EMI) problems, which make it difficult to pass the tests required to obtain certification from the Federal Communication Commission (FCC). Good design of the system requires a high-speed reliable power sources with low switching noise and dynamic loading conditions, minimal crosstalk between the high speed signals traces, high and low frequency isolation techniques and good signal integrity with minimal transmission line effects.
2.5.1 General Challenges Since the level of performance of a DSP and clock frequencies continue to increase rapidly, managing noise and radiation becomes an increasingly important issue. In Gigahertz world, lines carrying signals serve as transmission lines, which may generate signal reflections that cause distortion. Furthermore, since the data are packed into smaller and smaller time cycles, the resulting short signal pulses are more susceptible to interference. The risk is especially great in working with audio and video systems, where the noise can degrade performances thin, which 25
usually do not have any impact on discrete data. The growth of the power and performance of modern DSP systems also creates challenges in achieving electromagnetic compatibility (EMC) compliance. At high frequencies, footprints in the act on the circuit board, as a mono-pole or loop antennas that produce emissions that are often difficult to meet the requirements in FCC Class A and Class B. The heat sinks and ventilation, which may be required to address the thermal challenges of high performance designs, can further exacerbate EMC problems. The trend towards integrating wireless capabilities creates further difficulties as intentional radiators are designed into the system. These trends make it necessary to revise the traditional design process of DSP. In the traditional approach, engineers focus on the functional and performance aspects of the project. Noise and radiation are considered only towards the later stages of the design process if and when prototype testing reveals problems. But today, noise problems are becoming more common and more than 70% of new designs fail the first-time EMC testing. As a result, it became necessary to begin addressing these issues from the outset of the design process. Investing a small amount of time when using a low-noise and low-radiation design techniques from the very beginning of the development cycle will generate a high returns by minimizing the cost of redesign on the later stages and the delay in the product ship date. (SPRU889., May 2005)
Figure 17: Typical DSP System. (Texas Instruments: SPRU889, 2005) Typical DSP systems such as shown in Figure 17 consist of plurality of external devices, such as audio CODEC, video, LCD, wireless communication (Bluetooth and IEEE 802.11), Ethernet controller, USB, power supply, generators, storage, memory and other supporting circuitries. Each of these components can either be either a generator of noise depend on the interference generated by adjacent components. Therefore, using a good high-speed design 26
techniques are required in order to minimize both the components and systems associated with the
noise
and
ensure
the
success
of
the
system
design.
Figure 18: A Typical Noise Path. (SPRU889., May 2005) The relationship between the noise source and the noise of the victim causes electrical noise. Figure 18 shows a typical path noise. The source of the noise, as a rule, quickly switching signal and the victim noise is the component carrying the signal whose performance is impacted by the noise. Coupling takes place via the parasitic capacitances and mutual inductances of the neighboring signals and circuits. Electromagnetic coupling occurs when the signal traces become effective antennas that radiate and generate interferences in adjacent circuitries. There are many mechanisms by which noise may be generated in an electronic system. Clock circuits tend to have the highest switching rates and, therefore, the main source of noise. Invalid terminated signal lines can generate reflections and signal distortion. Ground plane resistance due to skin effect and proximity effect can lead to significant ground noise. Noise may also be formed within the semiconductors itself (Texas Instruments: SPRU889, 2005):
Thermal noise is also known as Johnson noise, thermal noise is present in all resistors and is caused by random thermal motion of electrons. Thermal noise can be addressed in audio and video designs, by keeping resistance as low as possible to improve the signalto-noise ratio.
Shot noise it is a shot noise which caused by charges moving randomly across the gate in diodes and transistors. This noise is inversely proportional to the DC current flowing through the diode or transistor so higher DC operating current increases the signal-tonoise ratio. Shot noise can become an important factor when the DSP system includes many analog discrete devices on the signal paths, for example discrete video and audio amplifiers.
Flicker noise is also known as 1/f noise; flicker noise is present in all active devices. It is caused by traps where charge barriers are captured and released randomly, causing random current fluctuations. Flicker noise is a factor of semiconductor process technologies so DSP system design cannot reduce it at the source but must rather focus on mitigating its effects. 27
Burst Noise and Avalanche Noise. The burst noise, also known as “popcorn” noise, is caused by ion contamination. Avalanche Noise is found in devices such as zener diodes that operate in reverse breakdown mode. Both of these types of noise are again related to the semiconductor process technology rather than system design techniques.
2.5.2 Transmission Line (TL) Effects Transmission line (TL) effects are one of the most common causes of noise problems in high-speed DSP systems. When do traces become TLs and how do TLs affect the system performance? The rule-of-thumb is that traces become TLs when the signals on those traces have a rise time (Tr) is less than twice the propagation delay (Tp). For example, if a delay from the source to the load is 2 nS, any of the signals with a rise time less than 4 nS becomes a TL. In this case the termination is required to ensure a minimal overshoots and undershoots caused by reflections. Excessive TL reflections can cause electromagnetic interference and random logic or DSP false-triggering. As a result of these effects, the design cannot get the FCC certification and be fully operational in all operating conditions, such as high temperatures or over-voltage conditions. There are two types of TL, lossless and lossy. The ideal lossless transmission line has a zero resistance while a lossy transmission line has a small series resistance, which distorts and attenuates the propagating signals. In practice, all TLs are lossy. (SPRU889., May 2005)
2.5.3 Transmission Line Theory A lossless propagation TL formed by on a trace, which consists of series parasitic inductors and parallel capacitors, as shown in Figure 19.
Figure 19: Lossless Transmission Line Model.
28
The speed of the signal, Vp, is dependent on properties such as the impedance, Zo, defined as an initial voltage V+, divided by the initial current I+ at a time. Equations 9 and 10 for Vp and Zo are: 𝑉𝑝 =
1
(9)
√𝐿𝐶 𝐿
𝑍𝑜 = √𝐶
(10)
where L is inductance per unit length and C is capacitance per unit length. Another important feature of transmission line is the propagation delay, Td. Equation 11 for Td is: 1
𝑇𝑑 = 𝑉𝑝 = √𝐿𝐶
(11)
The source and load TL reflections depend on how well the output impedance and the load impedance, respectively, with impedance matched. Load reflection factors and source reflection coefficients shown in the equations 12 and 13: 𝑍𝑠−𝑍𝑜
𝑆𝑜𝑢𝑟𝑐𝑒 𝑟𝑒𝑓𝑙𝑒𝑐𝑡𝑖𝑜𝑛 = 𝑍𝑠+𝑍𝑜 𝑍𝑙−𝑍𝑜
𝐿𝑜𝑎𝑑 𝑟𝑒𝑓𝑙𝑒𝑐𝑡𝑖𝑜𝑛𝑠 = 𝑍𝑙+𝑍𝑜
(12) (13)
where Zs and ZƖ are source impedance and load impedance, respectively. As an example, Figure 20 shows the waveforms of the load for both non-terminated and terminated circuits. As shown in the previous example, the interrupted TL has a zero reflection, and consequently, no ringing occurs in the waveform as shown on the top of Figure 20. The problem is that in high-speed digital design by adding a 50-ohm resistor to ground no load is not practical, since it requires a buffer to drive too much current in each line. In this case, the current will be 3.3V / 50 ohm = 66mA. The method, known as parallel termination can be used to solve this problem. It consists of adding a small capacitor in series with the load resistance to DC block. RC combination must be much less than the rise and fall of the signal propagating on the trace.
29
Figure 20: Waveforms for Terminated and Unterminated Circuits. Figure 21 shows a parallel termination method. This technique can be used in the application in which one output controls multiple loads as long as the traces of the loads called L2 are a lot shorter than the main trace L1. To complete the parallel termination method, it is necessary to calculate the maximum value for L2 in accordance with equation 14 below assuming the main trace L1 and the rise time Tr are known. 𝑇𝑟
L2,max= 𝐿110
(14)
Figure 21: Parallel Termination Method. (Texas Instruments: SPRU889, 2005)
30
2.5.4 Practical Considerations of Transmission Line Theory In general, high-speed DSP systems consist of a plurality of CMOS devices, where the input impedance is very high, typically in MOhm, and an input capacitance is relatively small, less than 20 pF. In this case, with no load termination, TL looks like a transmission line with a capacitive load, rather than an open circuit. Capacitive load helps to reduce the rise time and allows designers to use only a series termination at the source. This approach is very common in high-speed systems.
Figure 22: Practical Model of TL. In Figure 22, the voltage across the load is slowly charged up to the maximum amplitude of the synchronization signal. Initially the load looks like a short circuit. After the capacitor is fully charged, the load becomes open circuit. The source resistor Zs controls the timing of the rise and fall. Resistance above outputs supply slower rise time. The load voltage at any time, t, is greater than the propagation delay. Time can be calculated using the following equation 15: 𝑉𝑙 = 𝑉𝑐𝑙𝑘(1 − 𝑒 −(𝑡−𝑇𝑑)/𝜏 )
(15)
where t is some instant of time longer than the propagation delay and τ = Cl*Zo , where Cl and Zo are the load capacitor and characteristic impedance, respectively. (Texas Instruments: SPRU889, 2005)
2.5.5 Ground Grid Effects on TL The previous examples were based on a model where a signal trace is on top of a ground plane known as a microstrip model. Other methods such as a ground grid, are also commonly 31
used. The following example demonstrates the effects of ground grid. In this configuration, designers need to understand the current flows and their impact on the impedance. Figure 23 shows an example of using a ground grid, rather than of ground plane for the PCB. As shown in figure 23, the current path is not immediately in the trace signal so there is a large loop current return, which allows higher inductance and lower capacitance per unit length. In this case, the characteristic impedance is higher than if a continuous ground plane was used.
Figure 23: Current Return Paths of Ground Grid. (SPRU889., May 2005) Figure 24 also shows another example of a ground grid, where the signal is routed diagonally. As shown in this figure, the return current has pass by a zigzag pattern back to the source and produces a large current return loop, which allows higher inductance and a smaller capacitance per unit length. In this case, the characteristic impedance is higher than using a continuous ground plane and is higher than in the case where a signal is routed in parallel with the ground grid as shown in Figure 24.
32
Figure 24: Current Return Paths for Diagonal Signal Trace. (SPRU889., May 2005) So, if ground grid is design as required, the best approach is to route the high speed signals directly on top of the grids and parallel to the grid to provide the smallest return loop current. This lowers the characteristic impedance at a level equivalent to the impedance of the continuous ground plane. It is very difficult to accomplish since complex board has a lot of high speed traces. Thus, a continuous ground plane is still the best way to keep characteristic impedance and EMI at low level. (Texas Instruments: SPRU889, 2005).
2.6 Oscilloscope probes Measuring an electrical signal inevitably affects that signal. This applies to all measurements, including the display of an oscilloscope waveform. Affecting the signal cannot be totally
eliminated,
but
it
can
be
minimized
sufficiently
that
the
effect
is
unimportant. Then the measured result is a sufficiently accurate representation of the real signal. It is therefore critical for the measurement engineer to understand the effect of the instrument on the signal. A x10 scope probe is useful in several applications:
To reduce loading effect on the circuit under test
To compensate for the effect of test cable capacitance
To permit the measurement of large voltages 33
2.6.1 Loading Effect and the Oscilloscope The input circuit of a general-purpose oscilloscope consists typically of a 1MΩ resistor in parallel with a small capacitance, perhaps 30pF. At low frequencies, the capacitance appears as an open circuit, so the input resistance is on its own. To make an accurate measurement, we must ensure that the source resistance (the Thevenin resistance of the circuit) is much less than 1MΩ. For example, to obtain 1% accuracy, the source resistance must not exceed 10kΩ.
2.6.2 Probe Compensation The compensation capacitance (shown in Figure 25 below) of the ×10 probe must be adjusted to suit the input capacitance of the oscilloscope.
Figure 25: 10x Probe Circuit This requires adjusting the compensation each time the probe is moved to a different scope. To compensate the probe, it is driven with a square wave. The scope display can appear as one of the three waveforms represented in Figure 26.
34
Figure 26: Probe Compensation Adjustment The upper display is under-compensated; the compensation capacitance is too small. In the lower display, it is overcompensated, the compensation capacitance is too large. The central waveform display is the right version. These square waves indicate the response of the probe over a range of frequencies. The upper waveform, with its undershoot, corresponds to a depressed highfrequency response. The lower waveform corresponds to an emphasized high-frequency response. The central waveform corresponds to a flat frequency response (E.McAbel, 1969).
2.7 Calibration System
A Fast Pulse Calibration System describes oscilloscope with high bandwidth using a pulse signals. The fast pulse oscilloscope calibration system (FPOCS) should be used to determine the step response parameters for digitizing oscilloscopes having a bandwidth of about 20GHz. The system can provide traceability of measurement standards, supported by the U.S. National Institute of Standards and Technology (NIST). It consists of fast electrical step generation hardware, personal computer (PC) and software, and a reference signal, i.e. a data file containing the generator output step signal. The reference signal is obtained by preliminary measurement NIST oscillator (calibration step signal). When the FPOCS is in use, the calibration step signal is applied to the devise under test, which is one of an oscilloscope sampling channel. The measured step signal is corrected for time base errors, and then the reference signal is deconvolved from it. Results impulse step and frequency meets estimates, and their associated parameters (e.g., transition duration, transition amplitude, -3db bandwidth) and uncertainties (John P.Deyst, 1998).
35
Fast pulse test signals are often used to characterize the dynamic behavior in the timedomain oscilloscopes, digitizers, and other data acquisition devices (Nicolson, Dec.1968), (W.L.Gans, Dec 1990). If the test signal is applied close to the ideal step, then certain performance parameters of an oscilloscope can be obtained from its response to this signal. These parameters include transition duration, overshoot, settling, etc. (IEEE Standart 1057-1994, Dec. 1994). Step response may also be used to determine the oscilloscope frequency response and the associated frequency- domain parameters: bandwidth, gain flatness, etc (Flach, June 1987).
2.7.1 Step Response Calibration Architecture The Fast Pulse Calibration System generation hardware includes a precision step generator, trigger generator, a delay network, an attenuator, and cables. The components have been selected to meet the triggering requirements of a precision step generator, to ensure traceability to standards at National Institute of Standards and Technology. It usually sent to National Institute of Standards and Technology periodically for measurements. (SP250, 1998 edition) NIST will return the equipment to the customer with a reference signal (a data file containing the NIST discrete-time estimate of the calibration step signal) Figure 27 below represented shows the installation of the Fast Pulse Calibration System hardware setup for response tests.
Figure 27: Hardware Representation for Step Response Calibration Technique. (SP250, 1998 edition)
The trigger generator produces a square wave having duration of 150ps and variable repetition rate and duty cycle. The repetition rate is used in this figure is 100 kHz, with 50% duty cycle. 36
The trigger generator output is connected to the delay line input. The delay line has two outputs; One output is connected through an attenuator, to the trigger input of the oscilloscope under test. The attenuator is necessary to reduce the amplitude of the signal within the range allowable for the oscilloscope trigger input. Another delay line output, which is delayed by 56 ns relative to the first output, connected to the trigger input of precision step generator. The generator produces precise step calibration signal that is 0.25 V amplitude, 10%-90% transition duration of about 15 ps, the low short-term jitter (𝛿 < 1.2 𝑝𝑠) and good settling and stability characteristics. The step generator has a remote head attached by an umbilical to its main unit. Remote head and umbilical allow the calibration step signal fed directly to the input of the oscilloscope (sampling channel) during the test, with no intervening cables, which degrade the signal (John P.Deyst, 1998).
2.8 The Main Board In order to implement an oscilloscope in practice I chose Embedded Artists' LPC4088 QuickStart prototyping Board which is due to its functionality has a wide range of applications. It uses ARM Cortex-M4 rapid microprocessor and standard through hole DIP package (44-pin), targeted at high-performance as well as low-power applications. It also has communication interfaces, large on-board memories and LCD controller enables graphical user interface applications (See the Figure 28 below).
Figure 28: Embedded Artists' LPC4088 QuickStart Prototyping Board. Here are some features:
NXP's Cortex-M4 processor running at up to 120 MHz
8 MB Quad SPI and 512 kB program flash
32 MB SDRAM, 96 kB SRAM, 4 kB on-chip E²PROM data memory 37
USB Host (A type) and Device (micro-B) interfaces
CMSIS-DAP Interface On-board (debug interface functions)
2.8.1 The Main Core on the Board The central core of the control of all processes on the board is LPC4088FET208. It is a mid-range 32-bit Microcontroller (MCU) based on ARM Cortex-M4. The ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals, and includes an internal pre fetch unit that supports speculative branching. The ARM Cortex-M4 supports single-cycle digital signal processing and SIMD instructions. A hardware floating-point processor is integrated in the core for several versions of the part. The LPC4088 also adds a specialized flash memory accelerator to accomplish optimal performance when executing code from flash. The LPC4088 is targeted to operate at up to 120 MHz CPU frequency. The peripheral complement of the LPC408x includes up to 512 kB of flash program memory, up to 96 kB of SRAM data memory, up to 4032 byte of EEPROM data memory, External Memory controller (EMC), LCD, Ethernet, USB Device/Host/OTG, an SPI Flash Interface (SPIFI), a General Purpose DMA controller, five UARTs, three SSP controllers, three I2C-bus interfaces, a Quadrature Encoder Interface, four general purpose timers, two general purpose PWMs with six outputs each and one motor control PWM, an ultra-low power RTC with separate battery supply and event recorder, a windowed watchdog timer, a CRC calculation engine and up to 165 general purpose I/O pins. The analog peripherals include one eight-channel 12-bit ADC, two analog comparators, and a DAC.
2.8.2 32-bit Multiply-Accumulate (MAC) Unit The 32-bit hardware multiply-accumulate (MAC) unit added in the Cortex-M4 is capable of accomplishing an operation of up to 32×32+64->64 or two operations of 16×16 in a signal cycle. This high-performance unit makes digital signal processing more efficient and greatly reduces the consumption of CPU resources. The 32-bit multiply-accumulate (MAC) unit has three main features: 38
Wide range of multiply-accumulate instructions
Choice of 16 or 32 bit multiply and 32 or 64 bit accumulate
All instructions execute in a single cycle
2.8.3 Floating Point Unit (FPU) The FPU is an optional unit of the Cortex-M4. Manufacturers can make their own decisions on the availability of this unit according to their different requirements. The FPU fully supports single-precision add, subtract, multiply, divide, multiply and accumulate, and square root operations. It also provides conversions between fixed-point and floating-point data formats, and floating-point constant instructions. The FPU has four main features:
FP extension registers that software can view as either 32 single-precision or 16 double word registers
Single-precision floating-point arithmetic
Conversions among integer, single-precision floating-point, and half-precision (16-bit) floating point formats
Data transfers of single-precision and double word registers
2.8.4 Comparisons between Cortex-M3 and Cortex-M4 Table 1 shows the list of the main differences between Cortex-M3 and Cortex-M4.
Architecture
Cortex-M3
Cortex-M4
ARMv7-M
(Harvard ARMv7-M
(Harvard
architecture)
architecture)
ISA Support
Thumb/Thumb-2
Thumb/Thumb-2
DSP Extensions
NA
Single cycle 16,32-bit MAC Single cycle dual 16-bit MAC 8,16-bit SIMD arithmetic Hardware
Divide
(2-12
Cycles)
39
Optional Floating
NA
Single precision floating point unit
Point Unit
IEEE 754 compliant Pipeline
3-stage and branch speculation 3-stage and branch speculation
Dhrystone
1.25 DMIPS/MHz
Memory
Optional 8 region MPU with Optional 8 region MPU with
Protection
sub regions and background sub regions and background
1.25 DMIPS/MHz
region
region
Non-maskable
Interrupts
Interrupt Non-maskable
Interrupt
(NMI) + 1 to 240 physical (NMI) + 1 to 240 physical interrupts
interrupts
Interrupt Latency
12 cycles
12 cycles
Interrupt Priority
8 to 256 priority levels
8 to 256 priority levels
Levels Optional JTAG & Serial-Wire Optional JTAG & Serial-Wire
Debug
Debug
Ports.
Breakpoints
Up and
to
8 Debug
Ports.
Up
4 Breakpoints
Watchpoints.
to
and
8 4
Watchpoints.
Table 1: The Main Differences between the Cortex-M3 and Cortex-M4.
2.8.5 SPI interface. Serial peripheral interface, similar to I2C, is a 4-wire synchronous serial data protocol, which is suitable for use in portable device platform devices, but it is not as common used as I2C. Serial peripheral interface is generally in form of 4-wire, but sometimes 3-wire too. The full names for the standard signal are as follows:
SCLK - Serial Clock (output from the control terminal)
MOSI - Master Output Slave Input (output from the control side)
MISO - Master Input Slave Output t (output from the terminal been controlled)
SS - Slave Select (Low Level action, output from the control terminal)
Users can control the SPI Slave through the SPI Master, wiring diagram is in Figure 29. 40
SPI MASTER
SCLK
SCLK
MOSI
MOSI
MISO
MISO
SS
SPI SLAVE
SS
Figure29: SPI Protocol Block-Diagram.
The main interface which I will use to transfer data is SPI. It allows me fast transfer data from my external ADC in further investigation.
2.9 Software 2.9.1 MBED Online Development Platform MBED is the industry's first online platform for fast, low-risk rapid prototyping of microcontroller-based systems built to create software for 8/16-bit microcontrollers and also 32bit microcontrollers. The MBED tools enable users who can get started with MBED tools very fast, by plugging in an MBED microcontroller, going to the mbed.org website to sign up, and downloading and running binary code which is similar to saving to a USB Flash Drive. To launch the browser-based compiler, should be created a new template project, and click ‘compile’ to build and download the binary. The tools are in ‘the cloud’, there is nothing to configure or install, and everything works on Windows, Mac or Linux. For developers currently using proprietary 8/16-bit microcontrollers, discrete logic, or even those new to the industry, MBED allows to work with 32-bit microcontrollers. The MBED C/C++ Libraries provide high-level interfaces to microcontroller peripherals, enabling a clean, compact, API-driven approach to coding. The combination gives immediate connectivity to peripherals and modules for prototyping and iteration of microcontroller-based system designs.
41
Engineers new to embedded applications can use MBED to experiment and test product ideas that could benefit from advanced microcontrollers. Experienced engineers can be more productive and adventurous in the proof-of-concept stages of development. Education, Enthusiasts and Inventors can use MBED as an accessible way to experiment with the application of microcontrollers without worrying about implementation details. As a result, the MBED tools will help a diverse audience exploit the opportunities presented by advanced microcontrollers when introduced to their own area of expertise.
2.9.2 Keil MicroVision - ARM Development Tools Keil MicroVision is free Windows-based software (with code uploading limitations) which solves many of the pain points for an embedded program developer. The Micro-Vision development platform combines a robust editor, project manager, and makes facility. MicroVision integrates all tools including the C compiler, macro assembler, linker/locator, and HEX file generator. It helps expedite the development process of embedded applications by providing the following:
Full-featured source code editor
Device database for configuring the development tool setting (Legacy support)
Project manager for creating and maintaining your projects
Integrated make facility for assembling, compiling, and linking your embedded applications
Dialogs for all development tool settings
True integrated source-level Debugger with high-speed CPU and peripheral simulator
Advanced GDI interface for software debugging in the target hardware and for connection to Keil ULINK
Flash programming utility for downloading the application program into Flash ROM
Links to development tools manuals, device datasheets & user’s guides.
Creating *.hex and *.axf file
Due to the fact that the free version has a limitation by uploading up to 32 kilobytes of code, I probably will in the future use specialized IDE which is free and also compatible with all NXP processors. 42
2.9.3 LPCXpresso – Development Tools from NXP Microcontrollers LPCXpresso is the name of a low cost development platform for the ARM-based LPC family of microcontrollers from NXP. The platform supports the ARM-based LPC microcontrollers and includes a simplified Eclipse-based IDE and a low-cost target board combined with a JTAG debugs Probe. LPCXpresso provides all of the software and hardware required to evaluate NXP microcontrollers and develop complete applications using the user’s own production hardware. The LPCXpresso IDE is a customized version of Eclipse CDT. Eclipse was designed as an integration platform which meant that plug-ins can be used to extend the capabilities of the IDE. The IDE can build an executable of any size and has a download limit of 128K bytes which is a great solution because it allows you to upload succinct examples and experiment with them. Also because the LPCXpresso IDE is Eclipse it includes all of the advanced programming environment features of Eclipse such as syntax highlighting, code folding, and click-through links to definitions and declarations. The single perspective greatly simplifies the Eclipse environment and enhances the entire LPCXpresso experience.
43
3.0 Methodology In this section represented the main information about the project design, major parts of which the project is assembled, comparative tables for different types of processors as well as the design characteristics of the analog circuit power and operation of the basic system components.
Block diagram of the project is shown in Figure 30 and consists of the following key components: 1. LPC4088 Experiment Base Board. The main board includes LSD panel with the main processor as well as provides access to a variety of protocols (described in more detail below). 2. LPC4088 Quick Start Board. The core of the whole system which can handle received via different protocols information, process it and display on the screen (or on a different output device) 3. Analogue block. It contains a circuit which eliminates any composes DC voltage. There also used a voltage bias circuit for correct representation AC voltage on the device screen. 4. FG-100 DDS Function Generator. The output device which can generate different types of signals in the range from 1 Hz's to 500 kHz with different amplitude values. 5. Alternative power supply block. Circuits which combining a voltage cascade system for the correct functioning of the device, as well as watching the battery charge level and outputting information on used power mode at the front panel of the device.
44
Figure 30: Hardware Block-Diagram. 45
3.1 Hardware construction The LPC4088 Experiment Base Board, which together with the LPC4088 Quick Start Board forms the LPC4088 Experiment Bundle (See Figure 31 below). This Base Board adds several expansion connectors to the LPC4088 Quick Start Board and makes it easy to connect displays to the board.
Figure 31: LPC4088 Experiment Bundle Construction. Embedded Artists’ LPC4088 Experiment Base Board let us get up-and-running quickly with the MBED-platform and Cortex-M4 programming in general. The features of the board are: 1. Interfaces and Connectors:
Dual 22-pos headers and 61-pos FPC/FFC connector for the LPC4088 QuickStart Board
ArduinoTM compatible expansion connectors
14-pos connector with UART/I2C/SPI/GPIO pins
micro-SD interface
Connector to 1.8" TFT LCD 128x160 pixels
Connector for character LCD (with standard 16-pin interface)
2. Audio Interface: 46
WM8731 Audio codec, with microphone input, Line in, Line out and Headphone out
3. LCD Interface:
40-pos FPC connector for 4.3" and 5" LCD interfaces
Touch screen interface controller based on AR1021
4. Other:
UART interfaces for UART0/UART3
Shift register on SPI bus controlling 8 LEDs
5-key Joystick
MMA7455 3-axis accelerometer (I2C connected)
LM75 temperature sensor (I2C connected)
5. Power:
Power supply, either via USB or external +5V DC (2.1mm jack)
All features of the board are shown in Figure 32.
. Figure 32: LPC4088 Experiment Base Board Overview 47
After the bundle was constructed the HDK USB interface should be connected to a PC. A microB to A USB cable is needed for this. The HDK USB interface is located on the bottom side of the board under the reset pushbutton, it shown in Figure 33 below.
Figure 33: LPC4088 QuickStart Board HDK USB Interface After the connection was established three LEDs (blue, green, red) will light and after a few seconds of activity, the PC will recognize the LPC4088 Quick Start Board HDK interface as a standard USB drive. On the next an account should be registered on the official site mbed.org. An account gives an access to the online compiler. After that LPC 4088 Quick Start Board should be added to account and access will be available to all MBED programs and libraries. To download an application into the LPC 4088 compiler creates a *.bin-file which then can be uploaded into “MBED” USB drive. When just need press the Reset push button and program will start to execute. A running pattern on the four user LEDs became visible. 48
The three HDK LEDs have the following meaning:
Red HDK LED: Flashes when there is activity on the HDK USB drive (when writing a binary file).
Green HDK LED: Flashes when the CMSIS DAP debug interface is used.
Blue HDK LED: Flashes when there is serial communication over the virtual USB serial COM channel.
3.2 Display module The board has several different ways to add display functionality. This chapter presents the way to connect a display to the board. The LPC4088 Experiment Bundle has built-in support for TFT color LCDs. The display can easily be mounted on the bottom side of the board (See LCD Pin connectors in the Table 2). The build-in support routed the RGB-pixel data signals that are available on the display expansion connector on the LPC4088 Quick Start Board to the 40-pos LCD connector, which is directly, connects to an LCD. On the LPC4088 Experiment Bundle 16-bit color depth is implemented for better performance. In Figure 34 shown display module. LCD input signals shown in Table 2:
Signal
Function
HSYNC
Sets the next active pixel to be first pixel on the next line.
VSYNC
Resets the internal circuitry so that the next active pixel will be in the upper left corner
DCLK
Latches the RGB data
Data(24 lines or 3x8bit RGB)
Actual pixel data equally split between red, green, blue
DEN
Indicates valid pixel data
Table 2: LCD Input Signal Definitions
49
Figure 34: Embedded Artists Display Module Here are some 4.3 inch TFT LCD specifications:
9MHz pixel clock.
4.3 inch TFT
480x272 pixels
65K colors (display supports more, but LPC4088 Experiment base board supports 16-bit color depth)
3.2.1 Mechanics of an LCD Panel The LCD panel includes a matrix of pixels (picture elements), divided by the red, green, and blue "sub-pixels". Each sub-pixel is controlled by a small transistor. LCD panel have internal row and column drivers, as well as DRAM. A row is selected by the row driver, whereas the column driver sequences through each of the columns. After each column has been written, the row driver selects the next row and the process repeats. The VSYNC signal resets both row and column drivers to the upper left pixel. The HSYNC causes the row driver to step to the new row. 50
Clock control sequences the column driver through each of the pixels, with each clock edge latching data values for red, green, and blue sub-pixels. These values drive a form of D/A converter to store electrical charge in the capacitor of each sub-pixel, which controls the drive of the transistor; This in turn adjust the brightness of the sub-pixel. A red-green-blue color mask used to filter the light from each sub-pixel to form the corresponding color.
Figure 35: Direct Color Addressing Like a DRAM, an LCD panel must be constantly refreshed or the image will fade. 4.3 inch TFT LCD panels work when refreshed around 60 Hz. The image data is usually held in a section of main memory or a Frame Buffer. Each location in the Frame Buffer corresponds to a pixel on the LCD. The value in the location determines the color displayed for that pixel. See Figure 35. The size of the Frame Buffer depends on two things: the number of locations needed, and the size of each location. I opted for the 4’3-inch display because basically it allows you to implement all the basic parameters required for display as well as to save LPC4088 RAM resources an increase LCD refresh speed. The total number of locations needed is determined by the panel resolution. The resolution of my panel is 480 × 272 pixels. Therefore 480 × 272 = 130 560 memory locations will be needed in the Frame Buffer (one for each pixel). 51
It also supports 24-bit systems but that would double to load on the external memory bus since each pixel is stored as 32-bits (instead of 16-bits). Connections with LCD provide 40 position LCD connector. It uses FPC connector to transfer data from the main board to LCD. This protocol also widely used in different types PC monitors. The FPC connection represented in the Figure 36 below:
Figure 36: 40-pos LCD FPC Connector between the Main Board and Experiment Board Once all connections are on the back side of the board, we can observe the on-board display (See Figure 37).
Figure 37: Mounted LCD Display
52
3.4 Independent Power Supply Circuit
Figure 38: Independent Power Supply Circuit
53
3.4.1 TP4056 Lithium Polymer Battery Charging Module A 3.7 Volt Lithium Polymer battery is 100% charged when its terminal voltage reaches 4.2 Volts, and selecting the correct charge current is also very crucial when charging battery packs, because over charging will ruin the battery, possibly cause it to catch fire. As Lithium Polymer batteries require special charging algorithm. A single-chip solutions based on the TP4056 chip is provided in this project for Lithium Polymer battery charging. The TP4056 IC is a constant current/constant voltage linear charger for single cell Lithium Polymer batteries. The TP4056 can work from USB power supply voltage and generate stable linear charging. Other features include current monitor, under voltage lockout, automatic recharge, and two status pin (which were resoldered into the front panel) to indicate charge termination and the presence of an input voltage. But the circuit is works only to control battery charge. In case LPC4088 required 5V voltage supply, so I have to use some DC to DC boost converter. Ideally these circuits should be shielded to prevent noise distortions).
3.4.2 MT3608 DC to DC Boost Converter This converter is based on the MT3608 chip. It is a constant frequency chip current mode. Stepup converter intended for small, low power applications. The MT3608 switches at 1.2MHz and allows the use tiny components. Internal soft-start results in small start-up current and increases battery life. The MT3608 has an automatic shifting to pulse frequency modulation mode at light loads. It also includes low voltage lockout, and current limiting protection which ideal for Li-Pol battery, also it has the thermal overload protection to prevent damage in the event of an output overload. It is maybe not ideal for oscilloscope design, but for my experimental model it is should be enough.
4.0 Software Implementation The software was written in ‘C++’ using NXP LPCXpresso IDE. 54
Because of the large amount of code, a modular approach was adopted where related functions are grouped together. This results in several independent source files each handling a different part of the program. Each source file has a corresponding header file that contains all the necessary declarations so that functions in the source file can be called from other parts of the program. The following source files make up the software and represented at following appendixes:
Software Flowchart (Appendix A)
Main.cpp (Appendix B)
Display.h (Appendix C)
Display.cpp (Appendix D)
EaLcdBoardGPIO.cpp (Appendix E)
EaLcdBoardGPIO.h (Appendix F)
4.1 Main.cpp The program contains the main() function, which is called Cortex M4 controller (controller has his own microcode which has to be executed). Next will be described an algorithm how the main() function works: 1. The program initializes the display. 2. The function creates a buffer array initialization with initial values (0) and structure array samples. 3. On the next stage the function draw appearances to fill the LCD screen. 4. Next stage is executing the main program loop (inside the loop program zero out max and min variables). 5. After that the function write into variable “freezed” value from “DigitalIn” class instance which was set to get voltage values from pin 31. 6. On this stage condition should be performed (condition “freezed” = false). If the “freezed” is false: 7. Start executing “clear_screen”(should be true) condition where program clear oscilloscope workspace.(“clear_screen” became “false”) else program clear the DFT trace. 8. After that buffer filled in values from “AnalogIn” class instance which set to read voltage values from pin 20. 55
9. On the next stage program offset buffer values to represent on the screen two semi waves of our signal. 10. Next min and max voltage values will be calculated. 11. After that code will fill in samples array for future DFT (function algorithm is described in Appendix G and DFT example represented in Figure 45, 46). 12. Next data values transferred to on the LCD screen to draw the input signal. 13. Next the function calculated amplitude values. 14. After all code executes to visualize all values. If the “freezed” is true and if “clear_screen” is false: 15. The function calculates and visualizes the DFT.
5.0 Testing As shown in the test setup, the FG-100 DDS Function Generator connected to both oscilloscopes, to make shure that they both show the same wave characteristics. Equipment: The required equipment to test the LPC 4088 Quick Start board is listed in Table 3:
Equipment Oscilloscope
HAMEG
Quantity 1
Basic Specifications Quad
channel
150
MHz
oscilloscope
HM1508-2 DC Power Supply
2
5 V, 500 mA
LPC4088 Quick Start Board
1
Cortex M4F processor, 12 bit ADC with maximum sampling frequency of 400k samples
LPC4088 Base board
1
LCD FPC 40-pos connector, SPI interface, external power supply and other.
FG-100 Generator
DDS
Function
1
1-500k
Hz,
Sine,
Square,
Triangle, Saw tooth waves
56
BNC plugs
2
-
Capacitors
2
1mF, 22mF
Potentiometers
3
4,7 k, 10 k, 20k
1
Windows 10 x64
Micro USB type A
1
-
USB type A to 1 mm jack
1
-
Multimeter UNI-T UT61
1
AC True RMS /DC voltage
PC
with
LPCXpresso
Installed
Table 3: Test Equipment Test Procedure: 1. Visual Check: In order to visually determine the nature of the wave and adjust the amplitude, we need another oscilloscope with which we can compare the reading with a signal generator. In this case, the reading is compared with the oscilloscope HAMEG HM1508-2. When submitting a signal from the signal generator LPC4088 can be set to the correct values of the amplitude and frequency by comparing them with the calibrated oscilloscope. Visual test represented in Figures 39-46 below. 2. Bandwidth: The bandwidth range for this project is the values of the frequencies in the range of 1 to 12 kHz. Test shows that anything above this range, it becomes difficult to see. This is due to low resolution analog-to-digital converter. To increase this range must use a high-frequency ADC. 3. Rise time: 𝑇𝑟 =
0.35 𝐹ℎ − 𝐹𝑙
(15)
Where, Tr -rise time, Fh= -3dB upper frequency, Fl= -3dB lower frequency, 57
0.35 is a constant for oscilloscope with bandwidth less than 1 GHz. 𝑇𝑟 =
0.35 = 0.0291 (𝑚𝑖𝑙𝑙𝑖𝑠𝑒𝑐𝑜𝑛𝑑𝑠); 12000 − 1
4. Frequency resolution and time step in DFT: The "time step"𝑑𝑡 between DFT windows in my case is 𝑑𝑡 = 𝑁. In my case, there is no overlap and I took 400 blocks samples to calculate DFT. The frequency spacing of the DFT is related to the sample rate and the DFT length. Specifically: 𝑑𝑓 =
𝑓𝑠 𝑁
(16)
where 𝑓𝑠 is the sample rate of the input data. 𝑑𝑓 in the equation above corresponds to the frequency spacing and number if binary numbers between each output. 𝑑𝑓 =
50000 𝐻𝑧 = 125 400
58
When 4.1V sine wave with 1000Hz frequency is applied to both oscilloscopes, they represent the same pattern. It shown in Figure 39 below.
Figure 39: 4.1Volts and 1000Hz Sine Wave Applied to LPC4088 and Hameg Oscilloscope 59
In the Figure 40 represented square signal with the same 4.2 peak to peak voltage:
Figure 40: 4.2Volts and 1000Hz Square Wave Applied to LPC4088 and Hameg Oscilloscope 60
In the Figure 41 represented triangular signal with the same frequency and 4 volts peak to peak voltage:
Figure 42: 4 Volts and 1000Hz Triangle wave applied to LPC4088 and Hameg Oscilloscope 61
In the Figure 43 represented saw tooth signal with the same frequency and 4 volts peak to peak voltage:
Figure 43: 4 Volts and 1000Hz saw tooth wave applied to LPC4088 and Hameg Oscilloscope 62
In the Figure 44 represented sine wave signal with 9000 Hz frequency and 2.4 peak voltage:
Figure 44: 2.4 Volts and 9000Hz sine wave applied to LPC4088 and Hameg Oscilloscope
63
In the Figure 45 represented sine wave signal with the same frequency and 2.4 volts peak to peak voltage. Then the DFT button is on LPC4088 shows us the input frequency.
Figure 45: 2.4 Volts and 9000Hz DFT functions applied to LPC4088(the green line pointed exactly 9 kHz) 64
In the Figure 46 represented sine wave signal with 3000 Hz frequency and 2.3 volts peak to peak voltage. Then the DFT button is in this figure more clearly shown DFT pattern.
Figure 46: 2.3 Volts and 3000Hz DFT functions applied to LPC4088(the green line point exactly to 3 kHz)
65
6.0 Conclusion and Future Work
6.1 Frame-Based Processing One of the improvements which can be implemented is Frame-Based Processing. Instead than processing one sample at a time, the DFT algorithm is applied to blocks, or frames of samples. DFT in a real–time program requires a different approach. In my project I used some functions from CMSIS DSP library, and this library processed blocks of sample and used direct memory access based on input/output values. It is possible to implement buffering, and sample block processing by using interrupt-based input/output. DMA-Based input/output on the LPC4088 is organized into unidirectional streams, but it possible to use 2 channels. One DMA channel can be configured to make DMA transfers between the output buffers and the SPI peripheral. It will be generating an interrupt when a transfer from buffer samples will be completed. Another DMA channel can be configured to make DMA transfers between the SPI peripherals and the input buffers in memory. It will generate an interrupt when a transfer from previous buffer samples will be completed. The same interrupt service routine can be used for both aforementioned DMA processes. The actions carried out in this routine should be assigned to the pointers and the array values should switch
between
buffers
dma_buffer_2) after
(e.g.
dma_buffer_1,
dma_buffer_2,
dma_buffer_1
and
that buffer flags can be set for full (1) or empty (0).
The main() function will be wait until both buffer flags will be settled. It is mean that until both DMA transfers should be completed before processing buffer values. After the processed buffer values should be included in the loop to repeat process with recently filled input buffer values. In general, frame based processing should be carried out in function which processed buffer values by using the contents of the most recently filled input buffer as input and writing output sample value to the most recently emptied output buffer. After the DMA transfers will be complete, and processing buffer functions will be called, every 32-bit samples instants and therefore any processing can be completed within processing buffer before the next DMA transfer completion.
66
6.2 High speed ADC Another important improvement that can be implemented in this project is to increase the number of samples and bit depth of analog-to-digital converter for more fast signal representation and much better signal representation. For example, the AD9266 which is a single-channel 16-bit, 40 MSPS analog-to-digital converter. It features is a high performance which includes on-chip voltage reference. AD9266 uses multistage differential pipeline architecture with output error correction logic to provide 16bit accuracy at 40 MSPS data rates through SPI protocol. There is also no missing codes architecture. The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. A differential clock input with a selectable internal 1-to-8 divide ratio can controls all internal conversion cycles. It also includes duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle for better ADC performance. This also useful such as it supports 3.3 V CMOS levels so it can be directly powered from LPC4088 internal voltage.
6.3 Using FFT instead of DFT The Discrete Fourier Transform is a mathematical operation which multiplies in my case samples sequence matrix of 400x400 and then draw the result on the LPC4088 LCD screen. To compute such a big matrix LPC4088 required about 10 seconds. To improve the execution, speed the Fast Fourier Transform (FFT) algorithm can be implemented. It is an efficient way to evaluate this operation. Typically, the number of operations required by the FFT is on the order of N*logN. The most famous FFT algorithms are for the case that N is a power of 2, but there are FFT for prime orders which can be much faster calculated instead of calculate such a big matrix.
6.4 Power Supply The MT3608 switches at 1.2MHz and this frequency produces the noise on the output voltage. For internal LPC4088 ADC this noise makes no difference, but for the future improvement LC filtering or an output filter capacitor technique can be applied. LC filters are generally used only where very accurate analog measurements are being taken, and the power supply rejection is poor at the ripple frequency. A much more common filtering technique is the output filter 67
capacitor. It can consist from tantalum capacitors which should be located to the source of noise as closer as possible. If, however, the noise level will make changes in the measured signal as an alternative circuit LPC4088 can be supplied directly from the battery. The laboratory power supply can also be used to provide clear supply voltage into the system.
6.5 Conclusions Looking back at this project, it was observed that the amount of time taken on research, designing and constructing the oscilloscope was much greater than the amount of time dedicated to testing. Due to this fact, there was not enough time to resolve every problem encountered and completely function the high precision oscilloscope. Having gathered all the circuits related to a readymade oscilloscope, it was assumed that once all the wiring is finished the high precision oscilloscope would function perfectly without giving much trouble. This assumption was wrongly proven because of the fact that many unexpected problems were encountered and they needed to be resolved in a short period of time. Therefore, it must be pointed out that much more consideration should have been given concerning timemanagement. First of the major problem encountered, was that certain components expected to arrive from abroad, did not arrive on time. The second problem was too small size of the main components for accurate solder which took too much time. Therefore, as a result, similar circuit was implemented.
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7.0 References 1. Ardizzoni, J. (2005, September). A Practical Guide to High-Speed Printed-Circuit-Board Layout. Retrieved from Analog Devices: http://www.analog.com/library/analogDialogue/archives/39-09/layout.html 2. E.McAbel, W. (1969). Meashurement Concepts: Probe Measurement. Tektronix. 3. Flach, T. S. (June 1987). Accurate Frequency Response Determinations from Discrete Step Response Data. IEEE Transmission Instrumentation Meashurement v.36,no2. 4. Hellwig, D. M. (n.d.). Rohde & Schwarz.High-Resolution Measurements with R&S Oscilloscopes. Munich. 5. IEEE Standart 1057-1994. (Dec. 1994). IEEE Standart for Digitizing Waveform Recorders. 6. John G. Proakis, D. G. (2007). Digital Signal Processing. New Jersey: Prentice-Hall, Inc. 7. John P.Deyst, N. G. (1998). A Fast Pulse Oscilloscope Calibration System. St.Paul, Minnesota, USA: IEEE Instrumentation and Meashurement. 8. Literature Number: SPRU889. (2005). High-Speed DSP Systems Design: Reference Guide. Texas Instruments. 9. Moore, G. (1979). Are we really ready for VLSI? 10. Nicolson, A. (Dec.1968). Broad-Band Microwave Transmission Characteristics From a Single Meashurement of the Transient Response. IEEE Transition Instruments Meashurement v.IM-17, no.4. 11. Ricardo Costa, D. P.-R. (February 2015). An FPGA-embedded oscilloscope. An FPGAembedded oscilloscope (pp. 1-5). Porto, Portugal: Research Gate. 12. Ruiter, J. H. (1949). Modern Oscilloscopes and Their Uses. Murray Hill Books. 13. S.Trimberger. (1994). Field Programmable Gate Array Techology. Boston, MA, USA: Kluwer Academic. 14. Society, I. I. (2001). IEEE Standard for Digitizing. NY: IEEE Instrumentation & Measurement Society. 15. Literature number SP250, N. S. (1998 edition). Calibration Services Users Guide.Texas Instruments. 16. Trimberger, S. M. (March 2015). Three Ages of FPGAs: A Retrospective on the First Thirty Years of FPGA Technology. Proceedings of the IEEE. Vol. 103, No. 3, 318-331. 17. W.L.Gans. (Dec 1990). Dynamic Characterization of Waveform Recorders and Oscilloscopes using Pulse Standarts. IEEE Transmission Instrument Meashurement, v.39,no.6. 18. Walden, R. H. (1999). Analog-to-Digital Converter Survey and Analysis. IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS, 17.
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Appendix A (Main Program Flowchart)
70
Appendix B (Main.cpp) Includes: #include "mbed.h" //#include #include "platform.h" #include "Display.h"
Type definitions: #define round(x) ((x)>=0?(int)((x)+0.5):(int)((x)-0.5)) #define PI 3.14159265358979 #define SAMPLES_COUNT 400 typedef struct { float real; float imag; } COMPLEX;
Local variables: COMPLEX samples[SAMPLES_COUNT]; AnalogIn ain_scale(A1); AnalogIn ain_signal(A5); DigitalIn din_freezing_btn(p31); Timer timer; Display display; float float float float
max = 0.0f; min = 0.0f; amplitude = 0.0f; frequency = 0.0f;
char str[6];//sprintf text buffer float buffer[SAMPLES_COUNT];//voltage samples float scale = 0.0f; int sleep_us = 0; bool freezed = false; int time_ms = 0;
Local functions: void dft(COMPLEX *x); int make_samples(unsigned short count, int delay); float range_limit(float a, float b); void draw_diagram(COLOR_T color); void draw_dft_marks(COLOR_T color); void draw_appearance(); void draw_result_values(); int main() { bool clear_screen = false;
71
display.init(); for(int i = 0; i < SAMPLES_COUNT; i++) { buffer[i] = 0.0f; samples[i].real = 0.0f; samples[i].imag = 0.0f; } draw_appearance(); while(1){ max = 0; min = 0; freezed = !din_freezing_btn; scale = ain_scale.read() * 100.0f; sleep_us = round(scale); if(!freezed) { if(clear_screen)//clear workspace { display.SetPenColor(WHITE); display.DrawSquare(0, 20, 400, 252); clear_screen = false; } else //clear DFT track { draw_diagram(BLACK); } time_ms = make_samples(SAMPLES_COUNT, sleep_us); for(int i = 0; i < SAMPLES_COUNT; i++) { buffer[i] = buffer[i] - 0.5f; max = max < buffer[i] ? buffer[i] : max; min = min > buffer[i] ? buffer[i] : min; samples[i].real = buffer[i]; samples [i].imag = 0.0f; } draw_diagram(YELLOW); max *= 3.3f; min *= 3.3f; amplitude = max - min;//max voltage 3.3v draw_result_values(); clear_screen = false; timer.reset(); wait_ms(166); } else { if(!clear_screen) {
72
dft(samples); display.SetPenColor(GREEN); for (int i = 0; i < SAMPLES_COUNT - 1; i++) { display.DrawLine(i, 166.0f + ((range_limit(samples[i].real, 33.0f)) * -1.0f), i, 166.0f + ((range_limit(samples[i+1].real, 33.0f)) * -1.0f)); } clear_screen = true; } } } } void draw_diagram(COLOR_T color) { display.SetPenColor(color); for (int i = 1; i < SAMPLES_COUNT - 1; i++) { display.DrawLine(i, 136.0f + ((buffer[i] * 225.0f) * -1.0f), i, 136.0f + ((buffer[i + 1] * 225.0f) * 1.0f)); } } int make_samples(unsigned short count, int delay) { timer.start(); for(int i = 0; i < count; i++) { wait_us(delay); buffer[i] = ain_signal; } timer.stop(); return timer.read_ms(); } void dft(COMPLEX *x) { COMPLEX result[SAMPLES_COUNT]; int k,n; for (k=0 ; kwidth * _lcdCfg->height * 2 * 3); // 2 is for 16 bit color, 3 is the number of buffers if (_framebuffer != 0) { memset((uint8_t*)_framebuffer, 0, _lcdCfg->width * _lcdCfg>height * 2 * 3); } } } bool Display::init() { if (_framebuffer == 0) { printf("Failed to allocate memory for framebuffer\n"); return false; } EaLcdBoard::Result result = _lcdBoard.open(_lcdCfg, _initStr); if (result != EaLcdBoard::Ok) { printf("Failed to open display, error %d\n", result); return false; } result = _lcdBoard.setFrameBuffer(_framebuffer); if (result != EaLcdBoard::Ok) { printf("Failed to set framebuffer, error %d\n", result); return false; } return swim_window_open(&this->_win, _lcdCfg->width, _lcdCfg->height, // full screen (COLOR_T*)_framebuffer, 0,0,_lcdCfg->width-1,_lcdCfg->height-1, // window position and size 0, // border WHITE, BLUE, BLACK); // colors: pen, backgr, forgr } void Display::DrawLine(int32_t x1, int32_t y1, int32_t x2, int32_t y2) { swim_put_line(&this->_win, x1, y1, x2, y2); } void Display::DrawColorLine(COLOR_T pen_color, int32_t x2, int32_t y2) { COLOR_T old_color = _win.pen; swim_set_pen_color(&this->_win, pen_color); this->DrawLine(x1, y1, x2, y2);
int32_t
x1,
int32_t
y1,
77
swim_set_pen_color(&this->_win, old_color); } void Display::DrawPixel(int32_t x, int32_t y) { swim_put_pixel(&this->_win, x, y); } void Display::DrawSquare(int32_t x1, int32_t y1, int32_t x2, int32_t y2) { swim_put_box(&this->_win, x1, y1, x2, y2); } void Display::DrawText(const CHAR* text, int32_t x, int32_t y) { swim_put_text_xy(&this->_win, text, x, y); } void Display::SetPenColor(COLOR_T pen_color) { swim_set_pen_color(&this->_win, pen_color); }
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Appendix E (EaLCDBoardGPIO.h) Includes: #include "EaLcdBoard.h"
Type definitions: #ifndef EALCDBOARDGPIO_H #define EALCDBOARDGPIO_H
An interface to Embedded Artists LCD Boards: class EaLcdBoardGPIO : public EaLcdBoard { public: EaLcdBoardGPIO(PinName sda, PinName scl); void setBC(uint32_t val) { setBacklightContrast(val); }; protected: virtual virtual virtual virtual virtual
void void void void void
setWriteProtect(bool enable); set3V3Signal(bool enabled); set5VSignal(bool enabled); setDisplayEnableSignal(bool enabled); setBacklightContrast(uint32_t value);
private: //DigitalOut pinWP; DigitalOut pin3v3; DigitalOut pin5v; DigitalOut pinDE; //DigitalOut pinContrast; PwmOut pinContrast; }; #endif
79
Appendix F (EaLCDBoardGPIO.cpp)
Includes: #include "mbed.h" #include "EaLcdBoardGPIO.h"
Type definitions: EaLcdBoardGPIO::EaLcdBoardGPIO(PinName sda, PinName scl) : EaLcdBoard(sda, scl), /*pinWP(P4_15),*/ pin3v3(P2_0), pinDE(P2_11), pinContrast(P2_1) { pinContrast.period_ms(10); setWriteProtect(true); set3V3Signal(false); set5VSignal(false); setDisplayEnableSignal(false); setBacklightContrast(0); } void EaLcdBoardGPIO::setWriteProtect(bool enable) { // Not Applicable }
pin5v(P2_21),
void EaLcdBoardGPIO::set3V3Signal(bool enabled) { //P2.0 L=3.3V on if (enabled) { pin3v3 = 0; } else { pin3v3 = 1; } } void EaLcdBoardGPIO::set5VSignal(bool enabled) { //P2.21 H=5V on if (enabled) { pin5v = 1; } else { pin5v = 0; } } void EaLcdBoardGPIO::setDisplayEnableSignal(bool enabled) { //P2.11 H=enabled LPC_IOCON->P2_11 &= ~7; /* GPIO2[11] @ P2.11 */ if (enabled) { pinDE = 1; } else { pinDE = 0; } } void EaLcdBoardGPIO::setBacklightContrast(uint32_t 4.30 for now #if 0
value)
{
//P2.1,
set
to
80
LPC_IOCON->P2_1 &= ~7; /* GPIO2[1] @ P2.1 */ if (value > 50) { pinContrast = 1; } else { pinContrast = 0; } #else uint32_t tmp = LPC_IOCON->P2_1; tmp &= ~7; tmp |= 1; LPC_IOCON->P2_1 = tmp; /* PWM2[1] @ P2.1 */ float f = value; pinContrast = f/100.0f; #endif //
if (value > 100) return;
// // // }
pca9532_setBlink0Duty(100-value); pca9532_setBlink0Period(0); pca9532_setBlink0Leds(LCDB_CTRL_BL_C);
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Appendix G (Discrete Fourier Transform Function) This code illustrates the DFT of an N-point, real valued sequence. Program is used to calculate the complex DFT. 𝑁−1 2𝜋𝑘𝑛 𝑁
𝑋(𝑘) = ∑ 𝑥(𝑛)𝑒 −𝑗
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𝑛=0
N-point complex sequence is stored in array result and a pointer to this array is passed to the function dft(). That function is required to replace the complex time domain sequence which passed to it with its complex, frequency domain representation (DFT). The COMPLEX structure intended for show the complex numbers in rectangular form. Here Euler’s formula calculates the relationship between exponential and rectangular representation of complex quantities: 𝐴𝑒 𝑗𝑤𝑡 = 𝐴𝑐𝑜𝑠(𝑤𝑡) + 𝑗𝐴𝑠𝑖𝑛(𝑤𝑡)
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Includes: #include #include "platform.h"
Type definitions: #define PI 3.14159265358979 #define SAMPLES_COUNT 400 typedef struct { float real; float imag; } COMPLEX; COMPLEX samples[SAMPLES_COUNT]; void dft(COMPLEX *x) { COMPLEX result[SAMPLES_COUNT]; int k,n; for (k=0 ; k
