Design and Implementation of a Robust Electronic ...

University of Sharjah College of Engineering Department of Electrical and Computer Engineering

Phase II – Senior Design Project 2

Design and Implementation of a Robust Electronic Read-out Circuit Chain for Monitoring and Processing of an EEG Signal

Project Group U00027790 U00024494 U00030226

Amal AbdulAziz Bushra Alhendi Saarah Abdulla

Project Examination Committee Supervisor Prof. Soliman Mahmoud Examiner Prof. Ahmed El Wakil Chair Dr. Anwar Jarndal

Spring 2014/2015

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Table of Contents List of figures ...................................................................................................................... iv List of Tables ...................................................................................................................... vii Abstract ............................................................................................................................... 1 Introduction ......................................................................................................................... 2 1 Electrodes ............................................................................................................................ 3 1.1 Introduction ................................................................................................................... 3 1.2 Types of Biopotential Electrodes ................................................................................... 3 1.3 Standard Methods of Electrodes Placement ................................................................... 4 1.4 EEG Recording Techniques ............................................................................................ 4 1.5 Conclusion ...................................................................................................................... 5 2 Instrumentation Amplifier.................................................................................................. 6 2.1 Introduction .................................................................................................................... 6 2.2 Simulation ...................................................................................................................... 6 2.3 Circuit Implementation ................................................................................................... 7 2.4 Results ............................................................................................................................ 8 2.5 Conclusion ...................................................................................................................... 9 3 Notch Filter ........................................................................................................................ 10 3.1 Introduction .................................................................................................................. 10 3.2 Generating Notch Filter from Band-pass Filter ............................................................ 10 3.3 Simulation .................................................................................................................... 11 3.4 Hardware Circuit and Settings ...................................................................................... 13 3.5 Results .......................................................................................................................... 14 3.6 Conclusion .................................................................................................................... 17 4 Variable Gain Amplifier ................................................................................................... 18 4.1 Introduction .................................................................................................................. 18 4.2 Simulation .................................................................................................................... 18 4.3 Hardware Circuit and Settings .................................................................................... 20 4.4 Results ......................................................................................................................... 21 4.5 Conclusion ................................................................................................................... 21 5 Low Pass Filter .................................................................................................................. 22 5.1 Introduction .................................................................................................................. 22 5.2 Simulation .................................................................................................................... 22 5.3 LTC1064-2 Circuit and Settings ................................................................................... 26

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5.4 LTC1064-2 Test Results ............................................................................................... 26 5.5 Sallen-Key Design and Circuit Implementation ........................................................... 29 5.6 Sallen-Key Test Results ................................................................................................ 30 5.7 Conclusion .................................................................................................................... 33 6 Overall System Design ...................................................................................................... 33 6.1 Introduction .................................................................................................................. 33 6.2 Simulation .................................................................................................................... 34 6.3 Hardware Circuit and Settings ..................................................................................... 36 6.4 Beta Testing .................................................................................................................. 37 6.5 Overall System Specifications ...................................................................................... 42 6.6 Conclusion .................................................................................................................... 43 7 Challenges, Constraints and Future Work ..................................................................... 44 7.1 Introduction .................................................................................................................. 44 7.2 Challenges .................................................................................................................... 44 7.3 List of Constraints ........................................................................................................ 45 7.4 Future Work ................................................................................................................. 45 8 List of Parts and Actual Cost ........................................................................................... 46 8.1 Testing Cost .................................................................................................................. 46 8.2 Actual Cost ................................................................................................................... 46

Conclusion .......................................................................................................................... 48 References ........................................................................................................................... 49 Appendices .......................................................................................................................... 50

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List of Figures Figure 1.1 – 10-20 EEG recording system ……………………................................... 4 Figure 2.1 – Simulink Model of the Instrumentation Amplifier AD8230 ................... 6 Figure 2.2 – Inverting and non-inverting input signals of the IA ................................ 7 Figure 2.3 – Output signal of the IA using Simulink ................................................... 7 Figure 2.4 – AD8230 internal architecture and hardware circuit ................................. 8 Figure 2.5 – Input and output waveforms of AD8230 ................................................. 8 Figure 3.1 – The effect of adding poles on the frequency response of a notch filter.. 10 Figure 3.2 – The operation of generating a notch filter from a band-pass filter…..... 11 Figure 3.3 – Notch Filter Simulink model………………………………….……..... 12 Figure 3.4 – The waveform and spectrum of the 100 Hz input signal (PSD2) .......... 12 Figure 3.5 – The waveform and spectrum of the 50 Hz input signal (PSD3) ............ 12 Figure 3.6 – The notch filter input waveform and spectrum (PSD1) …..................... 13 Figure 3.7 – The notch filter output waveform and spectrum (PSD4) …................... 13 Figure 3.8 – Hardware circuit diagram and internal structure of LMF90 ………...... 14 Figure 3.9 – The input and output waveforms of the notch filter with input signal frequency of 100 Hz ………....................................................................................... 15 Figure 3.10 – The input and output waveform of the notch filter with input signal frequency of 50 Hz …………………………………................................................. 15 Figure 3.11 – Frequency response of LMF90 notch filter ………………................. 16 Figure 4.1 – VGA model using Simulink .................................................................. 19 Figure 4.2 – Input signal of the VGA using Simulink ............................................... 19 Figure 4.3 – Output signal of the VGA using Simulink ............................................. 20 Figure 4.4 – Circuit implementation of VGA ............................................................ 20 Figure 4.5 – Input and output signals of the VGA with gain=100 ............................. 21 Figure 5.1 – Low Pass Filter LTC1064-2 Simulink model ...................................... 22 Figure 5.2 – Waveform and spectrum of input signal (PSD1) …………................... 23 iv

Figure 5.3 – Waveform and spectrum of LPF referred noise (PSD2) ........................ 23 Figure 5.4 – Waveform and spectrum of random high frequency noise (PSD3) ....... 24 Figure 5.5 – Waveform and spectrum of signal and total noise added (PSD5) ......... 24 Figure 5.6 – Waveform and spectrum of the LPF output (PSD4) …………….......... 25 Figure 5.7 – Bode and phase plot of LPF simulation ………………………............. 25 Figure 5.8 – Hardware circuit implementation of the LTC1064-2 LPF ……............ 26 Figure 5.9 – The input and output waveforms of the LPF with input signal frequency of 100 Hz ………………………………………………………………………........ 27 Figure 5.10 – The input and output waveforms of the LPF with input signal frequency of 300 Hz ………………………………………………………..………...…........... 27 Figure 5.11 – The Frequency response of LTC1064-2 with cutoff frequency of 200 Hz …………………………………………………………………………….......... 28 Figure 5.12 – The input and output waveforms of LTC1064-2 with input signal frequency of 100 Hz …………………………………………….….......................... 29 Figure 5.13 – Hardware circuit implementation of 4th order Sallen-Key LPF .......... 30 Figure 5.14 – Input and output waveforms of the 4th order Sallen-Key LPF with a 100 Hz input frequency ………………………………….………..……………….......... 31 Figure 5.15 – Input and output waveforms of the 4th order Sallen-Key LPF with a 500 Hz input frequency ………………………………….……………………..….......... 31 Figure 5.16 – Frequency response of a 4th order Sallen-Key LPF with 120 Hz cutoff frequency ………………………………………………………….…………........... 32 Figure 6.1 – Overall system block diagram ………………………......….…............ 33 Figure 6.2 – Overall system Simulink model ………………….……………............ 33 Figure 6.3 – Waveform and spectrum of the instrumentation amplifier input .…...... 34 Figure 6.4 – Waveform and spectrum of the instrumentation amplifier output ......... 34 Figure 6.5 – Waveform and spectrum of the notch filter output ………………........ 35 Figure 6.6 – Waveform and spectrum of the variable gain amplifier output …......... 35 Figure 6.7 – Waveform and spectrum of the low pass filter output ……….….......... 36 Figure 6.8 – Overall system circuit implementation ……………………….…........ 36 Figure 6.9 – Waveform of the electrode output signal …………………….….......... 37 v

Figure 6.10 – Waveform of the IA output signal …………………...…………........ 37 Figure 6.11 – Waveform of the notch filter output signal …………………….......... 38 Figure 6.12 – Waveform of the high pass filter output signal …………………........ 38 Figure 6.13 – Waveform of the VGA output signal …………………………........... 39 Figure 6.14 – Waveform of the low-pass filter output signal …………………........ 39 Figure 6.15 – Subject 1 EEG waveform ………………………………………........ 40 Figure 6.16 – Subject 2 EEG waveform ………………………………………........ 40 Figure 6.17 – Subject 3 EEG waveform ………………………………………........ 41 Figure 6.18 – Subject 4 EEG waveform ………………………………………........ 41 Figure 6.19 – Subject 5 EEG waveform ………………………………………........ 42 Figure 6.20 – Beta waveform ………………….………………………………........ 42

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List of Tables Table 3.1 – Filter characteristics with center frequency of 50 Hz ............................. 16 Table 5.1 – LTC1064-2 filter characteristics .……………...…..…….…………............... 28 Table 5.2 – Sallen-key LPF filter characteristics ………………………………................ 32 Table 8.1 – Parts list and cost of the system for testing …......................................... 46 Table 8.2 – Parts list and actual cost of the system ……............................................ 47

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Abstract The electroencephalogram (EEG) is a recording of the electrical activity of the brain from the scalp. EEG signals are very low in amplitude and frequency. The amplitude range extends up to 100μV and the maximum frequency present is 100Hz. In this project, an EEG system was designed and implemented to extract the EEG signal and minimize the various interferences. The system consists of several blocks for monitoring and processing purposes. Electrodes are used to extract the brain signal. An instrumentation amplifier, to amplify the difference between the active and reference electrodes and reject the common signals to both inputs. A notch filter is used to remove the 50 Hz power-line interference, followed by a variable gain amplifier to amplify the signal. A low pass filter is used to remove the high frequency noise and smooth out the signal. Finally, the signal was displayed using LABVIEW via Data Acquisition (DAQ).

‫الملخص‬ ‫حخطُػ أيىاج انذياغ هٍ غشَقت نخسدُم انُشاغ انكهشبائٍ يٍ فشوة انشأط حُخح انعصبىَاث انذياغُت‬ ‫فىنج و أكبش حشدد حصم‬-‫ ياَكشو‬100 ً‫ يذي انًىخاث انذياغُت ًَخذ إن‬.‫إشاساث نذَها يذي صغُش و حشدد قهُم‬ ‫فٍ هزا انًششوع حى حصًُى وحُفُز َظاو نخخطُػ يىخاث انذياغ نغشض اسخخالص‬. ‫ هشحض‬100 ‫إنُه انًىخاث هى‬ ‫اندضء‬. ‫انُظاو َخكىٌ يٍ عذة أخضاء نشصذ ويشاقبت اإلشاساث انذياغُت‬. ‫اإلشاسة انذياغُت و حقهُم انخذاخالث‬ ‫اندضء انثاٍَ هى اندهاص انًكبش و َسخخذو‬. ‫األول هى انقطب انكهشبائٍ و َسخخذو السخخالص اإلشاسة انذياغُت‬ ‫ وأَعا َسخخذو نخصغُش اإلشاساث‬،‫نخكبُش انفشق بٍُ انقطب انكهشبائٍ انُشػ و انقطب انكهشبائٍ انًصذس‬ ٍ‫انًششح إَقاف انُطاق َسخخذو إلصانت انخذاخالث انصادسة ع‬. ‫انًشخشكت بٍُ انقطبٍُ وانخٍ حًثم انعىظاء‬ ‫اندضء انخانٍ فٍ انُظاو هى يكبش انفىنج انًخغُش وَسخخذو نخكبُش اإلشاسة‬. ‫ هشحض‬50 ٌ‫خطىغ انكهشباء رو‬ ‫ يششح انخشدداث انًُخفط هى اندضء األخُش فٍ انُظاو و َسخخذو إلصانت انخشىشاث‬.‫انذياغُت راث انًذي انصغُش‬ . LABVIEW‫ انًشحبػ ببشَايح‬DAQ ‫حى حىصُم اإلشاسة األخُشة بعذ حكبُشها فٍ خهاص‬. ‫راث انخشدد انكبُش‬

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Introduction Biomedical signals are the signals generated from the electrochemical activity in the human body. One of the main bioelectrical signals is the EEG. An electroencephalogram (EEG) is a test that measures and records the electrical activity of your brain. These signals can be extracted by bio-medical sensor systems. The aim of this project is to design an EEG system in the IC level, minimize the various noise and interferences and finally process the obtained signal. The obtained signal can be used for further medical applications. The main goal is to improve the current acquisition systems that will benefit not only patients but the entire medical field. The project addresses the design and implementation of an improved robust electronic system that can monitor and process EEG signals. EEG signals are low in amplitude (µV) and are contaminated with noise. So, the function of the EEG acquisition system is to remove the noise and amplify the desired signal. To monitor and process EEG signals, a system must include four main blocks. Sensors are used to extract the required signal, amplifiers to enhance and amplify them, filters to remove unwanted interferences. In this project, the blocks of the system are electrodes, instrumentation amplifier, notch filter, low-pass filter, variable gain amplifiers and an analog to digital converter. This report will include simulation and unit testing of each block, as well as the overall system simulation and implementation. The importance of this project is that it can be used for many biomedical applications, e.g. helping in creating new treatments and obtaining new measurements of brain activity based on EEG signals. It can be helpful also in clinical environments, e.g. for epilepsy diagnosis or tumors, predicting epileptic seizures, detecting abnormal brain states and diseases , stroke rehabilitation and classifying sleep stages.

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Chapter 1 Electrodes

1.1 Introduction Electrodes are crucially important because they constitute the first stage of the signal processing chain. Electrodes’ properties dominate the overall performance of the acquisition system and the noise making its selection extremely important. The readout circuits often have very large input impedance and a non-zero current must flow to the input of the circuit from the body. This current is carried by ions in the body but in the wires it is carried by the electrons; so an interface is required to convert the ionic current into an electronic current. That interface is called a transducer interface between the readout circuit and the body. The transducer interface is known as bio-potential electrodes [1].

1.2 Types of Biopotential Electrodes Biopotential electrodes can be classified into three types; wet, dry and noncontact. Wet electrodes use a type of gel as an electrolyte between the electrode and the skin surface. The electrical contact between the skin surface and the electrode is done by using the electrolyte gel [2]. The second type of the bio-potential electrode is the dry electrode. These electrodes don’t use gel to establish the electrical contact between the skin and the electrode [3]. The third type is the non-contact electrodes. The non-contact was introduced because the presence of the hair can make the electrode lose contact with the scalp. They are considered as a pure capacitor between the readout circuit and the skin surface, so they allow remote sensing of the bio-potential signals [3]. The wet electrode is the most suitable electrode because it has the lowest input impedance, low rms noise and commercially available [4]. The wet electrode used in this project is the Ag/AgCl since it's the most common type of the wet electrodes. The metal of the electrode is made from silver (Ag) and it's covered with an AgCl layer.

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1.3 Standard Methods of Electrode Placement The basic job of the electrode is to read the signal from the skin surface which is in the microvolt range. To measure the neuronal activity of the brain (EEG signal), it is required to have a potential difference over time in the basic electrical circuit. Therefore, a signal (active) electrode, a reference electrode and a ground electrode are needed. The standard method of Electrode Placement is the 10-20 method which has been used since 1958 for clinical EEG. The 10-20 electrode system uses 21 electrodes. The distance between two adjacent electrodes is either 10% or 20% of the total right-left and the front-back distance on the skull as shown in Fig.1.1. 10-10 electrode system and 10-5 electrode system are other methods of electrode placement. The numbers in the electrode system names refer to the distance between two adjacent electrodes [5].

Fig. 1.1 10-20 EEG recording system [6].

In this project, the electrodes were limited to only two electrodes; one active electrode and the reference electrode. The ground electrodes have no significant role in the modern instrumentation so it was not used.

1.4 EEG Recording Techniques The choice of a location for an active electrode on the scalp to record the EEG depends on the application. Each location of the brain has a different function. The front side of the scalp controls the intentional and motivational emotions. The center 4

of the scalp deals with the sensory and motor functions. The sides of the scalp, close to the ears, certain memory functions stand. The visual areas are located on the back of the scalp. There are several locations to place the reference electrode. The reference electrode can be chosen as linked-earlobes, linked-mastoids, vertex, ipsilateral-ear, contralateral-ear and the tip of the nose. In this project, the location of the active electrode was placed on the forehead (FP). The reason for this location as there is no hair present to disturb the signal and it is known to produce a stable signal. The patient is also asked to close their eyes, due to the presence of EOG artifacts. The most dominant wave present in the anterior region of the brain is the beta wave. Beta states are the states associated with normal waking consciousness. Low amplitude beta waves with multiple and varying frequencies (12.5–30 Hz) are often associated with active, busy, or anxious thinking and active concentration [7]. The location of the reference electrode was chosen to be on the mastoid. The mastoid is the bone behind the ear. EEG signals can be measured only with respect to a reference electrode. Ideally, the reference electrodes get affected by global voltage changes in the same way as all the active electrodes. This results in subtracting out the brain unwanted activity or the surrounding activity, which is known as the noise. The best reference for the EEG one channel application is the mastoid because it’s located in the inactive zone. The linked earlobes may be used but they cause some distortion to the EEG signals, since there is an electric current flowing inside the linking wire so it wasn’t used in the project [8].

1.5 Conclusion In this project, the wet electrodes are used because it is the most accurate among the other two types and has low impedance. Also, it's commercially available and widely used in the medical field since it's more practical and has lower noise than the other electrode types. The active electrode was placed on the forehead and the reference electrode was placed on the mastoid.

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Chapter 2 Instrumentation Amplifier

2.1 Introduction An instrumentation amplifier (IA) is defined as a device that amplifies the difference between two input signal voltages while rejecting the common signals to both inputs. The IA therefore, provides a very important function in this project which is the extraction of EEG signals from the electrodes. The chosen IA from the first phase of the project is AD8230 which belongs to the switched capacitor category, fortunately it already has a built in sampling clock with sampling frequency of 6 kHz. This IC was chosen due to several factors; high Common Mode Rejection (CMR > 110dB), adjustable gain (G=10 to 1000), and relatively low generated noise (0.22µV/√Hz).

2.2 Simulation The IA was modeled using Simulink as a gain block in series with a low-pass filter. And since the IA has a differential input it was modeled as a subtractor block with two sinusoidal inputs. The two inputs are 180 o phase shifted shown in Fig. 2.2. The input referred noise was taken into consideration and added with the input signals. It was modeled as white noise with amplitude of 3 µVpp. The output of the IA model is shown in Fig. 2.3. The specifications for the model are the gain which is 10 and the gain bandwidth which is 2.5 kHz. The model is shown in Fig. 2.1.

Fig. 2.1 Simulink Model of the Instrumentation Amplifier AD8230.

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Fig. 2.2 Inverting and non-inverting input signals of the IA.

Fig. 2.3 Output signal of the IA using simulink.

2.3 Circuit Implementation The circuit that was built is shown in Fig. 2.4 RF and RG are the gain setting resistors; the gain can be adjusted using the following equation (2.1) In our case, the gain was approximately set to 10 using RF= 5.6 kΩ and RG= 1 kΩ. Low gain is preferred at the first stage of the block design because the received signal from the electrode will be highly contaminated with noise.

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Fig. 2.4 AD8230 internal architecture and hardware circuit.

2.4 Results The IC was tested using two antiphase 100 mVpp sinusoidal inputs of 100 Hz frequency. The gain was verified to be 10 as shown in Fig. 2.5.

Fig. 2.5 Input and output waveforms of IA AD8230.

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2.5 Conclusion The chosen IA was simulated and tested practically for input signals with the same amplitude and frequency of an EEG signal. Test results showed that it removed the common signals which are basically noise and interferences. It also showed that it provided gain to the input signal. So, the IA chosen is suitable for this project application.

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Chapter 3 Notch Filter

3.1 Introduction The notch filter is one of the building blocks of the proposed design. It is used mainly to remove the 50 Hz power-line interference. Power line noise can be easily picked up through electrode cables, electrical devices and the patient being monitored. The IC chosen in Phase I is LMF90, which is of switched capacitor configuration.

3.2 Generating Notch Filter from Band-pass Filter To realize a notch filter, theoretically, its transfer function must have at least two zeroes in the jω axis places at ±jω0. However, such filter will not have a unity gain at zero frequency and will not be sharp. So, to obtain a good notch filter two poles has to be added close enough to the zeroes. Since both pole/zero pair are at equal distance to the origin, the gain will be unity as shown in Fig.3.1.

Fig. 3.1 The effect of adding poles on the frequency response of a notch filter [9].

A notch filter can be produced by the use of a band-pass filter. The simplest band-pass filter has at least two poles in its transfer function, as shown below

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(3.1) To generate a notch filter the input of the band-pass filter has to be subtracted from its output. This operation is described in Fig. 3.2.

Band-pass Filter HBPF(s) VIN

+ _ ∑

VOUT

Fig. 3.2 The operation of generating a notch filter from a band-pass filter.

VOUT is the output of the notch filter, where its transfer function has two poles and two zeroes as described earlier. The transfer function of the band-stop filter can be derived from the figure (3.2) This method was also used in the design of LMF90 bandstop-filter. However, the band-pass filter used is fourth order. The transfer function of a band-stop filter can be derived (3.3)

3.3 Simulation The notch filter block was modeled using Simulink. Fig. 3.3 shows the system with the added noise components generated from the block itself and the environment. The input is a sinusoidal signal of frequency 100 Hz. Also, the input referred noise of the block with 350 µVrms is added to the input signal. In addition, a 50 Hz signal is added which the notch filter will remove.

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Fig. 3.3 Notch Filter Simulink model.

The following figures show the output of each Power Spectral Density block in the system.

Fig. 3.4 The waveform and spectrum of the 100 Hz input signal (PSD2).

Fig. 3.5 The waveform and spectrum of the 50 Hz input signal (PSD3).

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Fig.3.6 The notch filter input waveform and spectrum (PSD1).

Fig. 3.7 The notch filter output waveform and spectrum (PSD4).

3.4 Hardware Circuit and Settings LMF90 is a 4th-order elliptic notch filter. An external 3.579545 MHz oscillator is used to set the center frequency. The clock to center frequency ratio is set to 100:1, so a clock frequency of 5 kHz must be used to obtain a 50 Hz center frequency. To set the clock frequency to 5 kHz, an internal clock frequency divider of 716 is chosen for the external oscillator. The hardware circuit is shown in Fig. 3.8.

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+5V

-5V

0.1 µF

VIN

14

13

V+

GND

12

11

VIN1

VIN2

0.1 µF

VOUT

10

9

D

VOUT

8 V

-

_ ∑ + 4th-Order Bandpass Level Shift

LMF90

Non-Overlapping Clock Generator

+2, +596, +715

W

R 1

-5V

LD 2

-5V

3

XTAL2

XTAL1

4

5

+5V

CLK 6

KL5 7

+5V 3.579545 MHz

Fig. 3.8 Hardware circuit diagram and internal structure of LMF90.

3.5 Results The circuit was then tested with the center frequency set to 50 Hz to remove the power-line interference. Fig. 3.9 shows the waveform of a 100 Hz input signal and the corresponding output of the filter. Then, the input frequency was changed to the center frequency of the notch; 50 Hz. The filter should not allow the signal to pass as its frequency is in the rejected bandwidth; the signal must be distorted and attenuated as much as possible. Fig. 3.10 shows the 50 Hz input signal and the notch output waveforms.

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Fig. 3.9 The input and output waveforms of the notch filter with input signal frequency of 100 Hz.

Fig. 3.10 The input and output waveform of the notch filter with input signal frequency of 50 Hz.

The notch filter circuit was then tested at various frequencies and the corresponding frequency response is shown in Fig. 3.11. At the center frequency of 50 Hz, the signal is maximally attenuated with a gain of approximately -40 dB. Table 3.1 shows the filter characteristics at the same range of frequencies.

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Gain (dB)

5 0 -5 -10 -15 -20 -25 -30 -35 -40 0

20

40

60 80 Frequency (Hz)

100

120

Fig. 3.11 Frequency response of LMF90 notch filter.

TABLE 3.1 FILTER CHARACTERISTICS WITH CENTER FREQUENCY OF 50 HZ. Frequency (Hz) Gain (dB) 10 -0.20123 20 -0.06656 30 -0.06656 40 -0.06656 45 0.396685 46 0.15793 47 -0.49179 48 -4.32941 49 -15.0934 50 -37.9525 51 -11.0453 52 -2.82658 53 0 54 0.550421 55 0.469622 56 0.313039 57 0.23583 58 0.080055 59 0.159379 60 0.202793 70 0.132612 80 0.066053 90 0.263229 100 0.19667

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3.6 Conclusion The chosen notch filter IC was simulated and tested practically for input signals with the same amplitude and frequency of an EEG signal and the power-line interference. Test results showed that it removed the 50 Hz power-line signal. So, the notch filter chosen is suitable for this project application.

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Chapter 4 Variable Gain Amplifier

4.1 Introduction A variable gain amplifier or VGA is a signal-conditioning amplifier with an electronically settable voltage gain. There are two types of VGAs; analog variable gain amplifiers and digital variable gain amplifiers (DVGAs). In analog VGAs, an analog voltage controls the gain by either a functional source, a digital to analog converter or a dc source. The gain of analog VGAs is measured in dB and is considered as a linear function of the input voltage. With DVGAs, the gain is controlled by a binary code or digital word applied to a digital port or register. In phase I of the project, the chosen IC was AD8369 which is a digitally controlled VGA. But this IC was not working so it was replaced by another VGA. The replacement VGA is AD8230 which is the instrumentation amplifier of the system design. However, since this IC has an adjustable gain and will be used with single input it can be considered as an analog variable gain amplifier. One VGA will be used in the system with gain 220.

4.2 Simulation A simulation was done for the VGA using MATLAB Simulink software. The VGA was modeled as a gain block in series with a low pass filter block, as shown in Fig. 4.1. The specifications of the VGA are mainly the gain which is 100 and the gain bandwidth which is 2.3 kHz. The inputs of the VGA are a sinusoidal input and the input referred noise which was modeled as white noise with amplitude of 3 µVpp. The input and output signals are shown in Fig. 4.2 and Fig. 4.3, respectively.

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Fig. 4.1 VGA model using simulink.

Fig. 4.2 Input signal of the VGA using simulink.

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Fig .4.3 Output signal of the VGA using simulink.

4.3 Hardware Circuit and Settings The circuit implemented for unit testing is shown in Fig. 4.4. RF and RG are the gain setting resistors. The gain can be adjusted according to equation (2.1).

Fig. 4.4 Circuit implementation of VGA.

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4.4 Results The gain of the VGA during hardware testing was set to 100. To obtain this gain, RF was set to 8.2 kΩ and RG was set to 162 Ω. Input and output signals of the VGA are shown in Fig. 4.5.

Fig. 4.5 Input and output signals of the VGA with gain=100.

4.5 Conclusion In this chapter, the VGA was modeled and simulated using Simulink and was also tested practically. It was verified from the simulation and tests that the VGA is working properly and can be connected to the other blocks of the system.

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Chapter 5 Low Pass Filter

5.1 Introduction The low pass filter is one of the building blocks of the proposed design. It is used mainly to remove the high frequency components and smooth out the desired signal. The chosen IC during Phase I was the LTC1064-2. However, after testing the IC and connecting it to the system it was found that this IC was not suitable for this application. The generated noise in the low frequency band was very high. The only solution due to the limited time was to build a Sallen-Key low-pass filter with the desired cutoff frequency.

5.2 Simulation The low pass filter LTC1064-2 was simulated using Simulink. Fig. 5.1 shows the system with the added noise components generated from the block itself and the environment. The input is a sinusoidal signal of frequency 100 Hz. Also, the input referred noise of the block with 80 µVrms is added to the input signal. In addition, random high frequencies generated from the surrounding is added which the low pass filter will remove.

Fig. 5.1 Low Pass Filter LTC1064-2 Simulink model.

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The following figures show the output of each Power Spectral Density block in the system.

Fig. 5.2 Waveform and spectrum of input signal (PSD1).

Fig. 5.3 Waveform and spectrum of LPF referred noise (PSD2).

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Fig. 5.4 Waveform and spectrum of random high frequency noise (PSD3).

Fig. 5.5 Waveform and spectrum of signal and total noise added (PSD5).

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Fig. 5.6 Waveform and spectrum of the LPF output (PSD4).

The frequency response of the low pass filter was obtained using linearization and is shown in Fig. 5.7.

Fig. 5.7 Bode and phase plot of LPF simulation.

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5.3 LTC1064-2 Circuit and Settings LTC1064-2 is an 8th-order Butterworth low pass filter. To set-up the cut-off frequency, a clock is generated with fclk : f-3dB = 100 : 1. The cut-off frequency used is 200 Hz since the maximum EEG signal frequency is 100 Hz. Therefore, a clock with frequency of 20 kHz is needed. Power supply used is ±5V. Fig. 5.8 shows the hardware circuit implementation of the low pass filter block. The external clock was built using a 555 timer. To set the frequency, the following equation was used f=

(5.1)

5V

5V

Vin

0.1μF

0.1μF

LTC1064-2

Vout

0.1μF

Fig. 5.8 Hardware circuit implementation of the LTC1064-2 LPF.

5.4 LTC1064-2 Test Results In the testing process, the cut-off frequency was adjusted to 200 Hz the same frequency of the proposed design. Fig. 5.9 shows the waveform of a 100 Hz input signal and the corresponding output of the filter. Then, the input frequency was increased to above the cut-off frequency; 300 Hz. The filter should not allow the signal to pass as its frequency is above the cut-off frequency; the signal must be distorted and attenuated as much as possible. Fig. 5.10 shows the 300 Hz input signal and output waveforms. The corresponding frequency response of the filter is shown in Fig. 5.11 and Table 5.1 shows the readings.

26

Fig. 5.9 The input and output waveforms of the LPF with input signal frequency of 100 Hz.

Fig. 5.10 The input and output waveforms of the LPF with input signal frequency of 300 Hz.

The low-pass filter circuit was then tested at various frequencies and the corresponding frequency response is shown in Fig. 5.11. At the cut-off frequency of 200 Hz, the signal is attenuated by approximately 3dB. Table 5.1 shows the filter characteristics at the same range of frequencies.

27

Fig. 5.11 The Frequency response of LTC1064-2 with cutoff frequency of 200 Hz.

TABLE 5.1 LTC1064-2 FILTER CHARACTERISTICS Frequency (Hz)

Gain (dB)

10 15 20

0.088097197 0.253468963 0.004174905

25 30 35 40 45 50 55

-0.079706864 -0.161275614 -0.161275614 0.004135153 0.004096152 0.004096152 -0.159754419

60 65 70

0.004096152 -0.07819617 -0.161275614

75 80 85 90

-0.07819617 -0.07894429 -0.161275614 -0.161275614

95 100 110 120

-0.161275614 -0.161275614 -0.240553975 -0.240553975

130 140

-0.240553975 -0.240553975

150 160

-0.240553975 -0.407515187

28

170 180 190 200 300

-0.831440361 -1.374202409 -2.053512466 -3.358028702 -20.32474398

400 500 600 700 800 900

-24.41020798 -25.18550495 -25.02465055 -25.02465055 -25.02465055 -25.18550495

After connecting the overall system, the LPF block was seen to generate high amplitude noise, which is unsuitable for this application as seen in Fig. 5.12.

Fig. 5.12 The input and output waveforms of LTC1064-2 with input signal frequency of 100 Hz.

5.5 Sallen-Key Design and Circuit Implementation A Sallen-Key fourth order low pass Butterworth filter was then designed with a cut-off frequency of 120 Hz. This cut-off frequency was chosen, as the maximum frequency present in the EEG band is 100 Hz. This fourth order filter was realized by cascading two second order low-pass filters. The circuit was built with TL081 opamps. Power supply used is ±5V. Fig.5.13 shows the hardware circuit implementation of the low pass filter circuit.

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R3

R3

+5V +5V R4

VIN

R4

TL081CN R1

TL081CN

R2 C1

R1

R2

C2

VOUT

C2 C1

-5V

-5V

Fig. 5.13 Hardware circuit implementation of 4th order Sallen-Key LPF.

To set the cut-off frequency of this circuit, equation 5.2 is used. To get f=120 Hz, the following values were set. R= R1= R2= 13.2 kΩ, and C= C1= C2= 0.1μF.

f=

(5.2)

To design a stable fourth order low pass Butterworth filter the quality factor of the first stage Q1 has to be equal to 0.541 and the quality factor of the second stage Q2 has to be equal to 1.307. The gain for each stage can be calculated using eq. 5.3. The gain of the first stage K1 will be equal to 1.152 and the gain of the second stage K2 will be equal to 2.235. The general transfer function of a fourth order Sallen-Key low pass filter is shown in eq. 5.4. (5.3)

(

)

(

)

(

)

(5.4)

5.6 Sallen-Key Test Results The system was then tested and various frequencies. Fig. 5.13 shows the waveform of a 100 Hz input signal and the corresponding output of the filter. Then, the input frequency was increased to above the cut-off frequency; 500 Hz. The filter should not allow the signal to pass as its frequency is above the cut-off frequency; the signal must be attenuated as much as possible. Fig. 5.14 shows the 500 Hz input signal and the LPF output waveforms. The corresponding frequency response of the filter is shown in Fig. 5.15 and Table 5.2 shows the readings.

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Fig. 5.14 Input and output waveforms of the 4th order Sallen-Key LPF with a 100 Hz input frequency.

Gain (dB)

Fig. 5.15 Input and output waveforms of the 4th order Sallen-Key LPF with a 500 Hz input frequency.

20 10 0 -10 -20 -30 -40 -50 0

200

400

600

800

1000

Frequency (Hz) Fig. 5.16 Frequency response of a 4th order Sallen-Key LPF with 120 Hz cutoff frequency.

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TABLE 5.2 SALLEN-KEY LPF FILTER CHARACTERISTICS

Frequency (Hz) 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 110 120 130 140 150 160 170 180 190 200 300 400 500 600 700 800 900 1000

Gain (dB) 7.617495868 7.617495868 7.617495868 7.617495868 7.617495868 7.617495868 7.617495868 7.617495868 7.617495868 7.617495868 7.617495868 7.517465323 7.416269347 7.416269347 7.313880465 7.210270215 7.105409106 6.891810893 6.635787189 6.295120403 5.654395763 4.547826501 3.113962008 1.793566008 0.235830495 -1.605966005 -2.895509281 -4.410453171 -6.246639537 -7.325073105 -22.05856093 -29.86716907 -34.72793005 -37.82596925 -39.76416951 -40.08005485 -40.57652652 -43.60188003

5.7 Conclusion In this chapter, the LPF was modeled and simulated using Simulink and was also tested practically. It was verified from the simulation and tests that the SallenKey LPF is working properly and can be connected to the other blocks of the system.

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Chapter 6 Overall System Design

6.1 Introduction After unit testing of each block of the proposed design, the overall system was linked, simulated and implemented. The overall system design is shown in Fig. 6.1. The overall gain was fine tuned after practical testing to get the desired output voltage amplitude (1-5 V).

Fig. 6.1 Overall system block diagram.

6.2 Simulation The overall system was simulated using Simulink. Fig. 6.2 shows the system with the added noise components and interferences. The input is a sinusoidal signal of frequency 100 Hz. The input referred noise is added before each stage for the corresponding blocks.

Fig. 6.2 Overall system Simulink model.

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The input to the instrumentation amplifier is shown in Fig. 6.3.

Fig. 6.3 Waveform and spectrum of the instrumentation amplifier input.

The following figures show the output of each Power Spectral Density block in the system.

Fig. 6.4 Waveform and spectrum of the instrumentation amplifier output.

34

Fig. 6.5 Waveform and spectrum of the notch filter output.

Fig. 6.6 Waveform and spectrum of the variable gain amplifier output.

35

Fig. 6.7 Waveform and spectrum of the low pass filter output.

6.3 Hardware Circuit and Settings After simulation of the overall system, it was linked and implemented on a breadboard. The system was then tested on several subjects. The output of each block was displayed using an oscilloscope.

Fig. 6.8 Overall system circuit implementation.

36

6.4 Beta Testing The output of the electrode is shown in Fig. 6.9. The signal shown is the desired EEG signal added to the composite noise; which consists of the 50 Hz powerline interference and other random noise.

Fig. 6.9 Waveform of the electrode output signal.

Fig. 6.10 shows the output of the instrumentation amplifier. It is clear that the random noise was reduced; however the 50 Hz interference remains.

Fig. 6.10 Waveform of the IA output signal.

37

Next, the output of the notch filter is displayed in Fig. 6.11. It is clear that the 50 Hz interference was removed by the notch filter. However, a DC shift was carried from the IA and added to the notch filter stage. The output of the notch was connected to the VGA, but there was no output present. This is because the VGA has limits to the input voltage and the presence of the DC shift blocked the signal from passing.

Fig. 6.11 Waveform of the notch filter output signal.

To solve the DC shift problem, a high pass filter was connected after the notch stage. This filter with cut-off frequency of 1 Hz was able to block DC signals. The output of the high pass filter is shown in Fig. 6.12.

Fig. 6.12 Waveform of the high pass filter output signal.

38

Fig. 6.13. shows the output of the VGA stage.

Fig. 6.13 Waveform of the VGA output signal.

The final stage is the low-pass filter and its output is shown in Fig. 6.14. The signal is smooth and free from high frequency noise; the desired EEG signal has been extracted.

Fig. 6.14 Waveform of the low-pass filter output signal.

39

The output was also displayed using LABVIEW software. This was done using a DAQ assistant module. One analog input channel was used to display the lowpass filter output. Testing results for several subjects are shown in the following figures.

Fig. 6.15 Subject 1 EEG waveform.

Fig. 6.16 Subject 2 EEG waveform.

40

Fig. 6.17 Subject 3 EEG waveform.

Fig. 6.18 Subject 4 EEG waveform.

41

Fig. 6.19 Subject 5 EEG waveform.

The obtained EEG waveforms were then compared to actual Beta signals. Fig.6.20 shows a Beta waveform which looks similar to the extracted signals.

Fig. 6.20 Beta waveform [10].

6.5 Overall System Specifications Several specifications of the overall system were calculated. The overall gain of the EEG system is approximately 77 dB. The total noise was found to be 14.05 mV.

42

6.6 Conclusion In this chapter, the overall system was modeled and simulated using Simulink and was also tested practically. It was verified that the overall system is working properly and later was tested on several subjects. The obtained EEG waveforms were shown to be similar to beta signals.

43

Chapter 7 Challenges, Constraints and Future Work

7.1 Introduction As with any project, the system design has limitations. During the implementation process, several issues arose. In this section, the challenges faced and the project constraints will be discussed.

7.2 Challenges The first problem occurred before the implementation process, when the components first arrived. The instrumentation amplifier and variable gain amplifiers were of the surface mount type and less than 10 mm in length. This SOIC configuration was not suitable for breadboard testing. The solution was to purchase adapters and solder the ICs on the adapters. Finding the suitable adapters in the region was a difficult task and had to be ordered from abroad. The next problem was with the VGA from the proposed design in Phase I. The ICs arrived faulty and did not work during testing. The VGA was then replaced by an analog VGA that has been discussed earlier in chapter 4. After that, another problem was encountered. The VGA had a limit to its voltage input, and a DC shift was carried with the input signal so the VGA did not allow it to pass. The solution to this problem was to build a DC blocking high pass filter. The last block in Phase I of the project was the ADC AD7091. However, the IC was unsuitable for breadboard testing and no adapters for it were available. The alternative IC ordered was the ADS7841. Programming this ADC was dependant on the type of digital processor connected to it and its internal clock frequency. Since the project has no digital signal processor, the suggested solution was to use software instead of the ADC. The software used was LABVIEW and the system was connected to it via Data Acquisition module (DAQ).

44

7.3 List of Constraints There are several limitations of the design. As this system is a one channel EEG acquisition, the extracted information is limited. Since multi-channel system use the basis of averaging the inputs, it gives more accurate results. As the electrode gel tends to dry out, the EEG system recording time is limited. Also, since the electrodes are of the wet type, they need to be replaced regularly.

7.4 Future Work This system can be further improved by converting it into a multi-channel EEG system. A transmitter block can be added to the design; it can be used to transmit the extracted EEG signal recordings. A digital signal processor can also be added to apply digital signal processing on the extracted EEG signal and use it for biomedical applications.

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Chapter 8 List of Parts and Actual Cost

8.1 Testing Cost Testing cost is different from the actual cost of the system. It is more costly because extra items were used only for testing. This includes the adapters used for the ICs and the soldering price. TABLE 8.1 PARTS LIST AND COST OF THE SYSTEM FOR TESTING. Parts

Quantity

Supplier

ECG tab electrodes

150 pcs

Al Madam Medical Supplies

Estimated Budget (AED) 105

ECG leads set

1 pcs

Coast and Middle East Electronics

224

AD8230

2 pcs

RS Installations Middle east

80

Adapter for AD8230

2 pcs

AlMuhairi Scientific and Technical Supplies

200

LMF90

1 pcs

AlMuhairi Scientific and Technical Supplies

75

Total Cost

684

8.2 Actual Cost The actual cost is less expensive than the testing cost since a PCB was used to implement the system. So, there is no need to use adapters for the ICs and no soldering cost will be added.

46

TABLE 8.2 PARTS LIST AND ACTUAL COST OF THE SYSTEM. Parts

Quanti ty 50 pcs

Al Madam Medical Supplies

Estimated Budget (AED) 35

ECG leads set

1 pcs

Coast and Middle East Electronics

224

AD8230

2 pcs

RS Installations Middle east

80

LMF90

1 pcs

AlMuhairi Scientific and Technical Supplies

75

ECG tab

Supplier

electrodes

Total Cost

414

47

Conclusion In Phase II, the system that was designed in the first phase was modeled and simulated. Then, the system was unit tested to make sure each stage worked properly. After unit testing several issues were encountered and changes were made to the original design. The overall system was then linked and tested. The design was then fine-tuned to suit the practical results obtained with actual EEG signals.

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References [1] G. Cauwenberghs, “Integrated Circuits and Electrodes Interfaces for Noninvasive Physiological Monitoring,” IEEE Transactions on biomedical engineering, VOL.61, NO.5, May 2014. [2] P. Tallgrena and S. Vanhatalo, “Evaluation of commercially available electrodes and gels for recording of slow EEG potentials,” Elsevier Science Ireland Ltd, 2005. [3] M. A. Lopez-Gordo, “Dry EEG Electrodes,” MDPI, Basel, Switzerland, Rep. 14( 12847-12870), 2014. [4] M. Puurtinen, “Measurement of noise and impedance of dry and wet textile electrodes, and textile electrodes with hydrogel” the 28th IEEE EMBS Annual International Conference, 2006. [5] R. Oostenveld and P. Praamstra, “The five percent electrode system for high-resolution EEG and ERP measurements,” Elsevier Science Ireland Ltd, 2001. [6] www.en.wikipedia.org/wiki/10-20_system_%28EEG%29 [7] www.en.wikipedia.org/wiki/Beta_wave [8] www.quora.com/Why-is-a-typical-EEG-reference-placed-on-mastoids-ears-or-nasion-as-opposedto-something-more-inert [9]www.ee.ic.ac.uk/pcheung/teaching/ee2_signals/Lecture%209%20%20Poles%20Zeros%20&%20Filters.pdf [10] http://www.infiniteminds.info/Learning-2.0/Brainwave-Entrainment/Understanding-Brainwavesand-Mental-States.html

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Appendices 1) AD8230 2) LMF90 3) TL081CN

50

AD8230

51

LMF90

52

TL081CN

53