th
Proceedings of the 19 International Conference on Automation & Computing, Brunel University, London, UK, 13 - 14 September 2013
Design and Implementation of an Optimal Battery Management System for Hybrid Electric Vehicles Mark Bowkett, Kary Thanapalan, Thomas Stockley, Mark Hathway, Jonathan Williams Centre for Automotive & Power System Engineering (CAPSE) Faculty of Computing, Engineering and Science University of South Wales Pontypridd CF37 1DL, United Kingdom
[email protected] Abstract— This paper investigates the design of an optimal battery management system for hybrid electric vehicles to allow performance improvements. Battery management systems are an important subsystem for hybrid electric vehicles, which ensure that the batteries are operating within the specified safe operating conditions. Thus, the design of a battery management system plays an important role on battery life preserving and performance improvement of hybrid electric vehicles. Battery management systems are affected by many factors and the key one being cell unbalancing. This paper presents an overview of different cell balancing topologies and their impact on system performance. Furthermore, the application of cell balancing topologies for Lithium-ion battery pack with the view of improving battery management systems for the hybrid electric vehicles is also investigated. Real-time implementation of an optimal battery management system is discussed with references to the University of South Wales (USW) hybrid electric vehicles. Keywords - hybrid electric vehicles; battery management system; cell balancing; modelling and simulation.
I.
INTRODUCTION
Range limitations of hybrid electric vehicles (HEV) and electric vehicles (EV) require new approaches to over-come usability restraints [1]. One of the solutions is to design and implement an optimal battery management system (BMS). By doing so, it will not only increase the range of the vehicle but also increase the reliability of the entire vehicle system. Battery management systems are an important subsystem for hybrid electric vehicles, which ensures that the batteries are operating within the specified safe operating conditions [2], [3]. Thus, the design of the battery management system plays an important role on battery life preservation and performance improvement of hybrid electric vehicles. The advances in lithium-ion battery technology make it possible to power light-duty vehicles by using only electric power stored in a battery (collection of cells). HEV and EV are starting to play important roles in the trend towards vehicle electrification, which is of major interest to the automotive industry. In such trends towards vehicle electrification it is of special importance to the automotive industry that battery endurance will guarantee
its proper function over a broad range of environmental and operational variations. Therefore the knowledge of battery life and degradation becomes crucial to vehicle performance and perceived vehicle quality. The BMS performs many tasks including the measurement of system voltage, current and temperature, the cells’ state of charge (SOC), state of health (SOH), remaining useful life (RUL) determination, controlling and monitoring the charge / discharge characteristics and cell balancing [4] – [7]. SOC refers to the amount of remaining charge in a battery which provides the user with vital information on system run-time before a battery recharge is required. In an EV the SOC information is presented as the fuel gauge. SOH refers to the amount of degradation that has occurred in a battery compared to the beginning of life [8], [9], and [10]. The main purpose of the paper is to employ an optimal BMS design for HEV and EV systems. This paper begins with a discussion of cell balancing techniques and this is followed by the design and implementation of BMS into University of South Wales (USW) hybrid electric vehicles (Fig.1) and electric vehicles.
Figure 1. University of South Wales hybrid electric vehicles
II.
CELL BALANCING
Cell balancing is one of the main functions of a BMS. A balanced battery is one in which at some state of charge, all the cells are exactly at the same SOC. The cells in a battery may be unbalanced in multiple ways, including; SOC, self discharge current, internal resistance and capacity [11]. The point of balancing is to maximize the charge that the battery can deliver, limited only by the cell with the lowest capacity. The balancing topologies can be broadly categorised as passive and active balancing [4]. A. Passive cell balancing topologies
Figure 3 illustrate the active cell balancing topologies principles. Active cell balancing circuits sample all cell voltages, but improve upon the passive technique by calculating the mean value of the cells then transferring the charge from the cells over this mean value to the cells under the mean value. Simply put this equalizes higher potential cells with that of the lower potential cells resulting in no waste, the only actual losses in such a system are from those within the active balancing electronics itself. Active balancing can be sub divided into further topologies such as capacitor and/or inductive component as well as controlling switches or converters [19] – [26]. III.
Figure 2. Passive balancing Passive balancing circuits perform their task by sampling all cell voltages, determining the lowest voltage cell within the stack and leveling all remaining higher voltage cells to this level by removing charge from these higher potential cells [4] – [7]. This is illustrated in Figure 2; where the 3 left most cells are unbalanced and the result of passive balancing is shown on the 3 cells to the right. This process is easily implemented, low cost and reliable, it is however wasteful and due to its discharge method it can generate large amounts of unwanted heat that must be dissipated within what is usually a sealed battery pack [12] – [18]. Such a method is slow to equalize and requires large areas of PCB real estate to allow for typically surface mount resistor cell load heat dissipation. A.1 Novel improvement solution A novel and simple circuit design has been researched and developed into improving passive circuits with minimal cost which can be retro fitted to existing units. The tests were carried out in the CAPSE labs at the University of South Wales and functional prototypes were designed and proved successful. Further design enhancements have been investigated for implementation in HEV. B. Active cell balancing topologies
Figure 3. Active balancing
BMS DESIGN FOR HEV
The complete battery management system is divided into two discrete physical units; monitoring and control, alternatively slave and master respectively [27], [28]. A single master PCB can control many slave boards. This design approach improves flexibility when compared to the single board master/slave PCB circuits and therefore extends the range of device solutions where the battery management system can be employed. This has benefits in terms of cost, expandability and reliability. The software architecture includes a persistent storage method where key control information is held in flash EPROM storage which is user accessible via a PC program; this allows a technically competent person to easily setup the battery management system to the requirements of their product without the need for the common fixed bespoke BMS design. Such required information includes but is not limited to; minimum and maximum voltage limits of the individual cells as given by manufacturer datasheets, number of cells in the system, discharge trigger margin value (maximum amount of potential difference between cells), over / under voltage warning limits, CAN bus messages etc. This design approach allows for tailored style functionality within the generic design and an easy means to expand or reduce storage capacity as to the requirements of the end user. This is all achieved by including the necessary expandability through low cost and a low component part count. The BMS slave boards can take a maximum of 12 cells (per individual board) provided the collective voltage does not exceed 75V. Practically the minimum cell count is 1 although this is determined by the voltage sum, as the slave boards require at least 10V to operate reliably. Provided these electrical requirements are met then any cell chemistry and arrangement can be managed [29]. Operations of such slave boards include monitoring of each individual cell with a single 12 bit sigma delta ADC that is multiplexed to the 12 individual cells. The sigma
delta ADC offers high resolution with a least significant bit voltage (resolution) of 1.5mV. This type of analogue to digital convertor (ADC) has low cost and distinct advantages over successive approximation register (SAR) convertors when in noisy environments as characteristically seen in the automotive industry [30]. Balancing occurs by turning on the associated MOSFET to the over voltage out of balance cell(s), this switches in a resistive load which discharges the cell and dissipates the energy as heat thus making the slave boards passive in operation. When not sampling the slave boards drop into an ultra low standby mode which reduces the supply current to approximately 12uA which relieves power consumption of the managed cell array. Currently 16 slave boards or 192 individual cells can operate from a single master board although this is further expandable with minor software modifications (beyond specification of the intended applications). For hardware redundancy it is necessary to be able to selectively communicate to individual slave board integrated circuits (IC’s), this is achieved via an electrically isolated addressable SPI bus compatible serial port. The addressable design allows for chip level redundancy should an IC fail on the slave board it is possible for a reserve IC to take over [27], [29]. SPI communications is shared through a single bus to minimize what would otherwise be a potentially highly complicated electrical wiring loom this greatly reduces manual labor during manufacture and reduces servicing / repair time of the packaged battery units. Mechanical interconnects are also reduced and reliability is therefore increased through simplicity. Slave board IC’s also incorporate watchdog timers; when triggered will reset any discharging cells to a non discharging state should any SPI bus communications be absent for periods of time between 1 to 2.5 second, this gives the best fail safe condition possible for the system. Each slave board has provision for 8 external independent 10k Ohm negative temperature coefficient thermistors with an independent onboard IC die temperature sensor, giving a total of 9 independent sensors. These are used to check cell stack temperatures are within healthy operating limits. The Master controller can at pre determined intervals take self test values of each slave board IC to check for correct operation, self tests check the slave board IC registers by clearing cell voltage and temperature registers to 0xFFF this is used to check that the slave board is accepting commands and performing new measurements. Other self tests verify the functionality of the digital portions of the ADC. Here a known internal voltage signal is applied to the ADC, if the ADC circuitry is functioning correctly the registers will contain known data that relates to the input
test voltage, this can be used to flag up any discrepancies and therefore highlight a potentially flawed IC. Self checks also include open wire faults, where a cell sensor cable is detected should it become lacerated or disconnected due to vibration or similar rigorous environmental conditions. Should the BMS or associated components fail it can be extremely difficult to diagnose its cause. For this reason a comprehensive list of error flags are stored on compact flash card (CF) along with a log of cell charge history including time stamps. Due to the relatively large amounts of data required for recording every cell in the system a rolling window is implemented where previous data is over written by new. However should a serious fault flag be set then the data window will be stopped to preserve the most important information, that is the data leading up to the event that resulted in the serious error. Error Flags are included and maintained in CF as the BMS can be powered from the monitored cell stacks, should an error be serious enough to cause a power loss any data in non volatile memory will be lost. Fault flags have associated time stamps, this allows a piece by piece examination of faults to be carried out in real time after the error but requires minimal information to be stored. Fault flags include breaches in max and min cell voltages, disconnected wires, ADC faults, over / under cell temperature limits, pack over current and more. Data transfers between master and slave boards consist of 8 bit bytes with most the significant bit (MSB) being transferred first. Data writes are latched into the slave on the rising edge of SCKI (clock). Data reads are read during the falling edge of SCKI. The chip select pin (CSBI) is held low during such reads and writes. To ensure data integrity has been maintained during transmissions a cyclic redundancy check (CRC) value is calculated and attached to the end of transmissions. The initial PEC value of 01000001 (0x41) is used and the polynomial is as follows: 1
(1)
The master controller has capacity for a current transducer based on the hall effect principle, chosen due to its galvanic isolation for improved safety. This component provides essential information of the overall pack state which determines if it is in a discharge or charge state. The most accurate time to measure cell charge states which feeds the master controller control strategy algorithm is when the pack is in a state of rest and the cells have relaxed. It is for this reason that the current transducer is present in the design as well as monitoring total current which can be throttled back should the battery pack come near to the maximum operating temperature [27] – [33].
A. Experimental setup The vehicles studied in this paper are the University of South Wales HEVs (Fig.1) and EVss (Fig.4). Optimal BMS designs are widely perceived as an important technology for HEVs and EVs. Heree we describe the development of a simple but optimal BMS design for the HEVs and EVs.
Not included in the design but noted as a worthy addition is the use of an overseer or suppervisor IC. Such a device would fortify the current systeem should ultra reliability coupled with extra traceabilityy of faults be required. The device should ideally be suppllied from a separate power supply or have capacity for maintaining m its own supply for a suitable duration of timee, it should be capable of logging the master controllerss power supply and heart beat signal. This will allow w for an insight into the environmental changes the maaster controller is subjected to during operation and certainlly during faults.
Figure 4. EV for BMS system im mplementation A block diagram of proposed BMS design is shown in Fig.5. This BMS design (Fig.6) providees the basis for the future advanced design, analysis andd improvement of BMS for HEV/EVs and other applicatioons.
Figure 7. Testing of BMS for HEV/EVs Fig.7) were carried out with Both bench and real life tests (F the battery management system m described above. It has the flexibility and scalability beyyond the range of simply hybrid electric vehicles. The BMS system has beenn implemented on a small people carrier as shown in Figuure 4; initial testing was set up on a bank of 44 cells whose chemical composition was lithium-ion. The BMS impllemented in this design contained a single master conntroller unit with 4 slave boards, 3 monitoring 12 cells annd a unit monitoring 8 cells which covers the complete 44 liithium cells onboard.
Figure 5. BMS system foor HEV
Besides the control aspectt of the BMS an absolute necessary requirement is the display d of critical data such as state of charge, remaining miles, m low charge alerts and fault flags. Depending on how w the user will display this information (existing clocks inttended for the use in purely combustion engine propelled vehicles v or bespoke clocks with either analogue or digitall interfaces) will determine the output signals from the conntrol board, as these could be CAN messages, analogue leevels or digital signals. It is a necessary requirement and shhould not be overlooked or under estimated as errors (typpically in estimating SOC) here will give an impractical user experience that will render the BMS useless desppite an otherwise perfectly engineered battery managementt system. Mechanically the BMS annd components should be designed to automotive stanndards due to the harsh conditions the units will be subjjected too.
Figure 6. Simple BMS deesign
IV.
CONCLUSION
In this paper design and implementation of an optimal battery management system for HEV system is described. An overview of passive and active cell balancing topologies and their impact on system performance are also discussed. The application of cell balancing topologies for Lithium-ion battery pack is carried out and the BMS is implemented in USWHEVs. REFERENCES [1]
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