Design and Implementation of Digital Echo Cancellation OnChannel Repeater in DVB-T/H Networks Yue Zhang1, KoK-Keong Loo1, John Cosmas1, Maurice Bard2, Jeff Gledhill3 1
School of Engineering and Design, Brunel University, Uxbridge, UB8 3PH, UK 2 Broadreach Systems, Devon, UK 3 Videsco, UK Email:
[email protected]
Abstract This paper is to investigate the hardware design and implementation of digital echo cancellation on-channel repeater (DECOCR) in DVB-T/H networks. There is a need for high isolation between transmitter and receiver antennas for on-channel repeater (OCR) to minimize feedback from the antenna coupling and to keep the system stable. Therefore, the adaptive echo canceller is to remove the echoes between the transmitter and receiver antennas in OCR to minimize the coupling. The design and implementation of DECOCR is based on the algorithm of echo cancellation by channel equalization. The paper will investigate the design and implementation of DECOCR based on digital signal processing (DSP) in FPGA device. The most important issues considered are to get shortest system process delay, highest SNR output and highest echo rejection rate. The laboratory measurement results show that the presented repeater can get up to 29dB echo cancellation and about 1us process delay with robust stability. The work in this paper was supported by the European Commission IST project – PLUTO (Physical Layer DVB Transmission Optimization)
to get high SNR baseband DVB-T/H signals. The most important item in DECOCR is the adaptive echo equalization filter. The DECOCR contains the shortest delay complex equalization filter with a novel structure. The proposed equalizer can cancel the echoes in the received multipath signals effectively to minimize the coupling loop interference and get better MER (Modulation Error Rate). Furthermore, the latency of the whole process is surprisingly short when employing a carefully designed equalization filter scheme. Furthermore, the channel estimation with Constant Amplitude Zero Autocorrelation (CAZAC) sequences is also implemented in FPGA. The channel estimation implementation is based on 1024 points FFT and IFFT. The estimation process is average over from 4 to 32 FFT frames. The performance of channel estimation in hardware is evaluated by different channels based on the mean error between actual channel and estimated channel with different signal noise ratio (SNR) level.
Keywords On-Channel Repeater, Echo Canceller, DECOCR, FIR, FPGA DSP CAZAC DVB-T/H 1. INTRODUCTION To extend the coverage of the DVB-T/H networks, repeaters were proposed for rural and suburban environments [1]. The main purpose of an on-channel repeater (OCR) is to enlarge the coverage of DVB-T/H [2][3] network. An on-channel repeater receives a signal from a distant transmitter and re-broadcasts an amplified version of it on the same frequency in single frequency network (SFN). COFDM systems such as DVB-T/H are specifically designed to work in the presence of strong echoes [4][5]. This opens the possibility of implementing an OCR which works by receiving the signal off air, amplifying it and then retransmitting it on the same frequency [6-8]. This paper will investigate the design and implementation of DECOCR based on digital signal processing (DSP) in FPGA device. The hardware structure is based on figure1. According to Figure 1, DECOCR contains low noise DDC, DUC and Low pass filter (LPF)
Figure 1. Hardware structure of digital echo cancellation on channel repeater
The performance of DECOCR is evaluated under various laboratory conditions prior to field test. The laboratory testbed is based on Spirent channel emulator, DVB-T/H modulator and ETX. According to the measurement results, as for a single echo, the DECOCR can get echo rejection rate up to 25dB. When combined with the real-time channel estimation part, the DECOCR can remove the echo up to
29dB. Meanwhile, the latency of the whole signal processing is only 520ns. As for the channel estimation with CAZAC sequences, the absolute error rate between estimated channel in hardware and actual channel versus SNR is provided which showing the channel estimation performance as part of the DECOCR. According to the results, the mean error of channel estimation for RA channel is 1.6e-3 at SNR 24dB and the mean error for TU channel is 9.827e-4 at SNR 24dB. This paper is organized as follows: Section 2 discusses the coupling interference in the on channel repeater for DVBT/H systems and the system design for DEOCR. Section 3 shows the hardware design for the OCR. Section 4 presents the discussions of the measurement results performed in this study. Section 5 is the conclusion according to the design and measurement results. 2.
THE ON-CHANNEL REPEATER AND THE COUPLING INTERFERENCE In this section, the coupling interference of the OCR in DVB-T/H systems will be investigated. Furthermore, the model design of OCR aim to remove the coupling interference is presented in the section as well. 2.1 The Coupling Interference in On Channel Repeater Figure 2 illustrates the principle of an OCR and the case of coupling loop. The receiving antenna of the OCR receives signal from the main transmitter with a level of P. This received signal is filtered in order to remove all the unwanted out-of-band signals. The filtering may include a frequency transposition around an Intermediate Frequency (IF). The signal is then amplified with a gain of G, and it is retransmitted on the same frequency.
Figure 3. Frequency selectivity due to the coupling loop effect in Rician channel
The effect of coupling interference in the frequency domain is as shown in Figure 3 as measured by TDF. Even if the echo remains in the guard interval, the C/N threshold required by the receiver to demodulate the received signal is thus increased and the coverage area is reduced. If the delay introduced by the OCR is larger than the guard interval, the signal may even not be demodulated. 2.2 The Model Design for Digital Echo Cancellation On-Channel Repeater The OCR is an additional transmitter in a SFN DVB network [9][10]. Its output can be modeled as a first high level echo that depends on the actual amplifier gain used followed by a delay cropped or residual cluster of rays. In order to cancel the echo produced by the OCR, we proposed a short delay on channel repeater with echo cancellation. The basic model design is shown in Figure 4. Training Sequence or Reference
Channel Estimator Unwanted Feedback
Taps Rx
Tx FIR Filter
S ∑ Low Noise Amplifier
∑
Power Amplifier
Training Sequence Insertion
Figure 4. The model for digital echo cancellation on channel repeater Figure 2. The coupling interference in on channel repeater
Due to the finite isolation between the transmitting and receiving antennas and the reflections on the nearby environment, the receiving antenna receives several delayed replicas from the repeater's own transmit antenna. These signals correspond to the transmitted signal modified by the transfer function, C, which includes a strong attenuation corresponding to the isolation between the repeater antennas. This leads to the coupling loop interference.
The model is based on an open-loop channel estimator. A low power training sequence such as CAZAC sequence is buried in the transmitted OFDM signal for the unwanted channel estimation based on the correlation principal. The main echo cancellation design issues are the maximum allowable processing delay, the sampling rate used for hardware implementation, the number of filter taps and how it affects the performance. The maximum allowable processing delay of the echo canceller is selected to be below 30% of the guard interval duration. This means that for 2K mode with 7 us guard interval, the maximum
Comment [J1]: Give full name.
allowable delay is around 2 us. This figure impacts the performance of the echo canceller because it sets a limit on the maximum number of taps used by the FIR filter. 3.
HARDWARE CIRCUITS SYSTEM DESIGN FOR THE ON-CHANNEL REPEATER n this section, the hardware circuit system design of DECOCR is presented. The hardware system design is based on Figure 1. The whole system includes receiving subsystem, echo equalization and re-transmitter subsystem. The hardware implementation is based on the Xilinx FPGA Virtex 4. 3.1 Receiving Subsystem Circuit Design The receiving subsystem circuit design is based on Figure 5. The receiving subsystem includes low noise amplifier (LNA), IF down converter, ADC, DDC and low pass antialias filter (LPF). The LNA is used to boost the weak received signal to an appropriate power level for IF down conversion without adding much noise. ADL5530 is used as the LNA. The ADL5530 provided by Analog Device is a broadband fixed-gain, linear amplifier that operates at frequencies up to 1000 Mhz. The gain and noise figure of the LNA are important to determine the noise figure of the receiving subsystem. In this application, ADL5530 can support a gain of stable 16.5dB over frequency with a noise figure of 3dB.
However, LPF is delay component. Therefore, LPF is the optional component for the subsystem. The performance of the receiving subsystem is measured by its ability to select a desired channel in the presence of strong adjacent channels, selectivity, and by its minimum detectable signal and sensitivity. 3.2 Echo Cancellation Subsystem Circuit Design In this subsystem, the main part is the echo cancellation filter as shown in Figure 6. The equalizer in the system is composed of a novel parallel finite impulse response (FIR) filter with auto load coefficients.
Figure 6. Echo Cancellation subsystem
The equalizer is used to compensate for various forms of linear distortions in the received signal. The linear distortions are caused by multipath distortion and coupling loop interference. In order to shorten the process delay for the echo cancellation filter in the whole system, a kind of parallel structure of the FIR filter is presented. There are two parts for the filter. One is the parallel equalizer filter with dynamic coefficients. The other is the coefficients auto-load control circuit. The parallel FIR filter is transpose form FIR filter which have several advantages over direct form structures for high speed and parallel implementation of FIR filter.
Figure 5. Structure of receiving subsystem
The down converter consists of a mixer and local oscillator. The down converter converts the desired RF signal to a fixed IF band with sufficient signal level. The frequency of the IF that involves a trade-off can be chosen by the designer. A high IF leads to better image signal rejection and a low IF need greater suppression of nearby interferes. AD6645 is used for ADC. The maximum clock for ADC is 105Mhz. After the ADC, the digital IF signal is downconverted to near baseband signal. Finally, the near baseband signal is converted to baseband signal by DDC. The LPF is the remove the alias from the baseband signals.
Figure 7. Direct-form FIR
As for the traditional direct form FIR filter shown in Figure 7, the multiplications can be performed in parallel, however the accumulation of the products requires at least log240 adder delays. Therefore, the delay limits the maximum throughput of a parallel implementation. But the transposeform FIR filter structure has several advantages for parallel implementation. The worst case propagation path between delay elements consists of one bus, one multiplier and one adder. The transpose-form FIR filter is also advantageous
for arithmetically efficient implementation. For fixed coefficients and dynamic coefficients, the transpose form FIR filter can get the same performance of direct form FIR. Through simulations and practice, transpose-form adaptive equalizer filter has shown to work with a short delay. In the system, the equalizer filter accepts 14 bit data in and 18 bit coefficients for 40 taps at sample rate 25Mhz. At the output of the filter, the result is rounded to 28 bits. 60 Direct-form FIR FIR complier Distributed arithmetic FIR Transpose-form FIR
50
Samples (Delay)
40
30
Figure 9. Re-transmitter Subsystem 20
10
0
0
5
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25 Taps
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Figure 8. Delay analysis for different FIR filter
From Figure 8, the delay of the transpose-form FIR is shortest delay FIR compared with other FIRs. When the system has 40 taps, the novel transpose-form FIR only gets 4 samples delay; it’s about 160 ns. As for the distributed arithmetic FIR, the delay is 13 samples at 40 taps. As for the traditional direct-form FIR, the delay is 43 samples at 40 taps. As for the FIR complier in Xilinx FPGA, the delay is 44 samples at 40 taps. The coefficients auto-load control circuit is to write the adaptive coefficients into the equalizer FIR. The coefficients must be written into equalizer FIR in a timedelayed manner so that the coefficient at tap n and time m will be used to calculate a new partial sum at position n and time m. The running FIR coefficients and update coefficients are located in different memory. When the load flag is set by the channel estimation circuit, the update coefficients will transfer to the running FIR coefficients memory. The most important is that the transfer process cannot halt the equalizer running. After the testing, the transfer process is adaptive for the equalization process. 3.3 Re-transmitter Subsystem Circuit Design The re-transmitting subsystem design is based on Figure 9. The re-transmitting subsystem includes DUC (digital upconverter), DAC (digital analog converter), IF upconverter, high power amplifier (HPA) and channel filter. DUC is to convert the baseband signal to IF band and.
Then the IF signal is fed into DAC. AD9772 is used for DAC and it can work up to 105MHz. The AD9772 is a single-supply, oversampling, 14-bit digital-to-analog converter optimized for baseband or IF waveform reconstruction applications requiring exceptional dynamic range. Thus the IF signals are up-converted to the RF band that exactly the same frequency as the input RF signal of the DECOCR. Because there are harmonic components at the output of the DAC, these components must be removed at the IF stage. A band-pass filter (BPF) can be used for removing the unwanted signal. After IF up-converter, an HPA is used for amplifying the up-converted RF signal. After HPA, a channel filter is used for removal of adjacent channel in the re-transmitted signal. The channel filter used in the DECOCR must provide proper filtering to meet the RF emission mask specified by the licensed spectrum. 4. MEASUREMNT RESULTS The performance of the designed DECOCR was evaluated via simulations and laboratory tests. The performance of DECOCR is evaluated under various laboratory conditions prior to field trial. The laboratory set-up is based on Figure 10. From the figure, the laboratory set-up can be divided into four sections such as transmitter, channel emulator, DECOCR and receiver.
Figure 10. Laboratory set-up
The transmitter is the MOD-1000 DVB-T/H modulator from Teamcast. The modulator IF signals are at RF UHF band through the up-converter. The channel emulator is the
Spirent wideband channel emulator. It can model UHF channel according COST 207 RA, TU, BU and HT channels. After the noise combiner, the UHF signals will be fed into the DECOCR. The repeater will send the coupling signals back into the input of the repeater after the echo cancellation. The output signal quality from DECOCR was measured with ETX and spectrum analyzer. 4.1 Measurement Results for Channel Estimation There are two different channels to evaluate the performance of the channel estimator in the on channel repeater. One is the three taps FIR channel, the other is the TU12 and RA6 according to COST207 [11].
Figure 12 Estimated channel impulse response (CIR) for the three taps channel profile
The channel estimation result in the on channel repeater is in Figure 12. From the figure 12, the delay between the estimated taps is 160ns. It means the channel estimation works well. The estimator can estimate the correctly delay. As for the amplitude, the estimated taps varies from 0.49 to 0.12. It means there is some noise in the estimation of the amplitude of the channel. Furthermore, there are some side impulse responses beside the main impulse response. These side responses are regarded as the noise for the channel estimation. Therefore, it is very important to take the average of a number of the channel estimation frames.
The three taps FIR channel profile is based on Table I. The actual channel impulse response (CIR) is shown in figure 11. From figure 11, the delay between the each taps is 160ns and the amplitude of the taps varies from 0.5 to 0.2.
TAPS 0 1 2
10
-2
Mean Error
TABLE I POWER DELAY PROFILE OF 3 TAPS Fading/relative Relative delay (us) linear 0 0.5 0.2 0.3 0.4 0.2
TU 1024F FT RA 1024FF T
10
-3
0.5 0.45
5
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S NR (dB )
Relative power
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Figure 13 The absolute error rate of estimated channel and actual channel versus SNR of CAZAC sequence by average of four frames
0.3 0.25
The Figure 13 is the result for the average of four channel estimation frames in TU12 channel and RA6 channel. According to Figure 13, the channel estimation works well at SNR of CAZAC sequences from 10dB to 30dB.
0.2 0.15 0.1 0.05 0
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Figure 11 Actual channel impulse response (CIR) for the three taps channel profile
4.2 Measurement Results for Echo Cancellation The integration measurement is based on the real time channel estimation. The power level of the feedback loop is controlled by the attenuator. The setup configuration is shown in figure 10. The attenuator is changed from 0 dB to 11dB as shown in Table II. According to the different power level of the feedback coupling, the on channel repeater can get the different echo cancellation rate based on the real time channel estimator. TABLE II ATTENUATION FOR THE FEEDBACK RUNS
Attenuation (dB)
1 2 3 4 5 6 7
0 1 2 3 4 6 8
30
8 9
10 11
As shown in Figure 13, there are three echoes in the output of the repeater without echo canceller. The coupling interference causes the three echoes. The main echo is the echo at 1.20us with -8.6dB power. The other two echoes at 2.40us and 3.60 us are the recursive feedback of the main echo. According to figure 14, the on channel repeater gets 27dB echo cancellation with 0 dB attenuation feedback. The main echo is cancelled to -35.1dB and the two minor echoes disappear. It means the channel estimator can correctly get the channel state information. And echo cancellation FIR filter can suppress the echo properly according to the real time channel estimator. Figure 15 the Attenuation of Feedback Level V.S. Echo Cancellation Rate
Therefore, the attenuation vs. echo cancellation rate is shown in Figure 15. From figure 15, the OCR works well with the real time channel estimation (RTCE). When the feedback level is changed from 0dB to 11dB, the on channel repeater can get the echo cancellation rate up to 29dB.
Figure 13 the Output CIR of the Repeater 0dB Attenuation of the Feedback Level without Echo Cancellation
Figure 14 the Output CIR of the Repeater 0dB Attenuation of the Feedback Level with Echo Cancellation
5. CONCLUSIONS It is very difficult to provide full coverage to the public in terrestrial broadcasting. Because of the technical challenges and cost constraints, it is not possible to deploy conventional signal distribution to transmitting stations. In these cases, the on channel repeater is the only viable solution. This paper presented the implementation of digital echo cancellation on channel repeater in FPGA. The hardware design includes the transceiver subsystem, channel estimator and echo cancellation subsystems. This paper also presents a short delay adaptive filter design to achieve the short process delay for the whole hardware system. The paper also proposes a hardware design of channel estimation with CAZAC sequences averaging by IIR filter in the on channel repeater. Furthermore, the paper also provides the measurement results of the performance analysis for the hardware design of the digital echo cancellation on channel repeater. The performance of DECOCR is evaluated under various laboratory conditions prior to field test. According to the measurement results, the DECOCR can eliminate the coupling loop echo up to 29dB combined with the real time channel estimation average. Meanwhile, the whole processing delay is only 520ns. ACKNOWLEDGEMENT The work presented in this paper was supported by the European Commission IST project PLUTO [12]. The authors would like to express special gratitude all the PLUTO project partners for their valuable contributions to the research.
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