Design and Implementations of Linear Congruential ...

International Journal of Electronics Communication and Computer Engineering Volume 5, Issue 4, ISSN (Online): 2249–071X, ISSN (Print): 2278–4209

Design and Implementations of Linear Congruential Generator into FPGA Zulfikar

Hubbul Walidainy

Department of Electrical Engineering Syiah Kuala University, Banda Aceh 23111, Indonesia Email: [email protected]

Department of Electrical Engineering Syiah Kuala University, Banda Aceh 23111, Indonesia Email: [email protected]

Abstract – This paper exposes circuit design of linear congruential generator (LCG) and implementation in FPGA. The circuit is derived from LCG algorithm proposed by Lehmer. Wordlengths reduction technique has been used to simplify the circuit. Several nets connection among the blocks of the circuit are ignored or disconnected. Simulation either behavior or timing have been done successfully. Four best Xilinx chips are chosen to gather comparison data of maximum speed and area occupied. Kintex 7 is the fastest chip among all it is about 309 MHz and Spartan 6 is slowest one which is only 73 MHz. The area occupied is similar among all of the selected chips.

for testing their ideas. Several of these has been realized into hardware and sell into the market [5],[10]. Initially, the algorithm of LCG combined with MonteCarlo method has been used for generating non uniform random numbers using Matlab [11]. After that, we develop the circuit of random number generator and implemented in FPGA [12]. In the paper, the increment factor (c) has been ignored (c = 0). Beside, we present novel design and FPGA implementation of LCG algorithm without ignoring the increment. The rest of this work report are organized as follows. Section II deals with theory of LCG algorithm. The design circuit of LCG for FPGA implementation and nets connections are covered in section III. Section IV provides some implementations data and analysis. Finally, the conclusions are viewed in section V.

Keywords – Linear Congruential Generator, FPGA, Xilinx, word lengths reduction, Kintex.1

I. INTRODUCTION Random numbers have been used in daily activities since long times ago. Nowadays, a small and cheap kid’s toy containing a random number circuit inside it. For example, in a toy like (that mimic) mobile phone will ring different types of sound when the same button is pressed more than one time. Several random numbers theory have been introduced in the last several decades. Linear congruential generator (LCG) that introduced 1954 by Lehmer [1] is the oldest and the most widely used pseudorandom number generator (PNG) [2]. Park & Miller suggest good parameters for LCG [3]. The suggestion is used in Matlab for generating uniform random numbers [4]. Many other random number generators have been proposed and also used in many applications. Blum BlumShub, Wichmann-Hill, Complementary multiply with carry, Inversivecongruential generator, ISAAC (cipher), Lagged Fibonacci generator, Linear feedback shift register, Maximal periodic reciprocals, Mersenne twister, Multiply-with-carry, Naor-Reingold Pseudorandom Function, RC4 PRGA, Well Equidistributed Long-period Linear, and Xorshift are some of the well-known methods [5]-[8]. Hardware for generating random number also available as well as its algorithm. The hardware have been used since 2008. LETech is the fastest among all hardware for computing random numbers, this hardware has been developed since 2008 [9], [10]. Research for finding the suitable algorithm of generating random number is well establish field until now. Many researchers use field programmable gate arrays (FPGA)

II. LINEAR CONGRUENTIAL GENERATOR There is a popular method and most used to generate random number called linear congruential generator. The idea was introduced by Lehmer according to sequential formula in (1) [1]. (1) X n 1  ( aX n  c ) mod m Where m is modulus, a is multiplier, c is increment. Parameters a, c and m have to be chosen carefully in order to avoid repetition of similar numbers before m [6]-[8]. Park & Miller suggested a good results will be obtained by choosing c=0 [3]. The modulus m should be a large prime integer, multiplier a will be an integer in the range 2, 3, . . . , m-1. The cycle length of LCG will never exceed modulus m, but it can be maximized using three following conditions [7], [13]:  c is relatively prime to modulus m,  multiplier a-1 is a multiple of every dividing modulus m,  multiplier a-1 is a multiple of four when modulus m is a multiple of four.

III. LCG CIRCUIT DESIGN A. General Circuit of LCG

Fig.1 shows block diagram LCG operation in general (seed is ignored). It requires multiplier, adder, comparator and subtractor blocks. Multiplier is used to multiple previous random value X with a, then add with increment c. After that it is compared to modulus m. The number is considered as random number if it is smaller or equal to m. The authors gratefully acknowledge the financial support from Otherwise, the number then subtracted with m. The result Research Center of Syiah Kuala University, Indonesia under project of this is then consider as random number. Hibah Bersaing. Copyright © 2014 IJECCE, All right reserved 809

International Journal of Electronics Communication and Computer Engineering Volume 5, Issue 4, ISSN (Online): 2249–071X, ISSN (Print): 2278–4209 The block diagram of Fig. 1 is involving arithmetic operation such as multiplication, addition, subtraction and comparison. In order simplify the process, the circuit is designed using word lengths reduction technique that has been suggested in [14]. Then subtarctor and comparator blocks can be removed, as shown in the Fig. 2. The designed circuit consist of a multiplexer, a multiplier, an adder, a buffer (required clear), and three buffers (required enable). Ports input Seed, A and C are used to pass initial value, multiplier and increment into the circuit. Meanwhile, port O is used to taking out the resulted random numbers.

Fig.1. Block diagram of LCG operation

Fig.2. General circuit of linear congruential generator The circuit is controlled by two signals enable and reset. Initially, signal reset have to be HIGH (enable=LOW) to clear the previous stored values in the buffer B4. Signal enable determine when the operation should be started. Pre-defined value (seed), increment and multiplier have to be available at the input ports before enable goes HIGH (reset=LOW). Then, every times clock goes HIGH, a random number resulted. Fig.3shows the circuit of the two signal controls. Fig.4. Word lengths reduction in multiplier’s block

Fig.3. Signal controls of the designed LCG circuit

B. Wordlengths Reduction The circuit of Fig. 2 can be used for any word lengths. The reduction of word lengths have to construct carefully to avoid undesirable operation result. For example, the LCG is designed for using maximum word lengths of 8 bit, the nets configurations of multiplier block and adder block are shown in the Figs. 4 and 5.

Fig.5. Word lengths reduction in adder’s block Based on arithmetic rules and to reduce area [15], the multiplication of B4 (8 bit) and B1 (8 bit) would require 15 bit at the output. In the design, we simply truncated (disconnected) the seven-higher nets (X(8) up to X(14)), this design is shown in the Fig. 4. Similarly, we can do the same thing to the nets of adder. In this case only one net (M(8)) disconnected as shown in the Fig. 5..

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International Journal of Electronics Communication and Computer Engineering Volume 5, Issue 4, ISSN (Online): 2249–071X, ISSN (Print): 2278–4209

IV. IMPLEMENTATIONS AND DISCUSSIONS A. Behavior Simulation The circuit in the Fig. 2 has been implemented into FPGA program. The simulations have been done using Xilinx ISE design suite. Some important data of synthesis result is shown. The comparison of area and speed have been done over several Xilinx’s chips.

Fig.6 shows behavior simulation result of modulus m=255, seed=7, multiplier a=3 and increment c=1. It can be seen the resulting numbers are random starting from 7 and all numbers are smaller than 255. Figs.7 and 8 show behavior simulation result of modulus m=216–1 and m=231–1 respectively. Also all number produced there never exceed modulus.

Fig.6. Simulation behavior result of m=255, seed=7, a=3, c=1

Fig.7. Simulation behavior result of m=216-1, seed=7, a=3, c=1

Fig.8. Simulation behavior result of m=231-1, seed=7, a=3, c=1

B. Synthesis result Some important synthesis data of the designed circuit using modulus m=255 into Xilinx Virtex 7 chip are: HDL Synthesis Report Macro Statistics # Multipliers :1 8x8-bit multiplier :1 # Adders/Subtractors :1 16-bit adder :1 # Registers :4 8-bit register :4 # Multiplexers :1 8-bit 2-to-1 multiplexer :1 ----------------------------------------------------------------------Slice Logic Utilization: Number of Slice Registers: 16 out of 437600 0% Number of Slice LUTs: 10 out of 218800 0% Number used as Logic: 10 out of 218800 0% Slice Logic Distribution:

Number of LUT Flip Flop pairs used: 17 Number with an unused Flip Flop: 1 out of 17 5% Number with an unused LUT: 7 out of 17 41% Number of fully used LUT-FF pairs: 9 out of 17 52% Number of unique control sets: 2 ----------------------------------------------------------------------Minimum period: 3.710ns (Maximum Frequency: 269.513MHz) Minimum input arrival time before clock: 2.023ns Maximum output required time after clock: 0.575ns Maximum combinational path delay: No path found From HDL synthesis report, the design circuit requires an 8x8-bit multiplier, 16-bit adder, four 8-bit register and 8-bit 2-to-1 multiplexer. In terms of slice logic utilization, the design occupies 16 slice registers and 10 slice LUTs. The distribution of slice logic from total amount of 17 are 9 for fully used LUT-FF pairs, 7 to unused LUT and 1 for unused flip-flop. The circuit also requires 2 unique control sets.

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International Journal of Electronics Communication and Computer Engineering Volume 5, Issue 4, ISSN (Online): 2249–071X, ISSN (Print): 2278–4209 The speed of the circuit limited to around 270 MHz when it is implemented into Virtex 7. Minimum input arrival time before clock is 2.023 ns. This means the data should be available at input port before that time. The maximum output required time after clock is 0.5775 ns.

C. Timing Simulation Fig.9 shows a close look of timing simulation result. There are some glitches when the number change from 67 to 202. This is because time from clock edge to pads varied. This variation range from 9.399 ns to 9.818 ns (post-PAR static timing report).

Fig.9. A close view of timing simulation

D. Comparison Four best Xilinx chips has been chosen in order to compare the speed and area of the designed circuit. Table I shows comparison of maximum frequency required for modulus m=255 (8 bit), m=216-1 (16 bit) and m=231-1 (31 bit) over Virtex 7, Spartan 6, Kintex 7 and Zynq chips. Table I : Maximum frequency comparison among Xilinx chips Maximum Frequency (MHz) Chips 8 bit 16 bit 31 bit Virtex 7 270 270 139 Spartan 6 154 154 73 Kintex 7 309 270 158 Zynq 272 272 140

area becomes twice when using modulus around 16 bits. Meanwhile when the modulus is changed to 31 bits, the occupied slices and LUTs increase to around three time. Figs. 11 and 12 show a more clear views of this behavior. Table II: Area occupies among Xilinx chips Chips Virtex 7 Spartan 6 Kintex 7 Zynq

8 bit Slices LUTs 16 10 16 10 16 10 16 10

Area Occupies 16 bit Slices LUTs 32 18 32 18 32 18 32 18

31 bit Slices LUTs 92 63 92 63 92 63 92 63

For m=255, the fastest chip is Kintex 7 and the slowest one is Spartan 6, but for m=216–1, the fastest chips is Zynq. In general, Kintex 7 is the fastest and Spartan 6 is the slowest chip. A more clear view of this figure can be seen graphichally in the Fig. 10.

Fig.11. Comparison of slice utilization among Xilinx chips

Fig.10. Comparison of maximum frequency among Xilinx chips Table II views area comparison among four Xilinx chips. It can be seen that all chip occupies the same area. For m=255, the chips required 16 slices and 10 LUTs. The

Fig.12. Comparison of LUTs required Copyright © 2014 IJECCE, All right reserved 812

International Journal of Electronics Communication and Computer Engineering Volume 5, Issue 4, ISSN (Online): 2249–071X, ISSN (Print): 2278–4209

V. CONCLUSION Design and implementation of linear congruential generator into FPGA have been done successfully. It is required special care of wordlengths connecting among the blocks of the circuit. By applying wordlengths reduction technique, a more efficient circuit has been obtained. The maximum frequency of the design circuit is 309 MHz (Kintex 7, m=255), and the minimum frequency is 73 MHz (Spartan 6, m=231–1). Kintex 7 is the best chip of applying the design LCG circuit. Further improvement of the design may be obtained by analyzing behavior of seed, multipliera and increment c. Finally, it is difficult to compare the result to the previous works since there is no available similar circuit or method before.

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AUTHOR’S PROFILE Zulfikar was born in Beureunuen, Aceh, Indonesia, in 1975. He received his B.Sc. degree inElectrical Engineering from North Sumatera University, Medan, Indonesia, the M. Sc. Degree inElectrical Engineering from King Saud University, Riyadh, Saudi Arabia, in 1999 and 2011,respectively. He joined as teaching staff in the Department of Electronics at Politeknik Caltex Riau, Pekanbaru, Indonesia in 2003. He served as head of Industrial Control Laboratory, Politeknik Caltex Riau from 2003 to 2006. In 2006, he joined the Electrical Engineering Department, Syiah Kuala University.His current position is head of Digital Laboratory, and his current research interests include VLSI design and System on Chips (SoC).

Hubbul Walidainy was born in Banda Aceh, Aceh, Indonesia, in 1973. He graduated from Electrical Engineering Department at Gadjah Mada University, Yogyakarta, Indonesia, in 1998. The Master Degree inElectrical Engineering from Gadjah Mada University, Yogyakarta, Indonesia, in 2003. He joined in the Department of Electrical Engineering, Syiah Kuala University,Aceh, Indonesia in 2000, as a teaching staff.His current position is the head of Telecommunication Laboratory.

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