GJTE-Vol(2)-Issue(4)
April 2015
ISSN: 2393-9923
Global Journal of Trends in Engineering
Design and verification of Current steering segmented Digital to Analog Converter Ankush Shingade1, Bhagyashree Wagh1, Harshada Gadge2, Rabinder Henry3, Arvind Shaligram1 1
Department of Electronic Science, S. P. Pune University, Pune, India 2 Sasken Communication, Technologies Ltd, Pune, India 3 Otto-von-Guericke University, Magdeburg, Magdeburg,Germany
E-mail Id:
[email protected],
[email protected],
[email protected]
ABSTRACT: Implementation of a segmented Digital to Analog Converter using 45 nm technology process. The proposed design includes cascode paired current steering segmented technique for one volt CMOS model. The designed circuit has been verified using different library modules and mismatch analysis has been performed with mathematical modelling. This model has been used for nonlinearity analysis of the circuit Keywords: Current steering, Digital to Analog Converter, Process technology, mathematical modelling, mismatch analysis. I. INTRODUCTION The present day digital systems interacts with natural world through Analog to Digital Converters (ADC) and Digital to Analog Converters (DAC). With improving accuracy and complexity of digital interfaces have resulted in stringent requirements in design of DAC. These requirements vary with different types applications. Depending upon the process technology the design technique of CMOS varies with respect to power requirements and performance requirements. In the proposed work a current steering segmented technique is implemented for 45 nm technology process to improve response time and at the same time consume less power. A new current steering technique based on fixed entities like “sub-DACs” architecture, which are nominally identical and operate in parallel. This results in enhanced and flexible performance, which is delivered in several modes of operation (OP). Mismatch errors are cancelled using a particular OP mode, which distributes the input word to several sub-DAC‟s [4]. Similarly, a 10-bit Charge-Redistribution ADC consuming very low power without external reference voltage by using a charge redistribution DAC is referred. This DAC is designed using step-wise charging module, a dynamic two-stage comparator and a delay-line based controller [5].A 10 bit current steering CMOS DAC is reported, which has been optimized for different sampling frequencies.The spurious free dynamic range (SFDR) is more than 55 dB for DC to Nyquist frequency range. This DAC is optimized for various embedded applications having large digital circuitry.[6] MOSFET mismatch effects on performance (yield) limitations are studied for improving performance of DAC[7][8]. The performance of a segmented current steering DAC in traditional 180 nm technology is discussed with respect to sampling frequency, settling time, and power consumption. The mentioned DAC have good linearity, low power consumption and small footprint [9]. The proposed segmented DAC is based on current steering technique, with 4 bit binary weighted architecture for LSB and 4 bit thermometer decoded architecture for MSB.The binary weighted DAC is one of the fastest conversion methods, but it suffers from poor accuracy. Whereas the thermometer coded DAC has highest accuracy, and fastest conversion time, but it requires more components and area, which increases the cost of DAC. To achieve the balance between accuracy, power consumption, conversion time, and area (i.e. cost) of chip, segmented DAC approach is used for this DAC.Design specifications are 8-bit DAC, 1V power supply, 80MHz clock frequency, full swing current output of 0-1mA, differential nonlinearity and integral nonlinearity are ± 0.25 LSB. The overall design includes three major parts 1) Reference currentsource. 2) 4 to 15 Bit decoder 3) 255 PMOS current cell with PMOS Differential switch. Figure 1 explains segmentation strategy for current steering DAC. As figure shows 8-bit DAC is divided into 4-bit binary weighted and 4-bit thermometer coded DAC.
Figure 1: Block diagram of a segmented current steering DAC. II. REFERENCE CURRENT SOURCE Reference current source generation is one of the important task for this DAC design. As per specifications i.e. for 8-bit resolution, and 1 mA output current a reference current source of 4 uA is designed. 92
GJTE-Vol(2)-Issue(4)
April 2015
ISSN: 2393-9923
Global Journal of Trends in Engineering The reference current source is designed considering mismatch variations for which Pelgrom equation is referred [1].The reference generator incorporates self-biasing cascode topology.The reference current source design have high output impedance, high swing and high output voltage. Differential Non Linearity (DNL) and Integral Non Linearity (INL) errors of DAC can be related to the matching properties of the unit current source. For binary weighted DAC, maximumDNL will arise at midcode i.e. when LSB switch off and ( MSB switch on. While in a segmented architecture DNLfor every code is similar. There is no abrupt increase in DNL as for binary weighted DAC. For „m‟ bit binary weighted DAC, having maximum DNL = 0.25LSB, „σ‟ is given by following formula.
(1) Moreover, since binary scaled current sources consist of groups of unit current sources, INLmaximum error occurs at midcode. This applies to unary weighted, binary weighted, and segmented current steering topologies, and it aggregates to:
(2) From equations (1) and (2) the optimum percentage of segmentation and the required precision of the unit current source iscalculated, once maximum INL and are defined. Analytically calculated INLmaximum is 0.31 and is 4%. Resolution Segmentation DNL INL σ 8 bits 4-4 0.25LSB 0.31 4% (0.1) Table 1: Theoretical calculated result of segmented DAC The above mentioned specifications are used to design current source and unit cell.Using the parametric analysis of 45 nm technology PMOS and NMOS models are finalized.PMOS 1V_lvt, and NMOS 1V_lvt models having low threshold voltageare utilized for low power application. Using equation no. 3 width (W), and length (L) of CMOS are calculated.[1] (3) Aβ is the transistor constant related matching constant in [%µm], Avth is the threshold voltage related matching constant in [mVµm]. Appropriate channel area WL and effective gate voltage VG_EFF = (VGS-VTH) are derived to achieve required standard deviation σ. Using equation 3 and saturation region formula W and L are calculated. W= 4.4 um, and L = 0.925 um. Figure 2 shows layout of reference current source design.
93
GJTE-Vol(2)-Issue(4)
April 2015
ISSN: 2393-9923
Global Journal of Trends in Engineering
Figure 2: Layout of reference current source III. UNIT CELL DESIGN Unit cell of segmented DAC consistsone cascode pair of 4uA reference current source and switches as shown in Figure 3. All transistorsare PMOS. Upper two transistor pin connections vgs1 and vgs2 are coming from cascode reference current source i.e. it is a cascode pair.Lower two transistors are switch pair, when one is active another is in cutoff region so that current can be steered into output branch. Figure 4 shows the layout of unit cell.
Figure 3: Unit cell of segmented DAC
Figure 4: Unit cell layout 4 to 15 bit decoder 4-bit to 15-bit decoder is designed to give triggering signal to switching transistors of thermometer coded DAC. As this block is pure digital it is implemented using 2-input, 3-input, and 4-input NAND gates. Figure 5 shows the layout implementation of 4 to 15 bit decoder.
Figure 5: 4 to 15 decoder layout IV. MISMATCH ANALYSIS USING MATLAB The ideal input vs output characteristics of DAC is staircase with uniform step size for complete range of input. There are various errors which hampers ideal output of DAC. While designing this DAC certain errors are taken into consideration and mathematical simulations are performed to understand their effect on DAC‟s performance. The complete mathematical model is done inMatlab [10]. The model analyses errors, offset, gain, DNL, INL, monotonicity, signal to noise ratio, total harmonic distortion, signal to noise &distortion ratio, total harmonic distortion plus noise, spurious free dynamic range, and effective number of bits. 94
GJTE-Vol(2)-Issue(4)
April 2015
ISSN: 2393-9923
Global Journal of Trends in Engineering The developed model generates DAC behavior depending on customized data. The input for the model includes number of bits for DAC, bitwidth for thermometer coded DAC, unit LSB current, estimated sigma (variation in unit current source), number iterations for performing mismatch analysis. The simulated is shown in Figure 6 to Figure 9.
Figure 6: Gaussian distribution of sigma (σ i.e. variation in unit current source).
Figure 7: Segmented DAC simulation with mismatch.
Figure 8: DNL response of segmented DAC for 1000 iterations.
Figure 9: INL response for segmented DAC for 1000 iterations. After performing mismatch analysis following observations are noted in Table 2. Depending on these observations it is clear that DNL, INL errors are minimum for 4-4 bit segmentation of DAC. Therefore final designing and layout of DAC was done for 4-4 bit segmentation. Segmentation DNL INL σ Unary Binary 2 6 0.1 0.6 5% 6 2 0.14 0.75 5% 3 5 0.2 0.5 4.5% 5 3 0.15 0.77 6% 4 4 0.14 0.35 5% Table 2: Mismatch analysis for different segmentation combinations. 95
GJTE-Vol(2)-Issue(4)
April 2015
ISSN: 2393-9923
Global Journal of Trends in Engineering V. RESULTS Simulation results for 8-bit current steering DAC are listed below.Figure 10 shows 4 to 15 bit decoder‟s simulation output. Figure 11 (A) shows Monte-Carlo analysis result, Figure 11 (B) shows Fast-Fast analysis result. Figure 12 (A), (B) shows Fast-Slow and Slow-Fast analysis results respectively. Slow-Slow analysis results are shown in Figure 13 (A), Figure 13 (B) shows Typical-Typical analysis result. Figure 14 shows an output result of DAC. Also final layout for DAC is provided in Figure 15. The layout contains array of unit cells, reference cascode current source, 4 to 15 Thermometer decoder.
Figure 10: 4 to 15 thermometer decoder response
Figure 11: (A) MC analysis, (B) FF analysis for DAC
Figure 12: (A) FS analysis, (B) SF analysis for DAC
Figure 13: (A) SS analysis, (B) TT analysis for DAC
96
GJTE-Vol(2)-Issue(4)
April 2015
ISSN: 2393-9923
Global Journal of Trends in Engineering
Figure 14: DAC output simulation
Figure 15: Full DAC layout VI. CONCLUSION Reference cascode current source (4 uA) is designed and validated. Different combinations of segmented DAC are studied using mathematical models and optimized results are reported for 4-4 combination. Implementation of 8-bit current steering cascoded DAC is designed in 45 nm technology using 1V_lvt model. Thermometer decoder is implemented using only NAND gates and verified.The corner points simulations are performed on the device and results are satisfactory. In all the 8-bit current steering segmented DAC are implemented in 220 um X 330 um layout area. REFERENCES [1] M. J. M. Pelgrom, T. Jochijms, and H. Heijns, “A CCD delay line for video applications,” IEEE Trans. Consumer Electron., vol. CE-33, pp. 603-609, 1987. [2] An 8 bit current steering DAC for offset compensation purposes in sensor arrays G. Bertotti1,2, A. Laifi1, E. Di Gioia1, M. Masoumi1, N. Dodel1, E. F. Scarselli2, and R. Thewes11Chair of Sensor and Actuator Systems, TU Berlin, Berlin, Germany 2ARCES, University of Bologna, Bologna, Italy. [3] A 200MHz 12- bit current-steering DAC in 0.35 um CMOS,De backer els,bauwelinck johan,Qul xlingzhi,vandewege jan. [4] A 10-b, 500-MSample/s CMOS DAC in 0.6 mm,Chi-Hung Lin and Klaas Bult. [5] An LCD Column Driver Using a Switch Capacitor DAC,Marshall J. Bell, Member, IEEE. [6] A 10-bit Charge-Redistribution ADC Consuming 1.9 �W at 1 MS/s Michiel van Elzakker, Member, IEEE, Ed van Tuijl, Member, IEEE, Paul Geraedts, Daniël Schinkel, Member, IEEE,Eric A. M. Klumperink, Senior Member, IEEE, and Bram Nauta, Fellow, IEEE. [7] A parallel current-steering DAC architecture for flexible and improved performanceR.A.T. van den Hoven, G.I. Radulov, J.A. Hegt, A.H.M. van Roermund.Mixed-signal Microelectronics Group, Eindhoven University of Technology, Electrical Engineering, Eindhoven. [8] Matching Properties of MOS Transistors marcel j. m. pelgrom, member,ieee,aad c. j. duinmaijer, andanton p. g. welbers. [9] Transistor matching in analog CMOS applications.Marcel J.M. Pelgrom, Hans P. Tuinhout and Maarten Vertregt Philips Research Laboratories, Bldg. WAY5, Prof. Holstlaan 4, 5656AA Eindhoven, the Netherlands.
97
