Design, implementation and verification through a ...

INTERNATIONAL JOURNAL OF SATELLITE COMMUNICATIONS AND NETWORKING Int. J. Satell. Commun. Network. 2003; 21:39–64 (DOI: 10.1002/sat.745)

Design, implementation and verification through a real-time test-bed of a multi-rate CDMA adaptive interference mitigation receiver for satellite communication Luca Fanucci1,n,y, Riccardo De Gaudenzi2,z, Filippo Giannetti3, Marco Luise3,} and Massimo Rovini3 2

1 Consiglio Nazionale delle Ricerche, IEIIT, Via Diotisalvi 2, 56122 Pisa, Italy European Space Agency, European Space Research and Technology Centre, P.O. Box 299, 2200 AG Noordwijk, The Netherlands 3 Universita" di Pisa, Dipartimento di Ingegneria dell’Informazione, Via Diotisalvi 2, 56122 Pisa, Italy

SUMMARY This paper presents the design, the implementation, and the main performance results of a multi-rate code division multiple access (CDMA) interference mitigation receiver for satellite communication. Such activity was performed within a research project supported by the European Space Agency (ESA), whose aim was to demonstrate the suitability of the linear adaptive interference mitigation detector (IMD) named extended complex-valued blind anchored interference-mitigating detector (EC-BAID) for single-user detection of a CDMA signal in third-generation (3G) satellite networks. Such a detector, which exhibits a remarkable robustness to multiple access interference, operates in a blind mode, i.e. it only requires knowledge of the timing of the wanted user’s signature code, and is therefore very well suited for integration into handheld user terminals. Experimental results in terms of bit error rate with respect to the theoretical behaviour were derived through a specifically developed test bed. Signal plus multiple access interference generation is performed via a computer-controlled arbitrary waveform generator, followed by frequency up-conversion to the standard intermediate frequency of 70 MHz: Additive white Gaussian noise is then injected with the aid of a precision noise generator. The core of the test bed is a flexible digital receiver prototype featuring the ECBAID detector plus all functions ancillary to IMD (multi-rate front-end, automatic gain control, code acquisition and tracking, carrier synchronization, etc.). Those functions were implemented through careful mixing of different technologies: field programmable gate arrays (FPGAs) for computing-intensive signal processing functions, digital signal processor (DSP) for housekeeping and monitoring, and application specific integrated circuit (ASIC) for adaptive IMD. The adopted design flow also allows an easy re-use of the prototype architecture to come to an overall integration of the receiver into a single ASIC with modest complexity and power consumption increase with respect to a conventional detector. Copyright # 2003 John Wiley & Sons, Ltd. KEY WORDS:

CDMA; adaptive interference mitigation receiver; satellite communications; VLSI

n

Correspondence to: L. Fanucci, Consiglio Nazionale delle Ricerche, IEIIT, Via Diotisalvi 2, 56122 Pisa, Italy. E-mail: [email protected] E-mail: [email protected] } E-mail: [email protected] y z

Copyright # 2003 John Wiley & Sons, Ltd.

Received 27 September 2002

40

L. FANUCCI ET AL.

1. INTRODUCTION The last decade witnessed an impressive blooming of literature on multi user detection (MUD) for the return link of a code division multiple access (CDMA) cellular or satellite radio network. In addition to proper MUD algorithms for return-link demodulation, a number of lowcomplexity single-user interference-mitigating detectors (IMDs) suited for user-terminal forward link demodulation have also been proposed and studied. Amidst such schemes (e.g. Reference see [1]), the class of linear blind minimum output energy (MOE) detectors [2, 3, 4, 5] appears to be an attractive candidate for boosting downlink performance [6]. In this paper, we report the main design and implementation aspects, as well as performance figures (both simulated and measured) of a multi-rate CDMA receiver including the so-called extended complex-valued blind adaptive interference-mitigating detector (EC-BAID) for adaptive interference mitigation [3]. This activity, sponsored by the European Space Agency (ESA) in the framework of the Multi USer and Interference Cancellation (MUSIC) technology research program (TRP) project, is targeted towards the field of satellite communications (see main specification in Table I) but has also a view to possible extension to terrestrial wireless networks. As a matter of fact, rake demodulators featuring IMDs showed attractive performance over terrestrial frequency selective fading channels [7]. Main focus of the activity was on the real-time demonstration of a compact ASIC-based advanced CDMA detector including adaptive interference mitigation. After this short introduction, Section 2 presents the CDMA signal format and Section 3 describes the main design aspects of a CDMA interference mitigation receiver. The relevant hardware implementation is detailed in Section 4. Section 5 presents the real-time test bed for receiver verification under practical working conditions. Section 6 summarizes measured performance results, and finally Section 7 provides an overview of the main findings and an outlook on future activity.

2. CDMA SIGNAL FORMAT According to the considerations reported in Reference [2], the CDMA signal format selected for the IMD test bed is quadrature phase shift keying (QPSK) direct-sequence spread-spectrum Table I. Excerpt from signal generation and MUSIC receiver specifications. Maximum/minimum channel data rate Maximum/minimum chip-rate Signature sequences type Signature sequence period L Maximum power unbalance between traffic channels Maximum number of interfering channels Interferers delay w.r.t. the useful channel Interferers phase shift w.r.t. the useful channel Chip shaping IF carrier frequency Minimum AWGN Eb =N0 Overall SNR degradation w.r.t. to FP simulation with ideal sync/EC-BAID configurations 103 4BER48  102

Copyright # 2003 John Wiley & Sons, Ltd.

64–2 kb=s programmable 2.048–0:128 Mc=s programmable WH+E-PN or E-Gold 32, 64 or 128
6 dB L 0–L chips programmable 0–3608 programmable SRC with roll-off factor 0.22 70 MHz 1 dB 41:0 dB

Int. J. Satell. Commun. Network. 2003; 21:39–64

41

DESIGN, IMPLEMENTATION AND VERIFICATION

(DS/SS) with real-valued (single-code) spreading/scrambling. The signal provided by the generator is a code-division multiplex made of K users having the same information rate Rb ¼ 1=Tb ; which can be represented by the following baseband equivalent description eðtÞ ¼

K X

ek ðtÞ

ð1Þ

k¼1

ek ðtÞ ¼

1 pffiffiffiffiffi X Pk ½ak;p ðuÞ þ jak;q ðuÞsk ðt  uTs  tk Þ exp½jð2pDfk t þ fk Þ

ð2Þ

u¼1

sk ðtÞ ¼

nL1 X

cjkjL ðlÞgT ðt  lTc Þ

ð3Þ

l¼0

where Pk is the k-th signal’s power, ak;p ðuÞ and ak;q ðuÞ are the ‘in-phase’ and ‘quadrature’ (I/Q) components, respectively, of the u-th QPSK information symbol, L is the period of the spreading sequence, Tc is the chip time, Ts ¼ 2Tb is the QPSK symbol time, Dfk is the k-th carrier frequency offset with respect to the nominal frequency f0 ; fk is the k-th user carrier phase, gT ðtÞ is the Nyquist root-raised cosine (NSRC) impulse response of the chip shaping filter, and tk represents the k-th user signal delay. Without loss of generality, we also assume 04tk 4Ts : The signature sequence ck ðlÞ is a short (i.e. less than one symbol long) composite sequence, made of a Walsh– Hadamard (WH) binary function overlaid by an extended pseudo-noise (PN) scrambling sequence with the same start epoch and period L [8]. Such composite sequences are necessary in multi-beam multi-satellite systems, or in cellular terrestrial systems, wherein the overlay PN is beam/sector unique, and a different WH signature sequence is assigned to each different user within the same beam/sector. The chip rate Rc of the useful signal is given by Rc ¼ nLRs ; where L is the signature code period, n represents the number of code periods within one symbol interval (i.e. Ts ¼ nLTc ; as is apparent from Equation (3) where jkjL denotes k modulus L), to be set in order to accommodate different service rates, and Rs ¼ Rb =2 is the symbol rate. The maximum chip rate is Rc;max ¼ 2:048 Mchip=s; while the supported code lengths, chip and bit rates are listed in Table II for the case n ¼ 1: The chip shaping NSRC filter bandwidth can be expressed as ð1 þ aÞRc ; where a ¼ 0:22 is the roll-off factor of the filter, thus the maximum signal bandwidth occupancy (at the intermediate frequency IF) turns out to be BIF ¼ ð1 þ aÞRc;max ¼ 2:56 MHz:

Table II. Code lengths, bit rates and chip rates supported by the MUSIC receiver ðn ¼ 1Þ: L ¼ 32 Rb Rb Rb Rb Rb Rb

¼ 4 kb=s ¼ 8 kb=s ¼ 16 kb=s ¼ 32 kb=s ¼ 64 kb=s ¼ 128 kb=s

Rc Rc Rc Rc Rc

} ¼ 128 kc=s ¼ 256 kc=s ¼ 512 kc=s ¼ 1024 kc=s ¼ 2048 kc=s

Copyright # 2003 John Wiley & Sons, Ltd.

L ¼ 64 Rc Rc Rc Rc Rc

¼ 128 kc=s ¼ 256 kc=s ¼ 512 kc=s ¼ 1024 kc=s ¼ 2048 kc=s }

L ¼ 128 Rc Rc Rc Rc

¼ 256 kc=s ¼ 512 kc=s ¼ 1024 kc=s ¼ 2048 kc=s } }

Int. J. Satell. Commun. Network. 2003; 21:39–64

42

L. FANUCCI ET AL.

3. DESIGN OF A CDMA INTERFERENCE MITIGATION RECEIVER Figure 1 shows the block diagram of the CDMA interference mitigation receiver. In this section the main design aspects of each receiver subunits are addressed. For all of them the design has been carried out by successive refinement steps starting from FORTRAN floating point modelling, through bit-true simulation up to hardware description language (HDL) code development. All of the hardware design parameters have been set as a trade-off between hardware complexity and system performance although the latest have been often prevailing. 3.1. Multi-rate receiver front-end The input modulated signal at IF fIF ¼ 70 MHz (whose spectrum is sketched in Figure 2) made of useful, MAI and channel noise, is first sampled at conversion rate fs ¼ 1=Ts ¼ 16:384 MHz by an ADC on 7 bits, yielding a new band pass signal at digital intermediate frequency (IFD) fIFD ¼ 4:464 MHz (whose spectrum is shown in Figure 3). The IFD signal is then downconverted to baseband by means of the I/Q rotators driven by a digitally controlled oscillator (DCO). The DCO generates two (locked) I/Q oscillations at fIFD ¼ 4:464 MHz; digitized at rate fs ; where the frequency fIFD is locally adjusted by the frequency error estimate Df# provided by the

CIC fs fs

IF Input ADC

I DCO Q

f I = 70

fs

Prompt-I

Compensation Linear N-stage Interp. Comb f Filter / CMF d f d =4Rc

N-stage Integrator f s

fs

In-Phase Front-End

Decimation ρ

2R c

Rc

DSP Interface

Rc

Symbol Start

E/L-I Code epoch

∆ fˆ

Rs EC-BAID Unit

CTAU

CIC

Decimation ρ N-stage

Quadrature Front-End

Prompt-Q

Compensation Linear Interp. Comb f Filter / CMF d f d =4Rc

N-stage Integrator f s

2R c CCTU

AFC Loop Filter

E/L

AFC

Symbol Cloc

Signal Int. Clock Detect 8 Rc

Rc

Rc E/L-Q

I/Q Soft Data

Rs I/Q Correl.

SACU

FED

Pilot Channel Code Traffic Channel Code

Figure 1. Receiver block diagram with signal processing rates.

Figure 2. Spectrum of the IF signal. Copyright # 2003 John Wiley & Sons, Ltd.

Int. J. Satell. Commun. Network. 2003; 21:39–64

43

DESIGN, IMPLEMENTATION AND VERIFICATION

Figure 3. Spectrum of the sampled IF signal at the ADC output. Table III. Chip rates, decimation factors and decimated frequencies. Rc (Mchip/s) 0.128 0.256 0.512 1.024 2.048

ns (sample/chip)

r

fd (Msample/s)

128 64 32 16 8

32 16 8 4 2

0.512 1.024 2.048 4.096 8.192

Automatic Frequency Control Unit (AFCU), described later in Section 3.3. Rejection of unwanted spectral images arisen in the down-conversion process and located at
7:456 and
8:928 MHz is deferred to the subsequent (low-pass) chip matched filter (CMF). The digital I/Q down-conversion is implemented by resorting to a phase accumulator, which numerically performs the integration of the digital frequency fIFD : The latter is set by the frequency control word (FCW) on nFCW ¼ 11 bits, according to the recursive algorithm fk ¼ fk1 þ 2pTs fIFD updated at clock rate fs ¼ 1=Ts : The phase accumulator operates on nacc ¼ 27 bits to attain a frequency resolution of fs =2nacc ¼ 0:122 Hz; which, after preliminary investigations based upon extensive simulation runs, was found to be accurate enough for our purposes. The phase fk ; which is represented on the npha ¼ 10 most significant bits of the accumulator output, is then passed to a 2 kbits look-up table (LUT) which yields sin ðfk Þ and cos ðfk Þ samples represented on nDCO ¼ npha  2 ¼ 8 bits in order to have the same RMS error for both amplitude and phase quantization [9]. We remark that the received signal is sampled at the nominal rate of fs ¼ 1=Ts ¼ 16:384 Msample=s and therefore the number of samples per chip turns out to be ns ¼ fs =Rc (the possible values for the various chip rates are reported in Table III). Since CMF and subsequent signal processing operations (especially chip timing synchronization) require a constant number of four samples per chip interval, the signal reveals significantly oversampled, and this will cause the CMF to bear an excessive complexity, due to the huge number of taps required. Therefore, some decimation is in order so as to achieve the target sampling rate ns ¼ 4 sample/chip. The decimation factor to be applied is defined as r ¼ ns =ns and its numerical values are reported in Table III as well. The issue of noise aliasing during decimation has been effectively circumvented by resorting to the so-called cascaded integrator and comb (CIC) architecture, which is well known from the literature [10]. The CIC represents a low-complexity solution to a multi-rate low-pass filter. After down-conversion and decimation down to the rate of ns ¼ 4 samples/chip interval, the signal samples enter the chip matched filter. The CMF/equalizer was obtained by merging the Copyright # 2003 John Wiley & Sons, Ltd.

Int. J. Satell. Commun. Network. 2003; 21:39–64

44

L. FANUCCI ET AL.

two cascaded functions of chip matched filtering for ffi optimum inter-chip-interference-free pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi detection (square-root raised cosine GR ðf Þ ¼ GN ðf Þ=Tc ; with GN ðf Þ a Nyquist raised-cosine spectrum, GN ð0Þ ¼ Tc ;) and an additional equalizer Heq ðf Þ to compensate for the in-band distortion introduced by the CIC filter [10, 11]. The target global transfer function of the filter, given by HFIR ðf Þ ¼ Heq ðf ÞGR ðf Þ; is then approximated by a 33-tap FIR filter optimized through a modified Parks–McLellan method [11, 12]. Further complexity reduction techniques, such as hardware time multiplexing and folded delay chain structure [13] were also adopted. The best trade-off between hardware complexity and performance were achieved by choosing 8 bits for input and output data width and 6 bits for filter coefficients. The CMF output samples are subsequently fed into first-order (i.e. linear) interpolators controlled in the tracking mode by an estimate of the timing delay coming from the chip clock tracking unit (CCTU) (see Section 3.2). During initial acquisition, the estimated delay is arbitrary so that the interpolator outputs are decimated at rate 2Rc and passed on to the code time acquisition unit (CTAU) for coarse code acquisition (see Section 3.2). Once coarse acquisition has taken place, the interpolator outputs are split into two streams at the rate Rc (‘prompt’ and ‘early/late’ samples). The early/late samples are used in the CCTU where fine chip timing synchronization takes place, while the prompt samples are delivered to the AFCU for carrier frequency recovery, and to the EC-BAID for data detection. Finally, the carrier phase recovery is embedded in the EC-BAID detector, thus it is not directly shown in Figure 1. 3.2. Code acquisition and tracking As mentioned before, the code synchronization issue can be split into coarse code acquisition, performed by the CTAU unit, and the subsequent fine chip timing tracking, carried out by the CCTU unit. During start-up, and before chip timing tracking is started, the CTAU has to decide whether the intended user m is transmitting, and, in the case he/she actually is, coarsely estimate the signal delay tm to initiate fine chip time tracking and data detection. Initial signal acquisition is carried out by processing the so-called pilot signal. It may be expedient to use a signature belonging to a different set with respect to that used for the traffic channels (hence nonorthogonal), in order to avoid false locks or wrong settings of the detection threshold when a large amount of CDMA orthogonal interference can be present as in the system downlink. To further ease acquisition and tracking, the pilot signal is usually transmitted with a power level significantly higher than the traffic channel(s) (the so-called pilot power margin or P =C ratio). The CTAU implements the parallel detection/acquisition circuit presented in Reference [14] after adaptation to QPSK with real spreading (a single code) instead of dual BPSK (double code), and delivers the information about the initial code phase either for traffic or syncreference signal generation. The signal presence information bit is also output by the circuit. The design parameters of that circuit, whose conceptual scheme is depicted in Figure 4, are: (i) the value of the normalized threshold l; and (ii) the length of the post-correlation smoothing window W : The CTAU receives the stream of complex-valued samples at rate 2Rc (two samples per chip) at the output of the interpolator. Such I/Q signal is processed by a couple of filters matched to the spreading code (this operation is also addressed to as the sliding correlation of the received signal with the local replica code). Also, the circuit assumes a correlation length (the impulse response length of the front-end FIR filters) equal to one symbol span, as a trade-off between Copyright # 2003 John Wiley & Sons, Ltd.

Int. J. Satell. Commun. Network. 2003; 21:39–64

DESIGN, IMPLEMENTATION AND VERIFICATION

45

Figure 4. Block diagram of the CTAU.

hardware complexity and performance according to computer simulations. A larger value of the correlation length (M symbols) decreases the probability of wrong code phase acquisition PWA ; but increases the total latency time WM and leads to a considerably more complex CTAU implementation. The CTAU uses an adaptive threshold to achieve a constant false alarm probability, PFA : The normalized threshold l is then selected in order to obtain the desired values of PFA and missed detection probability PMD : A value of l ¼ 1:75 was derived by means of extensive bit-true computer simulation as a trade-off between PFA and PMD for all the operating scenarios. Lower values of l would still ensure low PMD ; but would also yield intolerably higher PFA when signal is not present. As a further simplification largely reducing the acquisition unit complexity, the input signal in the CTAU can be quantized on 1 bit (i.e. the MSB of the front-end outputs). Such a raw quantization decreases performance in terms of probability of wrong acquisition, but it can be anyway compensated through appropriate lengthening of the smoother window length W ; which can be set to 1024 as baseline to satisfy the specifications. The signal amplitude control unit (SACU), depicted in the block diagram of Figure 1, keeps constant (controlled) the signal amplitude at the input of the CCTU and the AFCU so as to keep their respective loop bandwidth constant as well, independent of signal to noise plus interference ratio (SNIR). To this aim we resorted to a digital control loop to refine coarse analog amplitude control performed at IF on the incoming signal. This is achieved through a first-order IIR digital filter, which outputs the time variant SACU gain AðkÞ; according to the recursive rule carried out at symbol rate AðkÞ ¼ Aðk  1Þ  gSACU ðjxðkÞj  xref Þ where xðkÞ ¼ AðkÞyðkÞ is the regulated version of the pilot-channel despreader output on the ‘prompt’ samples yðkÞ (i.e. sampled at the optimum Nyquist sampling time) and gSACU is the customary step size, Copyright # 2003 John Wiley & Sons, Ltd.

Int. J. Satell. Commun. Network. 2003; 21:39–64

46

L. FANUCCI ET AL.

Figure 5. Synchronization loop and CCTU architecture.

xREF the amplitude reference value. gSACU and xREF configuration parameters can be externally programmed with 2-bit and 6-bit control signals, respectively. Particularly, the former can assume the values 22 ; 23 ; 24 or 25 : The CCTU is dedicated to chip-time reference recovery once the signal code has been coarsely detected by the CTAU. It is based on a non-coherent pilot-aided closed-loop tracker [15] involving also a linear interpolator (LI) [16]. The CCTU is decomposed into a chip-timing error detector (CED) that operates on the early–late samples and an update unit that recursively updates the integer delay and the fractional epoch input to the LI. The CED is the traditional non-coherent early–late correlator with time offset equal to one chip and full-symbol correlation. In order to ease clock tracking, despreading involves a local replica of the pilot signature code. The CED unit performs despreading for early and late pilot-signal samples, i.e. the sample taken, respectively, TC =2 before and after the optimum time sampling. To reduce implementation complexity, we adopted a simplified version of the error signal proposed in Reference [16], given by the magnitude difference of early and late pilot despread symbol, instead of their squared values. The relevant performance difference was shown to be negligible by simulation.k The CED output is then low-pass filtered in the update unit (see Figure 5) according to equation Ek ¼ Ek1  gCCTU e0k where gCCTU is the loop step size, to be chosen as a trade-off between acquisition time and steady-state jitter performance, and e0k the CED output after amplitude regulation. We actually adopted a time-variant solution, wherein the loop step size is modified when CCTU lock is acquired. Specifically we use gCCTU ¼ 26 during CCTU acquisition and then gCCTU ¼ 27 in the steady-state condition. Finally, the update unit outputs the control signals to the LI and the symbol sync signal to the EC-BAID. Bit-true jitter performance indicates no appreciable performance degradation and BER impairments due to chip tracking under worstk

Performance impairment may become less acceptable in case of terrestrial systems characterized by frequency selective channels. In this case the multipath sensitivity of the DLL is largely enhanced by the lack of a squaring device.

Copyright # 2003 John Wiley & Sons, Ltd.

Int. J. Satell. Commun. Network. 2003; 21:39–64

DESIGN, IMPLEMENTATION AND VERIFICATION

47

case multiple access interference (MAI) conditions outlined in Table I also resulted to be negligible. Further testing flexibility has been achieved allowing a custom step size programmability on 2 bits and ranging in the gCCTU discrete range [26 –29 ]. 3.3. Automatic frequency control The AFCU implements a long loop approach (see Figure 1), wherein the multi-rate receiver front-end is included in the loop since the relevant processing latency is definitely negligible with respect to the intrinsic response time of the AFCU as a whole. The unit operates on the I/Q symbol-time samples despread with the pilot code and amplitude controlled by the SACU. These signal is fed to the frequency error detector (FED) in order to generate the frequency error signal en ðkÞ which, after low-pass filtering, drives the DCO. Denoting the symbol-time sample at the SACU output as xðkÞ; the frequency error signal en ðkÞ is given by en ðkÞ ¼ ImfxðkÞxn ðk  2Þg [17]. The use of a two-symbol delay for the AFCU is justified by the improved jitter performance of the loop in the presence of strong MAI. The relevant S-curve is then SðnÞ ¼ Efen ðkÞjng ¼ A2 sinð4pnTs Þ; so the lock-in (pull-in) range of the AFCU is equal to 0:25=Ts : The two-symbol delay contributes to decorrelate the MAI components in the two received signal samples used by the FED, as opposed to a standard one-symbol-delay discriminator. The frequency error signal en ðkÞ is filtered by an IIR loop filter to give the updated estimate of the frequency offset n# ðkÞ at symbol rate. When using a pilot channel to perform frequency control, we could also lengthen the coherent despreading interval with respect to a symbol period, and slow down the updating rate accordingly. This would probably enhance loop robustness against noise, but it also would make it more sensitive to a large initial frequency offset, which can be as high as 10% of the symbol rate. This is why we stuck here to symbol-time integration and symbol-rate updating. The frequency filter step size is set as a trade-off between acquisition time and steady-state frequency jitter, as usual. It amounts to 215 during initial acquisition, and then after 104 symbol periods it is switched to the value 219 ; so we get short acquisition time and low steady-state jitter. Computer bit-true simulations indicate that performance degradation is negligible when the AFCU error signal is represented on 9 bit, the relevant filtered version (frequency control word) is represented on 11 bits and the internal loop filter registers are 21-bit sized. The HW implementation actually allows the step size to be adjustable with 3-bit precision in the discrete range ½219 ; 215 : 3.4. The EC-BAID demodulator The EC-BAID detector, whose high-level conceptual schematic is depicted in Figure 6, is just a linear detector operating on the chip-rate sampled received signal yðmÞ to yield the symbol rate signal b1 ðrÞ as follows: b1 ðrÞ ¼ ð1=LÞhe1 ðrÞT  ye ðrÞ he1 ðrÞ

ð4Þ

e

where is the extended (we use superscript to this aim) 3L-dimensional array of the complex-valued detector coefficients, and ye ðrÞ is the 3L-dimensional vector of chip-rate signal samples (with the index r running at symbol time). It is evident that the detection of each symbol calls for observation of three symbol periods (i.e. the current, the leading and the trailing ones). We will not dwell here on further details on the EC-BAID algorithm, which can be found in Reference [3] and we will just mention that the Copyright # 2003 John Wiley & Sons, Ltd.

Int. J. Satell. Commun. Network. 2003; 21:39–64

48

L. FANUCCI ET AL.

Figure 6. High-level conceptual block diagram of the EC-BAID detector.

detector coefficient vector is expressed according to the following canonical decomposition he1 ðrÞ ¼ ce1 þ xe1 ;

ce1 ¼ ½0; cT1 ; 0T ;

xe1 ¼ ½xT1;1 ; xT1;0 ; xT1;þ1 T

ð5Þ

where c1 is the L-dimensional vector of the intended user’s spreading code chips and xe1 is the adaptive part of the detector’s coefficients. The so-called anchor constraint cT1  x1;w ¼ 0; w ¼ 1; 0; 1; is essential in order to achieve blind adaptation and the interference-mitigating feature of EC-BAID resides in the strategy for designing the code-orthogonal vector xe1 [3]. Summarizing, the adaptive algorithm can be expressed in the form xe1 ðk þ 1Þ ¼ xe1 ðkÞ  gBAID ee1 ðkÞ

ð6Þ

where ee1 ðkÞ is an error signal which must be computed to drive the detector’s MOE towards a minimum and the adaptation step gBAID must be set as a trade-off between steady-state jitter and convergence speed. Extensive simulation runs revealed that a static sampling error in the receiver might arise a harmful long-term bias on the mean square error at the EC-BAID output which entails a slow drift of the BER far from the value it has with ideal sampling. Also, it was noticed that such a phenomenon occurs on a much slower time scale than that characteristic of the EC-BAID updating equation, i.e. the slow drift starts occurring, with a time constant at least ten times larger than that of EC-BAID adaptation. The drift is presumably due to a slow tendency of the EC-BAID to find a MOE configuration that, in the presence of a sampling error, does not lead to a condition of optimum BER as in the case of ideal sampling. The long-term drift can be counteracted by introducing a small ‘leak factor’ in the EC-BAID adaptive equation, as shown in the following equation: xe1 ðk þ 1Þ ¼ ð1  gleak gBAID Þxe1 ðkÞ  gBAID ee1 ðkÞ

ð7Þ

where gleak is the (normalized) leak factor. Of course, this factor has to be optimized since a factor too small has no effect, while introducing a large leak factor makes the loop noisy: such optimization, verified by computer simulation, led to an optimum value of gleak ¼ 23 ¼ 0:125: Copyright # 2003 John Wiley & Sons, Ltd.

Int. J. Satell. Commun. Network. 2003; 21:39–64

DESIGN, IMPLEMENTATION AND VERIFICATION

y(k)

49

cˆk

z(k) DEC

from EC-BAID

to DSP

ˆ

e −j θ(k) LOOK-UP TABLE

θˆ (k)

PED

LOOP FILTER

eθ (k)

Figure 7. Block diagram of the CPR unit.

3.5. Carrier phase recovery The carrier phase recovery Unit (CPRU), whose block diagram is shown in Figure 7, consists of a conventional decision-directed phase recovery loop for coherent data demodulation. Since the EC-BAID algorithm is demonstrated to be phase invariant [3], CPRU is placed right after the adaptive detector so that it can operate at symbol rate Rs instead of chip rate. In the CPRU, the signal yðkÞ coming out of EC-BAID is first counter rotated by an amount equal # to the current estimate y# ðkÞ of the carrier phase y according to zðkÞ ¼ yðkÞejyðkÞ [5, 17]. Subsequently, it is sent to a hard detector so as to provide an estimate c#k of the k-th QPSK data symbol. Signals zðkÞ and c#k are used by the phase error detector (PED) to build-up the phase error signal ey ðkÞ ¼ Imf#ck zðkÞg which represents the input of the loop filter. We resorted to a second-order loop in order to compensate for the residual frequency jitter at the output of the AFCU. The relevant loop equations are: y# ðk þ 1Þ ¼ y# ðkÞ þ mðkÞ ð8Þ mðkÞ ¼ mðk  1Þ  gð1 þ rÞey ðkÞ þ gey ðk  1Þ

ð9Þ

As with all decision-directed loops, the QPSK hard detector of the CPRU introduces a p=2 ambiguity in the phase recovery process. This means that the two I/Q components may be swapped and/or they can be sign-reversed after phase correction. This ambiguity is solved with the aid of the 24-symbols long unique word, which is periodically inserted in the data frame to ease frame sync. The CPRU is also provided of a phase lock detector to indicate phase acquisition.

4. DIGITAL RECEIVER HARDWARE IMPLEMENTATION The receiver design phase was supported by extensive computer-based BER verification, for both floating point and bit-true models. Subsequently, the digital section of the receiver has been implemented by resorting to programmable logic device as far as the ancillary receiver’s functionalities is concerned and to an ASIC plug-in board for the EC-BAID IMD detector. 4.1. Digital front-end FPGA implementation A customarily designed digital board, named PROTEO, mainly consisting of two programmable logic devices field programmable gate array (FPGAs), was used for the implementation of Copyright # 2003 John Wiley & Sons, Ltd.

Int. J. Satell. Commun. Network. 2003; 21:39–64

50

L. FANUCCI ET AL.

the ancillary receiver’s functionalities, such as digital front-end processing, acquisition and synchronization loops. The first device is devoted to base-band conversion, chip-matched filtering, linear interpolation for signal re-sampling, and carrier frequency recovery. The second one features CTAU, CCTU and SACU for signal detection and timing synchronization. It also contains an interface unit for information exchange with the DSP during initial receiver start-up and signal monitoring/measurement during receiver operation. Synthesis results revealed an occupation of about 93% of available logic cells of PROTEO board. 4.2. EC-BAID ASIC design The EC-BAID digital design was carried out by using a ‘top-down’ approach based on very high-speed integrated-circuit hardware description language (VHDL) to obtain a technologyindependent, highly flexible description at the behavioural level. Once a ‘synthesizable VHDL’ description was reached, gate-level design was performed using the logic synthesis tool SynopsysTM : The whole design was initially targeted towards the AlteraTM Flex EPF10k100 devices for a preliminary verification, and subsequently the EC-BAID detector was re-targeted to the 0:18 mm HCMOS8D technology provided by ST Microelectronics. At each design step, the VHDL model (behavioural, synthesizable, and gate level) was automatically verified against the simulation results of the FORTRAN bit-true model. The ASIC design database concerning the EC-BAID detector was then transferred to the Blast Fusion tool by MagmaTM via electronic data interchange format (EDIF) for design back-end operations (such as floor planning, placement, routing and post-layout verification). The ASIC design resulted to be pad-limited, thus particular care was devoted to reduce the number of I/Os as much as possible. This limitation was circumvented by resorting to proper output multiplexing and serial loading of EC-BAID configuration parameters. Furthermore, the device provides a main output consisting of the useful signal’s despread samples, plus an auxiliary output for enhanced observability which, according to a proper circuit configuration parameter, can be selected among the modulus of vector xðeÞ ; the recovered carrier phase, the standard correlator output or the local digital AGC gain. The resulting ASIC, whose layout is shown in Figure 8, contains only 23 kgates plus 23 kbits of static RAM, which are totally equivalent to roughly 55 kgates: The technology used is the HCMOS8D CMOS process characterized by 0:18 mm gate length, up to six levels of metal layers, and a 1:3 V minimum core power supply. A maximum clock frequency of 32:768 MHz has been achieved, corresponding to a maximum chip-rate of 4:096 Mchip=s; twice the maximal chip rate required for the MUSIC receiver. The overall chip area size is 2:33 mm2 while the relevant chip power consumption amounts to roughly about 12:5 mW at the maximum clock frequency of 32:768 MHz: The selected package is the TQFP44, with 44 pins and an external side length of 10 mm: The resulting low-hardware complexity and low-power consumption performance make this circuit well suited to integration into a low-cost hand-held mobile user terminal. In addition, the feasibility of a single-chip alldigital CDMA modem, was investigated, too. Preliminary design results demonstrated that the whole receiver could be implemented in a single ASIC with roughly 110 kgate complexity and the overall power consumption should amount to about 100 mW at the higher chip rate. The board with the ASIC to be connected to the PROTEO test board is depicted in Figure 9; while the photo in Figure 10 shows the integration of the PROTEO test board with the EC-BAID ASIC board. Copyright # 2003 John Wiley & Sons, Ltd.

Int. J. Satell. Commun. Network. 2003; 21:39–64

DESIGN, IMPLEMENTATION AND VERIFICATION

51

Figure 8. Final EC-BAID ASIC layout.

5. REAL-TIME TEST BED For CDMA interference mitigation receiver verification under practical working conditions (satellite channel, 70 MHz intermediate frequency) a real-time test bed has been designed and developed. A sketch of the test-bed architecture is reported in Figure 11. The all-digital receiver is provided with an analog front-end board that performs anti-alias filtering, amplitude control and direct IF analog-to-digital conversion. Signal generation is carried out by means of an off-the-shelf arbitrary waveform generator (AWG) loaded with the desired CDMA signal generated by off-line computer simulation. The AWG outputs a Copyright # 2003 John Wiley & Sons, Ltd.

Int. J. Satell. Commun. Network. 2003; 21:39–64

52

L. FANUCCI ET AL.

Figure 9. Board with the EC-BAID ASIC.

modulated CDMA signal at the first intermediate frequency fIFD ¼ 4:464 MHz: After upconversion to 70 MHz; a precision noise generator injects Gaussian downlink noise on the CDMA signal. The whole test bed is fully controlled by means of a custom developed LabVIEWTM application for PC which first of all sets the CDMA transmitter (including the number of active signals, power ratio versus useful channel, frequency and phase offsets, time delays, etc.) and programs the AWG using an optimized FORTRAN code. The control application also provides initialization of the receiver parameters through RS232 serial interface and via DSP. This has been actually charged to supply the receiver settings parameter both to the digital front-end section (PROTEO board) and to the ASIC plug-in board (via PROTEO board). The desired Copyright # 2003 John Wiley & Sons, Ltd.

Int. J. Satell. Commun. Network. 2003; 21:39–64

DESIGN, IMPLEMENTATION AND VERIFICATION

53

Figure 10. Picture of the PROTEO test board with the EC-BAID ASIC board (upper left).

SNIR is also set through the application controlling both a spectrum analyser, to estimate the useful signal power, and the noise generator, to insert the right amount of noise. Alternatively, it is also possible to set manually a needed value of SNIR ratio. Furthermore, the LabVIEWTM application allows the monitoring of the main internal signals, such as the CDMA base-band signal, the CTAU and CCTU lock detectors, the loop gain factor (SACU gain) and so on. Receiver BER performance is also estimated by direct counting, both for the conventional correlation detector and for the EC-BAID. This is actually carried on by the DSP, which eventually passes back the results to the master PC via RS232. Copyright # 2003 John Wiley & Sons, Ltd.

Int. J. Satell. Commun. Network. 2003; 21:39–64

54

L. FANUCCI ET AL.

Control via IEEE488

Mixer

TP

TestPoint fIF

fIFD

NOISE GENERATOR

AWG

Download via IEEE488

Arbitrary Waveform Generator

Signal +MAI

Low-pass Filter

fLO

B-P Filter 1

TP Signal +MAI +Noise

T TX SECTION

L.O. Ext.in

RS 232

PLL

L.O.

TP

to RECEIVER MUSIC Receiver BOARD Digital Section

IF

IF 70MHz 1V p-p Diff.out

TP

VGA

fIF

BALUN

IF N

B-P Filter 2

TP Vagc RX SECTION AGC

Figure 11. Overall test-bed configuration.

Figure 12. LabVIEWTM GUI for modulator parameters setting. Copyright # 2003 John Wiley & Sons, Ltd.

Int. J. Satell. Commun. Network. 2003; 21:39–64

DESIGN, IMPLEMENTATION AND VERIFICATION

55

Figure 13. LabVIEWTM GUI for MAI parameters setting.

This way, we built a very flexible test bed, much flexible in signal parameters setting and in receiver monitoring and controlling. As an instance of such a feature, Figure 12 shows the transmitter set-up control panel as it appears on the master PC display. The test-bed operator can set the signal bit rate and chip rate, the sequence type and the number of active channels. Furthermore, advanced settings allow to set the interference parameters, such as sequences order, normalized delay, frequency and phase offset and power margin w.r.t. the useful channel. Figure 13 shows the graphical user interface (GUI) for transmitter advanced settings. Once the set-up dialog box has been closed, parameters setting is passed to an optimized FORTRAN code to produce the signal to be loaded in the AWG memory, and the receiver setting takes place. Figure 14 shows the relevant GUI panel, which allows to review the receiver configuration and setting before they are effectively send to the receiver via RS232 serial interface. Finally, the signal transmission can start, and the application provides results in terms of receiver control and measurements. Several external signals, as well the main internal ones, are kept under control. For improved testability, the PROTEO breadboard was also equipped with an external plug-in digital to analog parallel converter (DAC) board, especially designed for the receiver, including anti-image analog filtering, not shown in Figure 10. The DAC board allows to display digital internal waveforms on a standard oscilloscope for monitoring purpose, such as the receiver flags (CTAU signal presence, CPRU and AFCU lock indicators, etc.) as well as the receiver signals at different stage of the demodulation process and the synchronization ones (CCTU sampling timing signal, AGC gain level, CPRU recovered phase signal, AFC error frequency signal and so on). The test-bed flexibility allows to run-time change the signal to be analogically converted for representation, by re-configuring appropriate multiplexers on FPGAs Copyright # 2003 John Wiley & Sons, Ltd.

Int. J. Satell. Commun. Network. 2003; 21:39–64

56

L. FANUCCI ET AL.

Figure 14. LabVIEWTM GUI for receiver parameter setting.

via the DSP. As an example of such test-bed feature, Figure 15 shows the measured IF power spectrum for the transmitted CDMA signal at 70 MHz with the parameter configuration specified in the figure caption. The signal bandwidth turns out to be about 2:5 MHz: The spectrum of the base-band converted CDMA signal (I component) at the output of the CMF is represented in Figure 16, in the same configuration as in Figure 15. As expected, the spectrum replicas due to sampling operation are located at
8:192 MHz; being 4Rc the signal sampling rate. An estimate of the received SNIR is also provided by the LabVIEWTM application. 6. PERFORMANCE RESULTS The error counting procedure for BER measurement is actually carried out by the DSP. As we mentioned before, a 24-symbol unique word is periodically inserted in the data stream to ease Copyright # 2003 John Wiley & Sons, Ltd.

Int. J. Satell. Commun. Network. 2003; 21:39–64

DESIGN, IMPLEMENTATION AND VERIFICATION

57

Figure 15. Measured IF power spectrum for the transmitted CDMA signal in the following operating conditions: Eb =N0 ¼ 10 dB; L ¼ 64; P =C ¼ 6 dB; Rb ¼ 64 kb=s; Rc ¼ 2048 kchip=s:

frame synchronization and to solve phase ambiguity before error counting takes place. An extensive measurements campaign aiming at evaluating the receiver BER in realistic heavy-MAI conditions has been carried out at the project’s testing facilities. All of the experimental results presented hereafter have been derived in the presence of a synchronous pilot signal code-division multiplexed with the useful traffic channel, but spread with a non-orthogonal extended Gold sequence, to ease code acquisition as discussed in Section 3.2. The pilot-to-useful carrier power ratio P =C was set to 6 dB as a good trade-off between interference level due to residual crosscorrelation and sync accuracy provided by pilot-aided operations. Furthermore, the interfering channels are assumed equi-powered and the useful carrier-to-single interfering power ratio is generally set to C=I ¼ 0 dB: The overlapping sequence is an extended Gold sequence, different from that of the pilot signal, and user discrimination is made resorting to Walsh Hadamard signature codes. Also, we defined mild, medium and heavy load conditions when the total number of active channels (encompassing the useful, the pilot and the interfering ones) is N ¼ L=4; L=2 and 3L=4; respectively. The update step size of the EC-BAID algorithm, introduced in Section 3.3, was set to gBAID ¼ 213 ¼ 1:44  104 for mild-medium loading and gBAID ¼ 215 ¼ 3:05  105 for heavy loading. The leakage factor, also defined in Section 3.3 was set to the optimum value gleak ¼ 23 ¼ 0:125; which was determined through this extensive testing campaign. Copyright # 2003 John Wiley & Sons, Ltd.

Int. J. Satell. Commun. Network. 2003; 21:39–64

58

L. FANUCCI ET AL.

Figure 16. Measured power spectrum of the base-band converted CDMA signal (I component) at the output of the CMF in the following operating conditions: Eb =N0 ¼ 10 dB; L ¼ 64; P =C ¼ 6 dB; Rb ¼ 64 kb=s; Rc ¼ 2048 kchip=s; fd ¼ 4Rc :

Concerning notation, in the following charts, the label ‘sw’ and empty marks denote numerical results obtained by computer simulation of the whole system (including all the sync loops) carried out with floating point precision while the label ‘hw’ and colour filled marks refer to test-bed measured results. We discuss now some of the most significant experimental BER results of our testing campaign. Figure 17 compares simulation and experimental measurements of the EC-BAID’s BER performance carried out for L ¼ 64 and Rc ¼ 512 kbit=s in the absence of MAI (apart from the pilot which is always assumed active). Finally, Figures 18 and 19 present simulated and measured BER performance for L ¼ 128 and mild loading (that means there are L=4 ¼ 32 overall active users) for Rc ¼ 1024 kchip=s and Rc ¼ 2048 kchip=s; respectively. The BER performance is reported here for both the simple correlator (CR) and the ECBAID. They are both compared with the simulated results, and an implementation loss of about 1:5 dB is experienced in both cases, which is mainly due to the analog front-end section, as confirmed by an extensive preliminary hardware testing and verification campaign. Copyright # 2003 John Wiley & Sons, Ltd.

Int. J. Satell. Commun. Network. 2003; 21:39–64

DESIGN, IMPLEMENTATION AND VERIFICATION

59

Figure 17. Experimental BER performance (useful signal+non-orthogonal pilot).

7. CONCLUSIONS AND PERSPECTIVES The following main conclusions can be drawn: (i) The CDMA test bed with IMD feature described in the previous sections proved fully functional and flexible enough to allow the testing of the receiver under realistic MAI conditions. Thanks to the IMD feature, the prototype HW implementation of the CDMA detector achieved considerable gain in terms of SNR (up to 3 dB) even at uncoded BER of 5  8  102 (see Figure 18) which is representative of a coded system operating point. Admittedly, though the CDMA signal format considered in this study does not match exactly the current commercial standards, the high flexibility of the HW architecture (direct IF sampling @ 16:384 Msample=s with all-digital signal processing, multi-rate transmission from 4 up to 128 kb=s with a maximum chip rate of 2:048 Mchip=s with variable-length codes) allows to derive significant results for 2nd - or 3rd generation (2G or 3G) CDMA-based systems. (ii) The test bed is particularly innovative as far as the circuits for pilot-aided synchronization of the received CDMA signal are concerned. More specifically, the approach encompassing a low-complexity parallel circuit for code acquisition supplemented by a traditional loop for fine tracking proved effective even in the presence of strong MAI. (iii) The phase-invariance feature of the EC-BAID allowed adoption of a conventional decision-aided second-order loop operating at symbol rate at the detector output for Copyright # 2003 John Wiley & Sons, Ltd.

Int. J. Satell. Commun. Network. 2003; 21:39–64

60

L. FANUCCI ET AL.

1 7 6 5

Rb=16 Kbit/s, Rb=1024 Kchip/s, L=128

4 3 2

0.1

BER

7 6 5 4 3 2

0.01 7 6 5 4 3 2

EC-BAID sw CR sw EC-BAID hw CR hw

0.001 0

3

6

9

12

Eb/N0 (dB) Figure 18. Experimental BER performance comparison: useful signal+pilot+30 asynchronous interferers ðC=I ¼ 0 dBÞ:

carrier phase tracking. Concerning carrier frequency recovery, a simple AFC circuit with minor modifications showed to be still effective, in spite of the strong MAI. Alternatively pilot-based carrier phase estimation can also be envisaged. (iv) The design and implementation of the prototype CDMA detector demonstrated that the addition of an interference mitigation feature to a handheld 3G receiver entails only a modest complexity increase. The ancillary functions of synchronization and performance monitoring can be carried out by proper modifications of traditional schemes even in the presence of a strong MAI. Thus, the impact of IMD on the surrounding modem functionalities can be kept to a minimum. As a consequence, envisaging a satellite (cellular) network with interference-mitigating downlink to combat inter-beam (intercell) interference is fully realistic. This would bring remarkable benefits as far as overall network capacity is concerned [16]. (v) The whole single-user IMD receiver can be easily integrated into a single-chip ASIC. The design flow adopted when implementing ancillary functions on FPGAs allows an easy reuse of the resulting architecture to come to an overall integration of the receiver into a single ASIC with modest complexity and power consumption. More can be done from the theoretical as well as the experimental point of view to assess the performance of adaptive interference mitigation on a selective radio channel. Although the role of satellites in 3G system is currently still being debated, it seems reasonable to assume that the satellite network can be harmonized with IMT terrestrial networks to carry out Copyright # 2003 John Wiley & Sons, Ltd.

Int. J. Satell. Commun. Network. 2003; 21:39–64

DESIGN, IMPLEMENTATION AND VERIFICATION

61

1 7 6 5

Rb=32 Kbit/s, Rc=2048 Kchip/s, L=128

4 3 2

0.1

BER

7 6 5 4 3 2

0.01 7 6 5 4 3 2

EC-BAID sw CR sw EC-BAID hw CR hw

0.001 0

3

6

9

12

Eb/N0 (dB) Figure 19. Experimental BER performance comparison: useful signal+pilot+30 asynchronous interferers ðC=I ¼ 0 dBÞ:

two fundamental functions: on the one hand, enhancing the limited broadcasting capabilities of 3G terrestrial networks, and on the other acting as a gap filler in poorly covered areas. Thus, the design and low-cost implementation of dual-mode terminals operating on similar carrier frequencies appears a mandatory issue. Moreover, further studies and experimentation on the performance of interference mitigation in a mixed satellite/terrestrial environment appear a necessary follow-up. This is the approach pursued by ESA, which is about to complete the development of a comprehensive 3G W-CDMA satellite UMTS (S-UMTS) test bed [18] that will allow a complete characterization of the the EC-BAID performance in the forward link of a multibeam multi-satellite (mobile) environment [19]. This activity will allow testing of concurrent multirate transmissions with orthogonal variable spreading factor (OVSF) channellization codes and will also feature integration of Rake reception with IMD, for path diversity exploitation. The SUMTS test bed is also being extended under European Commission funding [20] to support the terrestrial UMTS UTRA radio interface, and will thus be able to verify the EC-BAID performance in a terrestrial environment.

ACKNOWLEDGEMENTS

The authors are much indebted to the many people who contributed to the start-up, the advancement, and the completion of this project. Special thanks to Edoardo Letta, now with Austriamicrosystems, Italy, and to Gianmarino Colleoni of ST Microelectronics, Italy. Copyright # 2003 John Wiley & Sons, Ltd.

Int. J. Satell. Commun. Network. 2003; 21:39–64

62

L. FANUCCI ET AL.

REFERENCES 1. Duel-Hallen A, Holtzman J, Zvonar Z. Multiuser detection for CDMA systems. IEEE Personal Communication 1995; 2(2):46–58. 2. Romero-Garcia J, De Gaudenzi R, Giannetti F, Luise M. A frequency error resistant blind CDMA mitigating detector. IEEE Transactions on Communications 2000; 48(7):1070–1076. 3. Fanucci L, Letta E, De Gaudenzi R, Giannetti F, Luise M. VLSI implementation of a CDMA blind adaptive interference-mitigating detector. IEEE Journal On Selected Areas in Communications 2001; 19(2):179–190. 4. Honig M, Madhow U, Verdu! S. Blind adaptive multiuser detection. IEEE Transactions on Information Theory 1995; 41(4):944–960. 5. De Gaudenzi R, Garde T, Vanghi V. Performance analysis of decision-directed maximum-likelihood phase estimator for M-PSK signals. IEEE Transaction on Communications 1995; 43(12):3090–3100. 6. De Gaudenzi R, Giannetti F, Luise M. Capacity of a multibeam, multisatellite CDMA mobile radio network with interference-mitigating receivers. IEEE Journal on Selected Areas in Communication 1999; 17(2):204–213. 7. D’Ercole S. Prestazioni di Ricevitori Adattativi a Cancellazione di Interferenza per Sistemi DS-SS-CDMA, Tesi di Laurea, University of Pisa, 2000 (in Italian). 8. Giannetti F, De Gaudenzi R, Luise M. Advances in satellite CDMA transmission for mobile and personal/ communications. Proceedings IEEE 1996; 84:18–39. 9. Gardner FM. Interpolation in digital modems-part I: Fundamentals. IEEE Transactions on Communications 1993; 41(3):501–507. 10. Hogenauer EB. An economical class of digital filters for decimation and interpolation. IEEE Transactions on Acoustics, Speech, and Signal Processing 1991; 29(2):155–162. 11. Samueli H. The design of multiplierless FIR filters for compensating D/A converter frequency response distortion. IEEE Transactions on Circuits and Systems 1988; 35(8):1064–1066. 12. McClellan JH, Parks TW, Rabiner LR. A computer program for designing optimum FIR linear phase digital filters. IEEE Transactions on Audio and Electroacoustics 1973; 21(6):506–526. 13. Bellanger M. Digital Processing of Signal}Theory and Practice. Scientific Director T.R.T. Le Plessis-Robinson: France, 1993. 14. Fanucci L, De Gaudenzi R, Giannetti F, Luise M. VLSI implementation of a signal recognition and code acquisition algorithm for CDMA packet receivers. IEEE Journal On Selected Areas in Communications 1998; 16(9):1796–1808. 15. De Gaudenzi R, Giannetti F, Luise M. Signal synchronization for direct-sequence code-division multiple access radio modem. European Transactions on Telecommunication 1998; 9(1):73–87. 16. De Gaudenzi R, Luise M, Viola R. A digital chip timing recovery loop for band-limited direct-sequence spreadspectrum signals. IEEE Transactions on Communications 1993; 41(11):1760–1769. 17. Mengali U, D’Andrea NA. Synchronization Techniques for Digital Receivers. Plenum Press: New York, 1997. 18. Caire G, De Gaudenzi R, Gallinaro G, Lyons R, Luglio M, Ruggieri M, Vernucci A, Widmer H. ESA satellite wideband CDMA radio transmission technology for the IMT-2000/UMTS satellite component: features & performance. Proceedings IEEE GLOBECOM ’99, Rio De Janeiro, Brazil, 5–9 December 1999. 19. Boudreau D et al. Wideband-CDMA for the UMTS/IMT-2000 satellite component. IEEE Transactions on Vehicular Technology 2002; 52(2):306–331. 20. Home page of the European Commission VIRTUOUS (Virtual home UMTS on Satellite) IST Project: http:// www.ebanet.it/virtuous.htm.

AUTHORS’ BIOGRAPHIES Luca Fanucci was born in Montecatini Terme, Italy, in 1965. He received the Doctor Engineer (summa cum laude) and the Research Doctor degrees, both in electronic engineering, from the University of Pisa, Pisa, Italy, in 1992 and 1996, respectively. From 1992 to 1996, he was with the European Space Agency’s Research and Technology Center, Noordwijk, The Netherlands, where he was involved in several activities in the field of VLSI for digital communications. He is currently a Research Scientist of CNR, the Italian National Research Council, at the Centro Studio per Metodi e Dispositivi per Radiotrasmissioni (CSMDR), Pisa. Since 2000, he has been an Assistant Professor of Microelectronics at the University of Pisa, Italy. His main interests are in the areas of System-on-Chip design, high-speed CMOS integrated circuit design, VLSI architectures for real-time image and signal processing, and applications of VLSI technology to digital communication systems. Copyright # 2003 John Wiley & Sons, Ltd.

Int. J. Satell. Commun. Network. 2003; 21:39–64

DESIGN, IMPLEMENTATION AND VERIFICATION

63

Riccardo De Gaudenzi was born in Italy in 1960. He received his Doctor Engineer degree (cum Laude) in electronic engineering from the University of Pisa, Italy in 1985 and the PhD from the Technical University of Delft, The Netherlands in 1999. From 1986 to 1988 he was with the European Space Agency (ESA), Stations and Communications Engineering Department, Darmstadt (Germany) where he was involved in satellite telecommunication ground systems design and testing. In particular, he followed the development of two new ESA’s satellite tracking systems. In 1988, he joined ESA’s Research and Technology Centre (ESTEC), Noordwijk, The Netherlands where is presently the head of the Communication Systems Section. He is responsible for the definition and development of advanced satellite communication systems for fixed and mobile applications. He is also involved in the definition of the Galileo European Navigation System. In 1996 he spent 1 year with Qualcomm Inc., San Diego USA, in the Globalstar LEO project system group under an ESA fellowship. His current interest is mainly related with efficient digital modulation and access techniques for fixed and mobile satellite services, synchronization topics, adaptive interference mitigation techniques and communication systems simulation techniques. Filippo Giannetti was born in Pontedera, Italy, on 16 September 1964. He received the Doctor Engineer (cum laude) and the Research Doctor degrees in electronic engineering from the University of Pisa, Italy, in 1989 and from the University of Padova, Italy, in 1993, respectively. In 1988/1989, he spent a research period at TELETTRA (now ALCATEL), in Vimercate, Milan, Italy, working on error correcting-codes for SONET/SDH radio modems. In 1992 he spent a research period at the European Space Agency Research and Technology Centre (ESA/ESTEC), Noordwijk, The Netherlands, where he was engaged in several activities in the field of digital satellite communications. He served as the Publications Manager of the IX edition of the Tyrrhenian International Workshop on Digital Communications (Lerici, Italy, 7–10 September 1997), and of the URSI Symposium ISSSE’98 (Pisa, Italy, 29 September–2 October 1998). From 1993 to 1998 he has been a Research Scientist at the Department of Information Engineering of the University of Pisa, where he is currently Associate Professor of Telecommunications. His main research interests are in mobile and satellite communications, synchronization and spread-spectrum systems. Marco Luise is a Full Professor of Telecommunications at the University of Pisa, Italy. He was born in Livorno, Italy, in 1960 and received the Doctor Engineer (cum Laude) and Research Doctor degrees in Electronic Engineering from the University of Pisa, Italy, in 1984 and 1989, respectively. In 1987 he spent 1 year at the European Space Research and Technology Centre (ESTEC), Noordwijk, The Netherlands, as a Research Fellow of the European Space Agency (ESA). In the years 1988–1991 he was a Research Scientist of CNR, the Italian National Research Council, at the Centro Studio Metodi Dispositivi Radiotrasmissioni (CSMDR), Pisa, and from 1991 to 1999 he was an Associate Professor of the Department of Information Engineering of the University of Pisa. In 1991, 1993, 1995 and 1997 he chaired the V, VI, VII and IX editions of the Tyrrhenian International Workshop on Digital Communications, respectively, and in 1998 he was the General Chairman of the URSI Symposium ISSSE’98. He’s currently Technical Co-Chairman of the 7th International Workshop on Digital Signal Processing Techniques for Space Communications and of the Conference European Wireless 2002. Prof. Luise is a senior member of the IEEE, was an Editor of the IEEE Transactions on Communications and has served as the co-editor of the ’98 Special Issue on Signal Processing in Telecommunications of the European Transactions on Telecommunications. He’s now co-editor of the IEEE Journal of Selected Areas in Communication special issue on Signal Synchronization in Digital Transmission Systems and Editor for Communication Theory of the European Transactions on Copyright # 2003 John Wiley & Sons, Ltd.

Int. J. Satell. Commun. Network. 2003; 21:39–64

64

L. FANUCCI ET AL.

Telecommunications. His main research interests lie in the broad area of communication systems, with particular emphasis on mobile and satellite transmission and CDMA wireless communications. He is the leader of the research project MUSIC financed by the European Space Agency. Massimo Rovini was born in Pisa, Italy, in 1974. He received the Doctor Engineer degree (summa cum Laude) in Electronic Engineering from the University of Pisa, Italy, in 1999. Since 2000 he has been PhD student at the Department of Information Engineering of the University of Pisa. Currently he is with the European Space Agency, at the European Space Research & Technology Centre, Noordwijk, The Netherlands, as a research fellow by the Communication Section of the Technical and Operating Systems Department. His main interests lie in the broad area of VLSI architectures for real-time signal processing, mainly relating to digital communication systems, and in hardware implementation and testing issues.

Copyright # 2003 John Wiley & Sons, Ltd.

Int. J. Satell. Commun. Network. 2003; 21:39–64