Design of a Compact Series-Connected AC Voltage ... - IEEE Xplore

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 51, NO. 4, AUGUST 2004

933

Design of a Compact Series-Connected AC Voltage Regulator With an Improved Control Algorithm Ming Tsung Tsai Abstract—This letter presents an improved control algorithm for the compensation of ac source voltage fluctuation. The proposed idea can be used to regulate both the overvoltage and undervoltage situations with only unidirectional energy transmission. Theoretical analysis has been achieved based on the power flow theory. A case study is demonstrated by means of a prototype experiment to prove its performance and effectiveness. Index Terms—Power flow, unidirectional energy transmission, voltage fluctuation.

I. INTRODUCTION

Fig. 3. Experimental waveforms. (a) Conventional V =f control method at the resonant speed. (b) Proposed V =f control method at the same resonant speed.

motor are the same as the motor parameters in Section III. Fig. 3(a) shows the oscillating current waveform of the conventional V =f control method without any compensator at the resonant speed. However, Fig. 3(b) shows the improved waveform of the proposed V =f control method with the compensator at the same resonant speed. The good current waveform is obtained. The gains of the dynamic current compensator used in the experiments are the optimal gains, k1 = 0:25 and k2 = 1, the same as in Section III. V. CONCLUSION In this letter, stability improvement of V =f -controlled induction motor drive systems by a dynamic current compensator was proposed. The proposed method uses a dynamic current compensator to improve the stability of the V =f -controlled induction motor drive systems. This method is easy to implement and helps eliminate the oscillations causing the instability of the V =f -controlled induction motor drive systems. REFERENCES [1] D. W. Novotny and J. H. Wouterse, “Induction machine transfer functions and dynamic response by means of complex time variables,” IEEE Trans. Power App. Syst., vol. PAS-95, pp. 1325–1335, July/Aug. 1976. [2] M. Daijyo, I. Hosono, H. Yamada, and Y. Tunehiro, “A method of improving performance characteristics of general purpose inverter,” Trans. Inst. Elect. Eng. Jpn., vol. 109-D, no. 5, pp. 339–346, May 1989. [3] L. Ben-Brahim, “Improvement of the stability of the V =f controlled induction motor drive systems,” in Proc. IIEEE ECON’98, 1998, pp. 859–864. [4] J. H. Youm and B. H. Kwon, “An effective software implementation of the space-vector modulation,” IEEE Trans. Ind. Electron., vol. 46, pp. 866–868, Aug. 1999. [5] J. W. Choi and S. K. Sul, “Inverter output voltage synthesis using novel dead time compensation,” IEEE Trans. Power Electron., vol. 11, pp. 221–227, Mar. 1996.

An ac voltage regulator (AVR) can provide a well-regulated voltage source, and is becoming more and more important due to the rapid decrease in the quality of power systems [1]–[7]. Generally, there are many different structures to implement an AVR, including a conventional transformer with mechanical or electrical tap changer, an adjustable transformer driven by motor, a saturated reactor, a regulative series transformer controlled by a dc-to-ac inverter which is supplied by a diode rectifier or a switching mode rectifier, a high-frequency ac-to-ac electronic transformer with or without a high-frequency transformer, and so on. The adjustable transformer or saturated reactor-based AVR has some disadvantages, including the use of bulky transformers and/or a slower response than switching-based structures. In contrast to this, the high-frequency switching-based AVR has the merit of a smaller size as it uses high-frequency switching technology. However, it normally allows only unidirectional ability of voltage regulating (voltage sag or voltage swell), and it is not suitable for a large-scale system. Thus, the regulative series transformer controlled by a dc-to-ac inverter seems to be a good choice as it manages only the fluctuation part of the source voltage, and has a smaller size than the topology that is processing the full-load power. Fig. 1(a) shows the circuit configuration of this type of AVR. However, this structure consists of a complicated two-stage control algorithm in order to deal with the bidirectional ability of voltage regulation, thus resulting in the cost increase and the switching efficiency decrease. This letter deals with a diode rectifier structure instead of the switching rectifier stage, and proposes an improved control algorithm to allow two-directional voltage regulation, even if the proposed rectifier uses only a diode structure. With the proposed control algorithm, it can be used to deal with both directions of voltage regulation, but only with unidirectional energy flow. As the front stage is a diode rectifier, it has merits including a higher switching efficiency, a simpler circuit structure, and a simpler control algorithm than the conventional two-switching-stage structure shown in Fig. 1(a). II. OPERATION THEORY ANALYSIS The inverter in the proposed system is controlled for the load voltage to be sinusoidal with constant root-mean-square (rms) value. It is in Manuscript received November 20, 2001; revised November 28, 2003. Abstract published on the Internet May 20, 2004. This work was supported by the National Science Council, R.O.C., under Research Project NSC91-2213-E-218034. The author is with the Department of Electrical Engineering, Southern Taiwan University of Technology, Tainan, Taiwan, R.O.C. (e-mail: mttsai@ mail.stut.edu.tw). Digital Object Identifier 10.1109/TIE.2004.831769

0278-0046/04$20.00 © 2004 IEEE

934

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 51, NO. 4, AUGUST 2004

TABLE I MAXIMUM REQUIREMENT OF V AMPLITUDE OVERVOLTAGE RATIOS

FOR

DIFFERENT

(a) TABLE II REQUIRED V AMPLITUDE DUE TO THE DIFFERENT LOAD POWER FACTORS

(b)

(c)

(d) Fig. 1. (a) Conventional two switching-stage topology of series-connected AVR system. (b) Phasor diagram of the proposed inverter operating in the undervoltage situation. (c) Phasor diagram of the proposed inverter operating in the overvoltage situation. (d) Phasor diagram when the phase-lag shift strategy is used for the capacitance load situation.

phase with the source voltage for voltage sags, and has a different angle from the source voltage based on the load power factor for voltage swells. In both situations, the inverter always operates for supplying power to the load from the front diode rectifier so as to avoid energy feeding back to the dc bus. The system changes the regulation mode according to the detected dc-bus voltage condition, and the inverter regulates the load voltage continuously. The power delivered by the inverter in steady state can be shown as follows:

= VL 0 VS VS 3 S i = Vi I L = P L 1 0 VL Si = Pi + Q i Vi

(1) (2) (3)

where Pi and Qi are the related transferred average power and reactive power from the inverter stage, VS is the source voltage, VL is the load voltage, IL is the load current, and Si is the apparent power from the

inverter stage. From (2), it can be seen that if you maintain the inverter voltage Vi in quadrature with the load current IL , regardless of source voltage variations (sag or swell), the transferred real power from the inverter stage will be zero. Thus, the inverter will become a self-controlled dc-bus reactive power compensator, with no need for a dc power supply, resulting in the simplest possible circuit design. However, [2] has shown that this control idea has a limited load power factor for undervoltage condition, and cannot be used in all load voltage situations. Reference [2] also suggests a method that minimizes the inverter power rating instead of zeroing the real power flow. It is obtained by maintaining the inverter output voltage in phase with the source voltage, regardless of source voltage variations. However, from the above equation, it is clear that the energy will be fed back into the proposed inverter if the load voltage is controlled in phase with the source in the voltage swell situation (VS > VL ). Thus, a bilateral two-stage solution will result so as to transfer the bilateral power flow. Otherwise, the circuit will implement an angle displacement between the source voltage and the load voltage to ensure unidirectional energy flow. This is also the key point of the proposed control algorithm. That is, the proposed inverter will regulate the load voltage by injecting an in-phase term during undervoltage situation, and by injecting a voltage that has a different angle from the source voltage to decrease the load voltage. Fig. 1(b) shows the phasor diagram of the proposed inverter operating with source undervoltage, where IL1 shows the inductance load, and IL2 shows the capacitance load. Regardless of load power factor, it shows the inverter voltage Vi differs from the load current IL1 and IL2 with a phase angle smaller than 90 , thus ensuring the power flows from the diode rectifier through the proposed inverter to the load. The regulation capability is dependent on the turns ratio of the series transformer. When voltage swells occur, the inverter output voltage is then regulated continuously in quadrature with the load current so as to zero the power flow through the inverter. Fig. 1(c) shows the phase diagram including the inductance load (IL1 ) and the capacitance load (IL2 ). Based on Fig. 1(c), the following equations can be obtained: VL

cos  = VS cos ; Vi = VS sin  0 VL sin :

(4) (5)

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 51, NO. 4, AUGUST 2004

935

TABLE III FED BACK POWER DUE TO THE DIFFERENT DISPLACEMENT PHASE ANGLES

Thus, it can be seen that the amplitude of the desired inverter output voltage Vi is dependent on the load power factors. The lower the load power factor, the smaller the VI amplitude; a maximum amplitude of Vi occurs in the unity power factor, and a minimum amplitude occurs in the pure reactance load. A different phase-shift strategy related to Fig. 1(c) may be used for limited voltage variation ranges, such as those using only the phase-lag shift strategy for all load situations in order to simplify the phase-shift algorithm. Fig. 1(d) shows the case where the phase-lag algorithm is used in the capacitance load situation, thus, the desired amplitude of the inverter output voltage will be as follows: Vi2 = VS sin  + VL sin :

(6)

It is clear that the desired inverter output voltage is larger than that of (5). Table I shows the maximum requirement of Vi amplitude for the resistive load due to the load overvoltage ratio. Thus, for a range of 20% overvoltage, the maximum requirement of Vi amplitude will be 0.663 per unit (p.u.) of the load. However, the amplitude of Vi is dependent on the load power factor. Table II shows the required Vi amplitude corresponding to the different load power factor for 20% source overvoltage. However, if a phase displacement smaller than the in-quadrature of the load current is adopted, then the energy will be fed back through the inverter to the dc bus. Table III shows the possible fed-back power for an example of 20% overvoltage of the unity power factor. As the inverter is certain to have some operating loss, the inverter is required to withstand some energy fed to the dc bus to supplement the operating loss. Thus, the practically required Vi amplitude is smaller than the above shown in Tables II and III.

The detailed power circuit of the proposed system is shown in Fig. 2(a). It includes the front stage implemented by a diode rectifier, and the inverter stage which is connected in series with the utility input through a transformer. Fig. 2(b) depicts the control block diagram of the inverter stage. It is mainly composed of a dc voltage regulator (DCR) for the outer loop, and an ac voltage regulator (ACR) for the inner loop, where Ki S (1 + tz 1 S )(1 + tz 2 S ) ACR = Kd : (1 + tp1 S )(1 + tp2 S )

(b) Fig. 2. (a) Detailed power circuit of the proposed AVR system. (b) Control block diagram of the proposed scheme.

III. CIRCUIT DESIGN

DCR = Kp +

(a)

(7) (8)

In the outer loop, the average value of the load voltage is detected by the rectified circuit and sent to the DCR. The DCR is used to regulate the load voltage to ensure that the command is followed. The inner ACR loop is designed for reducing the variation effects of the load current and dc-bus voltage, and enhancing system stability. The main control difference between voltage sag and voltage swell is the additional + 90 or 090 phase shifter, depending on the related leading or lagging load power factor. The amplitude of this in-quadrature signal

is controlled by the dc-bus voltage variation. It generates a zero-level signal in voltage sags, and a proportional dc signal according to dc-bus voltage variations in voltage swells. This control strategy is based on the concept of energy balance. The proposed inverter operates in such a way that when the voltage swells, the in-phase command of the ACR loop will cause the energy to feed back to the dc bus, resulting in a dc-bus increase. If the dc-bus voltage increases above the permitted levels, then the in-quadrature signal will be produced, and its amplitude corresponds to the error between the permitted dc-bus voltage and the actual dc-bus voltage. The in-quadrature signal is fed into the ACR loop to shift the ACR loop command. If the phase-shift quantity of the command is insufficient, the energy will be fed back continuously to the dc capacitor, also resulting in an increase of dc-bus voltage. A larger dc control signal will be generated, resulting in a larger in-quadrature term being sent to shift the ACR loop command until the energy can no longer be fed back, thus a new status of energy balance is established. In contrast to conventional 90 phase-shift control, the proposed idea has the merit of an optimum phase-shift quantity, resulting in a minimum phase shift of load voltage.

936

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 51, NO. 4, AUGUST 2004

30 F. The control circuit is composed of analog circuits including

operation amplifiers and multipliers. The reference sine-wave signal is generated from the zero-crossing detector and a bandpass filter. The cosine-wave signal is obtained by shifting the sine wave to a 90 displacement. Fig. 3 shows the experimental results of the RL load including three different conditions of source voltage, where R = 12 , L = 10 mH. Fig. 3(a) shows the corresponding source voltage and load voltage during voltage sags which show that the source voltage is about 90 Vrms , and the load voltage has been boosted to the desired quantity of about 100 Vrms ; also, the waveform shape has been modified by the proposed inverter to a sinusoidal waveform. Fig. 3(b) shows the normal source voltage situation, where the source and load voltage are nearly the same amplitude. Fig. 3(c) shows the corresponding source voltage and load voltage during voltage swells. The source voltage is about 110 Vrms which shows clearly the proposed inverter has decreased the source voltage amplitude, and a phase-lagging shift effect has been verified. Fig. 3(d) shows the measured efficiency in the R load case, and a comparative efficiency between the proposed system and the conventional two-switching-stage system have also been shown in this figure. As the proposed system has only a single switching stage, the entire efficiency should be higher than the two-switching-stage system. This has been verified in Fig. 3(d). V. CONCLUSION A series-connected ac voltage regulator was developed. A simple and effective control strategy for the compensation of source voltage fluctuation has been used. It provides two benefits of having high efficiency and it easy to implement, due to the proposed control algorithm. Prototype experiments have proven the system performance. The proposed method is suitable for the entire source voltage variation. It shows the developed method to be valuable for the power electronics industry. REFERENCES

Fig. 3. Experimental results of RL load. (a) Undervoltage case. (b) Normal voltage case. (c) Overvoltage case. (d) Measured efficiency.

IV. EXPERIMENTAL TEST A prototype of a 1-kVA rating system related to Fig. 2(a) has been used to verify the proposed idea. The power circuit consists of a diode rectifier and a voltage-source PWM inverter . The switching frequency is about 10 kHz, the source voltage is about 100 Vrms normally, and the dc-bus voltage is 140 V, Cdc = 1200 F, L1 = 2 mH, and C1 =

[1] Y. S. Lee, D. K. W. Chen, and Y. C. Cheng, “Design of a novel ac regulator,” IEEE Trans. Ind. Electron., vol. 38, pp. 89–94, Apr. 1991. [2] C. C. Chen and D. M. Divan, “Simple topologies for single phase as line conditioning,” IEEE Trans. Ind. Applicat., vol. 30, pp. 406–412, Mar./Apr. 1994. [3] X. Z. Zhang, “Analysis and design of switched-mode ac/ac voltage regulator with series connected compensation,” in Proc. IEE Power Electronics and Variable-Speed Drives Conf., Oct. 1994, pp. 181–187. [4] S. Rathmann and H. A. Warner, “New generation UPS technology, the delta conversion principle,” in Conf. Rec. IEEE-IAS Annu. Meeting, San Diego, CA, Oct. 1996, pp. 2389–2395. [5] S. J. Jeon and G. H. Cho, “A series-parallel compensated uninterruptible power supply with sinusoidal input current and sinusoidal output voltage,” in Proc. IEEE PESC’97, 1997, pp. 297–303. [6] W. E. Brumsickle, R. S. Schneider, G. A. Kuckjiff, D. M. Divan, and M. F. Mcgranaghan, IEEE Trans. Ind. Applicat., vol. 37, pp. 212–217, Jan./Feb. 2001. [7] S. J. Chiang, C. Y. Yen, and K. T. Chang, “A multimodule parallelable series-connected PWM voltage regulator,” IEEE Trans.Ind. Electron., vol. 48, pp. 506–516, June 2001.