ISSN: 2347-9302 (Online)
IJEEEAR Vol. 2, ISSUE 2, Feb. 2014
Design of a Threshold Voltage Adjustable Digital Buffer Sunil Kumar Niranjan, Amit Kumar Singh, Ashutosh Dwivedi Dept. of Electrical Engineering, School Of Engineering Shiv Nadar University Gautam Budh Nagar, India
[email protected],
[email protected],
[email protected] Abstract—This paper illustrates the buffer circuit which is useful in the digital circuit as a input buffer. In the design of input buffer two inverters can be used in which one has the threshold voltage control ability and the other one acts as a basic inverter. It is shown that the combination of these two inverters works as a buffer circuit which provides the slicing ability of the input signal of the digital input signal. Keywords - Threshold Voltage Controllable Inverter, Self Biased, High Speed Buffer.
I. INTRODUCTION In many digital circuits it is observed that after the generation of the square wave from the generator the waveform no longer remains in its original form after some time due some additive noise. Due to this, effect could be seen as the increase of its rise time and fall time where main reason is the capacitance of transmission path. Therefore, the waveform directly can not be used for driving the large set of digital circuit demanding perfect wave shape. One solution to this attenuation problem in wave shape could be address using buffer circuit in which buffer circuit removes all of these undesirable effects. A typical buffer has a switching voltage (threshold voltage) control inverter which provides slicing ability in the input wave. Due to this ability of buffer circuit slow rise time and fall time effect could be removed as well as output width could also be controlled. Furthermore, gain of the buffer also removes the attenuation of the input wave. This paper shows the comparison of basic buffer with proposed buffer circuit with the help of parameters like input waveform slicing range and delay and power minimization. THRESHOLD VOLTAGE CONTROLLABLE INVERTER Threshold voltage of the inverter is the input voltage of the inverter where the input voltage and output voltage both are same. Vth = Vin = Vout In the basic inverter circuit (fig.1) for ‘level-1’ equations, its threshold voltage can be written as [1],
Where Kr
=
, Kn and Kp are the
transconductance parameters of the NMOS and PMOS respectively. From equation-1, it is clear that, to vary the threshold-voltage, voltage Vdd and the transconductance parameter ratio (Kr), needed to vary. However, Kr could be changed during the time of manufacturing for the inverter therefore this option does not lead to effective means for controlling the threshold voltage, Vtn and Vtp as well as these parameters are also fabrication dependent. Alternative, approach is to change in ‘Biasing Voltage’ (Vdd). Because threshold voltage is directly proportional to the biasing voltage, so if increase /decrease in biasing voltage affects the threshold voltage proportionally.
II.
(
)
……(1)
Vth = (
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IJEEEAR 2014
Fig.1 Basic inverter This approach is also not effective because output high voltage is also decreased with the supply voltage Vdd. As well as the high output voltage of the buffer circuit an not be decreased further beyond a fix value. This result into that range of the variation of the supply voltage Vdd is also fixed. For example, if minimum value of the output high voltage is 2V then we can’t vary Vdd below the 2V.
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ISSN: 2347-9302 (Online)
IJEEEAR Vol. 2, ISSUE 2, Feb. 2014
Consider a case when Kr = 1 and we can fix this value by Wp = 2.5Wn (Wp = channel width of PMOS and Wn = channel width of NMOS) [1], Vtn = 1V and Vtp = -1V. Therefore, it leads to Vth = Vdd/2. In this case we can vary the threshold voltage in the range of 1-2.5V. But if we want the threshold voltage variation with high gain then this technique is not so good and upper limit is also defined till 2.5V. In order to have effective approach in which technique should be such that gain of the inverter should remain constant and threshold voltage variation range should be high. This condition can be achieved by the circuit depicted in fig.2 [2]. In this circuit threshold voltage of the inverter can be varied with much larger range in comparison to previous case and results into acceptable gain.
waveform pulse remain symmetric and the second inverter changes waveform in same phase to get the perfect input wave. For the case when Wp = Wn for the second inverter, it will sliced the input wave at the middle level of its total swing [1] so that final output pulse will be symmetric. Variation of threshold voltage with respect to control voltage is shown in fig.4 the minimum threshold voltage is 1 volt and the maximum threshold voltage is 3.0 V. Output high voltage of the first inverter with respect to control node with the loading effect of second inverter is shown in fig.4. In this arrangement output high voltage does not go below the 3.6 V, which is greater than the threshold voltage of the second inverter.(these results are for the (W/L)1=25/2, (W/L)2= 25/2, (W/L)3= 20/2, (W/L)4=40/2, (W/L)5= 40/2, (W/L)6=10/2, (W/L)7=25/2, (W/L)8=10/2 in um order) Supply voltage Vdd
M5
M1
M2
M8
Threshold voltage Control Node
Input
output M7 M3
M4
M6
Ground
Fig.2 Threshold voltage controllable inverter
Fig.3 Digital Input Buffer Circuit
Left most part of this circuit is the inverter and right hand part is useful in controlling the threshold voltage of the inverter. Its output is dependent on the difference voltage of the both input node [3]. It is useful for the high frequency, its 3-dB bandwidth is the order of GHz [3]. Due to self biasing of the inverters and negative feedback it minimize impact of process parameters, supply voltage and ambient temperature (PVT) variations [3]. III. DIGITAL INPUT BUFFER In order to design digital buffer, one another inverter could be connected in series with this inverter. It is achieved such that the first, circuit’s input waveform will be sliced at desired voltage so that output
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IJEEEAR Vol. 2, ISSUE 2, Feb. 2014 arrangement, threshold voltage will be 0V for the input imperfect pulse and maximum value of the threshold for the input pulse is 2.0V. The value of Vdd is 5V. For control node voltage 2.5V output is shown in fig.6. In this waveform input pulse has 1 usec rise time and fall time which is removed in output pulse.
Fig.4 Threshold Voltage Variation w.r.t. Control Node Voltage
Fig.5 Test Circuit
IV. TEST CIRCUIT In test circuit fig.5 input voltage is superimposed with 1V voltage level because minimum threshold voltage is 1V for the inverter. By this
Fig.6 Output Result V.CONCLUSION The circuit described in the paper has advantages such that it uses less no. of transistors along with the less number processing stages (only 2) involved. As well as, it reduces the effect of unwanted capacitance. These features make it very fast and low power consumption buffer with threshold voltage adjustable ability.
[1] Sung-Mo Kang and Yusuf Leblebici, CMOS: Digital Integrated Circuits Analysis and Design, 3rd edition, Tata McGraw-Hill Edition, Page no.-197-212. [2] M. Bazes, “ Two Novel Fully Complementary Self-Biased CMOS Differential Amplifiers,” IEEE journal of Solid State Circuits, Vol.26, no.2, Feb. 1991. [3] Vladimir Milovanovic and Horst Zimmermann, “Analysis of Single-Stage Complementary Self-Biased CMOS Differential Amplifiers,” IEEE conference, Copenhagen, 1213 Nov, 2012.
REFERENCES
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