Design of An Efficient Active Noise Cancellation Circuit for In-ear Headphones Kuan-Hung Chen1, Hong-Son Vu2, Kuo-Yuan Weng1, Jin-Huang Huang3, Yu-Ting Tsai3, Yu-Cheng Liu3, and Wen-Hung Wang4 E-mail: {kuanhung,jhhuang,yucliu,P9943427}@fcu.edu.tw,
[email protected],
[email protected], and
[email protected] 1 Department of Electronic Engineering, Feng Chia University, Taichung 40724, Taiwan, R.O.C 2 Ph.D. Program in Electrical and Communications Engineering, Feng Chia University, Taichung 40724, Taiwan, R.O.C 3 Department of Mechanical and Computer-Aided Engineering, Feng Chia University, Taichung 40724, Taiwan, R.O.C 4 MERRY Electronics CO. LTD, Taichung Industrial Park, Taichung, Taiwan, R.O.C Abstract—This paper proposes an efficient active noise cancelling (ANC) circuit design for the in-ear headphones. We develop a hardware oriented Least Mean Square (LMS) adaptive algorithm, and design a modified high-performance feed-forward ANC architecture which only uses one microphone to effectively cancel broadband noise for the in-ear headphones. The proposed ANC circuit design has been successfully implemented through adopting the standard cell-based design flow based on the TSMC 90nm CMOS technology. Besides, the proposed design has been verified under versatile noisy scenarios for its real-time ANC performance by using a Field Programmable Gate Array (FPGA) platform. Experimental results show that the proposed highperformance circuit design can reduce disturbing noise of various frequency bands very well, and outperforms the existing works. The proposed design can attenuate the broadband pink noise between 300 Hz to 900 Hz, with a maximum performance of 18 dB. Moreover, the proposed design can achieve 406.5 k samples/sec data throughput rate at operating frequency of 50 MHz, at the costs of 111.7 k gates and power consumption of 4.47 mW.
Fig. 1. Proposed feed-forward hardware-oriented LMS algorithm for ANC inear headphone applications.
sampling period, the previous works cannot reduce broadband noise well. To overcome this challenge, we propose a hardware oriented LMS algorithm which distinguishes the conventional one in the following aspects: (1) compute the required multiply-accumulate operations in individual filtering tap; (2) increase data throughput rate by adopting the pipelining technique to shorten the critical path delay time of the circuit. Besides, a novel method of modifying the feed-forward ANC algorithm is also proposed to reduce the complexity in hardware design for the in-ear headphones by using only one microphone. The proposed ANC circuit design has been successfully implemented through adopting the standard cellbased design flow based on the TSMC 90nm CMOS technology. In addition, the proposed design has been verified under versatile noise scenarios for its real-time ANC performance by using a field programmable gate array (FPGA) platform, i.e. XILINX ZEDBOARD. Furthermore, a SOUNDCHECK Control Systems Analyzer is adopted to measure the noise canceling performance. A mannequin with a dedicated audio earphone mounted in its ear is employed to observe the residual noise signal. The performance of noise cancellation can reduce broadband noise very well. The proposed design can attenuate the broadband pink noise between 300 Hz to 900 Hz, with a maximum performance of 18 dB. The rest of this paper is organized as follows. Section II proposes the modified feed-forward ANC algorithm. The VLSI implementation of the proposed work is presented in Section
Keywords—architecture design, active noise cancellation, inear headphone, LMS, VLSI design
I.
INTRODUCTION
With the advent of semiconductor technology in recent years, the demands for ANC headphones have emerged in portable devices. These adaptive ANC techniques require longlength adaptive filters with hundreds of taps for effective noise cancellation, which also increases the computational cost and results in slow convergence. The Filtered-x Least Mean Square (FxLMS) algorithm is by far the most widely used Least Mean Square-based algorithm in adaptive filtering where the secondary path is estimated online by updating the coefficients of Finite Impulse Response (FIR) filter iteratively. Modern portable devices require stereo audio channels and low-power consumption. To achieve high-performance and low-power consumption, a dedicated VLSI hardware architecture design is indispensable. Therefore, we develop a hardware oriented LMS adaptive algorithm and design a modified high-performance feed-forward ANC architecture to effectively cancel broadband noise for the in-ear headphones. The well-known LMS algorithm and its variations have been adopted in previous works [1]-[5] to actively cancel noise. Because the algorithm includes numerous multiply-accumulate operations and divisions which are necessary to be computed within one
c 978-1-4799-5230-4/14/$31.00 2014 IEEE
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Fig. 3. The proposed hardware architecture for the ANC in-ear headphone.
where p'm (n) is the coefficient vector of the estimated primary path P(z).
Fig. 2. The simulation results of the proposed ANC system for canceling (a) noise of a moving train, (b) broadband pink noise, and (c) broadband white noise.
p'm (n) = [ p'0 (n), p'1 (n),.., p' M −1 (n)]T ,݉ ൌ Ͳǡ ͳǡ Ǥ Ǥ ǡ ܯെ ͳ (3) In summary, we can write the LMS algorithm as follows:
III. In Section IV, the experimental and validation results are presented. Finally, Section V concludes the work. II.
PROPOSED HARDWARE ARCHITECTURE FOR THE ANC INEAR HEADPHONE
e' (n) = d ' (n) + y(n) d ' (n) =
¦ p'
m
( n)x ( n − m), ݉ ൌ Ͳǡ ͳǡ ʹǡ Ǥ Ǥ ǡ ܯെ ͳ
¦ s'
m
( n) x ( n − m ), ݉ ൌ Ͳǡ ͳǡ ʹǡ Ǥ Ǥ ǡ ܯെ ͳ
(4)
( n) x (n − m ), ݉ ൌ Ͳǡ ͳǡ ʹǡ Ǥ Ǥ ǡ ܯെ ͳ
(5)
m=0
d ' (n) =
This paper presents an ANC in-ear headphone which uses a dedicated ANC circuit design. Besides, a modified highperformance feed-forward ANC algorithm which requires only one microphone is also provided to reduce the complexity in hardware design for the in-ear headphones. This proposed algorithm uses the internal model (the estimated primary path) to synthesize the error signal e(n) instead of to measure the error signal e(n) by using a physical error microphone. Hence, the adaptive feed-forward ANC system requires only one microphone for each ear, resulting in low-cost and simplification in designing the ANC in-ear headphones. Fig. 1 describes a block diagram of the proposed in-ear headphone design based on the proposed modified feed-forward ANC algorithm. In Fig. 1, an available estimate of P(z) is presented by P’(z). The dedicated ANC in-ear headphone is equipped with a microphone (reference microphone) outside per ear-cup. The second microphone mounted inside per ear of mannequin is used for measuring the passive attenuation when the noise passed through the ANC in-ear headphone passively. Thus, we can get the impulse response of the estimate function P’(z) as the relation between the sound pressure level Pin inside the earcup and the sound pressure level Pout outside the ear-cup, (P=Pin/Pout) [3]. To get the impulse response of the estimate function S’(z), an off-line modeling technique in [2] was adopted to estimate S(z) during a training stage. The error microphone is replaced by a microphone inside the ear of a mannequin. At the end of training, the estimated model is fixed and used for active noise control. In this paper, the excitation signal white noise is used as for identifying the adaptive system. After the off-line modeling is completed, the ANC inear headphone is operated in the active noise cancellation mode. An identification process shown in (1) and (2) is adopted to recognize the error signal of the ANC system. M −1
M −1
x ' (n) =
M −1
¦ p'
m
m=0
y (n) =
L −1
¦ w (n) x(n − l ), ݈ ൌ Ͳǡ ͳǡ ʹǡ Ǥ Ǥ ǡ ܮെ ͳ l
(6)
l =0
e' (n) = d ' (n) + y(n)
(7)
wl (n + 1) = wl (n) + μx' (n − l )e(n), ݈ ൌ Ͳǡ ͳǡ ʹǡ Ǥ Ǥ ǡ ܮെ ͳ (8) Equations (4) to (8) form the modified feed-forward ANC algorithm which requires only single microphone. If the sampling frequency and operating frequency of the proposed design are respectively 48 kHz and 50 MHz, the proposed design has to finish the signal conversion and all calculations within the following time period, as shown in (9). 50 MHz/48 kHz ≅ 1041 clock cycles
(9)
Therefore, all the computations including two 64-tap FIR filters respectively for S'(z) and P'(z), and a 24-tap (i.e. L=24) adaptive filter W(z) must be finished in 1041 clock cycles. Before entering a circuit design, we investigate the proposed model by using Matlab. Then, we propose a hardware architecture composed of a 24-tap adaptive filter and the two 64-tap estimated FIR filters for realizing the proposed modified feed-forward ANC algorithm. To have a complete examination, three tests were used in three scenarios: (1) playing the noise of a moving train; (2) playing broadband pink noise; (3) playing broadband white noise. In all the experiments, the FxLMS filter has filter order of 24 and step size of 0.01. Meanwhile, the two estimated FIR filters P’(z) and S’(z) have filter order of 64. For the first experiment, the noise of a moving train was used as a noise source. This experiment simulates the scenario when the ANC in-ear headphone is affected by the external noise. Fig. 2(a) illustrates the noise canceling performance in the time domain of the proposed design, with the blue line and the red line are the sound in the acoustic cavity close to a listener’s ear before and after the ANC in-ear headphone operates respectively. For the
(1) (2)
m =0
600
(a)
(b)
Fig. 4. The chip layout and micro-photo of the proposed ANC circuit design. (a) The chip layout (including I/O pads). (b) The micro-photo of the implemented chip.
Fig. 5. The FPGA verification platform for testing proposed ANC headphone.
specifications when operated at the clock frequency of 50 MHz are shown in Table I. In addition, the chip layout and microphoto of the proposed design are illustrated in Fig. 4. The proposed design with its dedicated hardware architecture only takes 123 clock cycles to finish the computations. The chip size is 0.923×0.924 mm2 including the IO pads. The total gate count is 111.7 k and total on-chip RAM memory is 180 Byte. The maximum operating frequency of the proposed design is 100 MHz, with a corresponding power consumption is 13.976 mW. Meanwhile, the required operating frequency of this design is 50 MHz. The implementation results show that the proposed ANC circuit design consumes only 4.47 mW when operated at the supply voltage of 1.0 V and the operating frequency of 50 MHz.
second and third experiments, broadband pink noise and broadband white noise were set up as the first experiment to evaluate the performance of the proposed model. Experimental results are shown in Fig. 2(b) and Fig. 2(c) respectively. Results of three experiments prove that the performance of the proposed ANC in-ear headphone at stationary state and the design can cancel a variety of noise very well. According to the model and the corresponding experimental results respectively shown in Fig. 1 and Fig. 2, this paper proposes a hardware architecture, as illustrated in Fig. 3 for the ANC in-ear headphone which includes the FIR filters for implementing P’(z) and S’(z), the 24-tap LMS unit, and the adder for summing the noise signal and the anti-noise signal. III. IMPLEMENTATION OF THE PROPOSED ANC IN-EAR HEADPHONE
TABLE I.
SPECIFICATIONS OF THE PROPOSED DESIGN
Item Technology Chip size Power supply Power consumption Required operating frequency Maximum operating frequency Gates Throughput
This section includes the details of the proposed 24-tap hardware architecture, as shown in Fig. 3, for the ANC in-ear headphone. In Fig. 3, the reference signal x(n) is sensed by a reference microphone close to the noise source before it propagates to a canceling-loudspeaker. This signal is then sent to two estimated FIR filters, i.e. P’(z) and S’(z), where the data are processed to produce two output signals d’(n) and x’(n), respectively. Then, these two signals and reference signal x(n) are sent to the proposed 24-tap LMS block. The 24-tap LMS block then updates new parameters for 24 weights of adaptive filter according to (6) to (8) to generate an anti-noise signal y(n). This anti-noise signal then drives the cancelingloudspeaker to produce a canceling sound that attenuates the primary acoustic noise in the ANC in-ear headphone. To synchronize the I/O signals for blocks of this proposed ANC circuit design, three signals clk, rst and start are used. And in order to reduce the computing time for the overall system, a three-stage pipelining is adopted to shorten the critical path delay time for the equations from (4) to (8). The first stage is used to compute the two estimate FIR filters S’(z) and P’(z), the second stage is used to compute the adaptive filter W(z), and the final stage is to compute the updating coefficients for adaptive filter. Due to the high-performance requirements, lowpower, the single multiply-accumulate (MAC) FIR filter is well suited [6]. Hence, this paper adopted the techniques in [6] to realize the proposed hardware architecture for the ANC in-ear headphone. The proposed design has been implemented by following the standard cell-based design flow with TSMC 90nm CMOS cell technology. The detailed chip features and
Specifications TSMC 90nm CMOS technology 0.923×0.924 mm2 Core Power 1.0 V 4.47 mW 50 MHz 100 MHz 111.7 k gates 406.5 k samples/sec
IV. PERFORMANCE EVALUATION AND COMPARISON Fig. 5 shows the system verification model of the proposed ANC circuit design on real-time commercial hardware of ZedBoard. Considering the hardware efficiency of a design, we adopt the performance index of data throughput rate. Table II briefly lists the comparison about the data throughput rate of the proposed design and other works. From the results in Table II, we can see that the proposed ANC circuit design implementation is much faster than that in [2] and [5]. Besides, Table II also shows the noise canceling performance of the proposed design when compared with that in [3]-[5], with excitation signals are broadband noises. A broadband pink noise with a frequency range of 300 Hz to 1 kHz is generated by using a computer to evaluate spectrum of the residual noise signal on the mannequin. The solid line in Fig. 6 illustrates the background noise while the dash dot line displays the noise reduction performance of the proposed ANC circuit design. The remaining dotted line indicates the noise signal attenuated after passing through in-ear headphone passively. Experimental result in Fig. 6 shows that the proposed design performs well in
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TABLE II.
COMPARISON OF THE DATA THROUGHPUT RATE AND NOISE REDUCTION PERFORMANCE FOR THE PROPOSED DESIGN AND PREVIOUS DESIGNS
Performance Item and noise type Application Platform Operating frequency (MHz) Data processing rate (sample/cycles) Throughput (samples/sec) Noise reduction at 300-700 Hz Noise reduction at 700-900 Hz Noise reduction at 350-400 Hz Noise reduction at 250-300 Hz
Proposed Design
Kuo, Morgan [2]
In-ear headphone FPGA 50 1/123 406.5 k 8-18 dB 4-8 dB Around 9 dB None
Duct DSP 10 1/341 29.33 k Unlisted Unlisted Unlisted Unlisted
Guldenschuh, Höldrich [3] Headphone DSP Unlisted Unlisted Unlisted 7-15 dB 5-7 dB Around 10 dB 15 dB
Zhang, Wu, and Qiu [4] Headphone DSP Unlisted Unlisted Unlisted 10-14 dB None Around 12 dB Around 6 dB
Chang, Li [5] Headphone Low-cost microcontroller 40 1/355 112.68 k None None 15-20 dB Around 20 dB
TABLE III. CHARACTERISTICS OF THE PROPOSED DESIGN, LOW-COST MICROCONTROLLER AND DSP Low-cost DSP Proposed design microcontroller (TMS320C6747) (PIC24H) Frequency 50 MHz 40 MHz 456 MHz Dedicate on Basic operations Complex math Math Function ANC operations (floating-point) 32k+external 2k Memory (Byte) 180 memory Resolution Low Low High Core supply voltage (volt) 1.0 3.3 1.2 Core Power consumption 4.47 237.6 [7] 585.84 [8] (mW) Item
reducing the broadband noise at frequency range of 300 Hz to 900 Hz, with a maximum performance of 18 dB. Table II also shows that the proposed design and the works [3], [4] achieved the best performance at frequency range of 300 Hz to 700 Hz. The noise canceling performance of the proposed design is better than that in [3] and [4], with a performance of around 818 dB. Fig. 6 also shows that the proposed design still yields an ANC up to over 900 Hz whereas the design [4] only cancels noise up to 700 Hz. To reduce the cost for the ANC headphones, the work [5] proposed using a low-cost microcontroller unit as a core component in the ANC headphone. However, this design only performs well in reducing small broadband noises. As a result, [5] could only attenuate broadband noises at 350 Hz to 400 Hz and 250 Hz to 300 Hz, with the achievable performances are respectively 1520 dB and 20 dB. In addition, the characteristics of the proposed design, a PIC24H and a floating-point DSP are briefly presented in Table III. From the characteristics in Table III, we can see that the proposed design only consumes a lowpower of 4.47 mW, which is much lower than that of a PIC24H and a floating-point DSP. This shows that the proposed design is very robust in supporting portable devices, which were originally relied on a digital signal processor or low-cost microcontroller. Moreover, the proposed ANC in-ear headphone outperforms the works [3]-[5] in attenuating broadband noise with a frequency range of 300 Hz to 900 Hz, and broadband noise range can attenuate by the proposed ANC in-ear headphone is much larger than that in [5]. V. CONCLUSION A modified feed-forward ANC algorithm has been proposed for single microphone active noise cancellation. In addition, a hardware-oriented LMS algorithm has also been presented in this work for implementing the high-performance ANC circuit design for the in-ear headphones. The proposed design has been successfully implemented following the standard cell-based design flow with TSMC 90nm CMOS technology. The performance of noise cancellation based on
Fig. 6. Spectrum of the residual noise signal for cancelling broadband pink noise, solid line: background noise, dotted line: ANC OFF, dash dot line: ANC ON.
the proposed ANC circuit design is verified and then compared with that of other works. Experimental results show that the proposed design can attenuate the broadband pink noise at a broadband frequency of 300 Hz to 900 Hz, with a maximum noise reduction of 18 dB. Furthermore, the proposed design can achieve 406.5 k samples/sec data throughput rate when operated at 50 MHz, at the costs of 111.7 k logic gates and 4.47 mW power dissipation only. ACKNOWLEDGMENT This work has been supported in part by the National Science Council, Taiwan, R.O.C., under Grants NSC 101-2622-E-035017-CC2. REFERENCES [1] S. M. Kuo and D. R. Morgan, “Active noise control: A tutorial review,” Proc. IEEE, vol. 87, no. 6, pp. 943-973, Jun. 1999.
[2] S. M. Kuo and D. R. Morgan, Active Noise Control Systems: Algorithms and DSP Implementation, New York: Wiley, 1996.
[3] M. Guldenschuh and R. Höldrich, “Prediction filter design for active [4] [5] [6] [7] [8]
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noise cancellation headphone,” IET. Signal Process., vol. 7, no. 6, pp. 497-504, Aug. 2013. L. Zhang, L. Wu, and X. Qiu, “An intuitive approach for feedback active noise controller design,” Applied Acoustics, vol. 74, no. 1, pp. 160-168, Aug. 2012. C. Y. Chang and S. T. Li, “Active noise control in headsets by using a low-cost microcontroller,” IEEE Trans. Ind. Electron., vol. 58, no. 5, pp. 1936-1942, May 2011. Designing for optimal results. High-Performance DSP using Virtex-4 FPGAs. R. Edition 1.0. DSP solutions. [Online]. Available: www.xilinx.com/publications/archives/books/ PIC24H Family Data Sheet. High-Performance, 16-bit Microcontrollers. [Online]. Available: www.microchip.com/downloads/en/DeviceDoc/70175d.pdf The power consumption of the Texas Instruments C6748/46/42. [Online]. Available: http://processors.wiki.ti.com/index.php/C6747/45/43_Power_Consumpti on_Summary
