Design of Multi Level Converter for Interline Power Flow Controller ...

International Journal of Emerging Technology and Advanced Engineering Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 3, Issue 11, November 2013)

Design of Multi Level Converter for Interline Power Flow Controller with Variable Inputs in SIMULINK/MATLAB M. Venkateswarareddy1, Dr. Bishnu Prasad Muni2,Ph.D, Dr. A.V.R. S. Sarma3, Ph.D, 1

Research Scholar(Ph.D), Electrical Engineering Dept., University college of Engineering, Osmania University, A.P India 2 Additional General Manager, Bharat Heavy Electricals Limited(R&D), BALA NAGAR, Hyderabad, India 3 Professor EE Dept., University College of Engg, Osmania University Hyderabad, India

Abstract--The Interline Power Flow Controller (IPFC) a concept for the compensation and effective power flow management of multi-line transmission systems. In its general form, the IPFC employs two or more number of converters (VSC) with a common dc link, each to provide series compensation for a selected line of the transmission system. Because of the common dc link, any converter within the IPFC is able to transfer real power to any other and thereby facilitate reactive power transfer among the lines of the transmission system. Since each converter is also able to provide reactive power compensation, the IPFC is able to carry out an overall real and reactive power compensation of the total transmission system. This capability makes it possible to equalize both real and reactive power flow between the lines, transfer power from overloaded to under loaded lines, compensate against reactive voltage drops and the corresponding reactive line power, and to increase the effectiveness of the compensating system against dynamic disturbances. The paper explains the basic theory and operating characteristics of the five level inverter based IPFC with phasor diagrams, and simulated waveforms in SIMULINK/MATLAB

In addition converter-based FACTS controllers are capable of independently controlling both active and reactive power flow in the power system. Series connected converter-based FACTS controllers include Static Synchronous Series Compensator (SSSC), Unified Power Flow Controller (UPFC) and Interline Power Flow Controller (IPFC). A SSSC is a series compensator with ability to operate in active/inductive modes to improve the system stability. The IPFC includes a Static Synchronous compensator (STATCOM) and a SSSC that share a common dc-link. The IPFC consists of two or more SSSC with a common dc-link so, each SSSC contains a VSC that is in series with the transmission line through a coupling transformer, and injects a voltage with controllable magnitude and phase angle into the line. IPFCs provide independent control of reactive power of each individual line, while active power could be transferred via the dc-link between the compensated lines.

Keywords - AC transmission, FACTS, IPFC, line compensation, 5 level inverter, power flow controller, Series compensation, VSC.

A. Inter line power flow controller Generally, the Interline Power Flow Controller (IPFC) is a combination of two or more independently controllable static synchronous series compensators (SSSC) which are solid-state voltage source converters which inject an almost sinusoidal voltage at variable magnitude and couples via a common DC link as shown in fig.1 Conventionally series capacitive compensation fixed thyristor controlled or SSSC based is employed to increase the transmittable real power over a given line and to balance the loading of a normally Encountered multi-line transmission system at their dc terminals and connected to the ac systems through their series coupling transformers.

Section II

Section I I. INTRODUCTION Flexible AC Transmission Systems (FACTS) based on either Voltage or Current Source converters (VSC/CSC) these can be used to control steady-state as well as dynamic/transient performance of the power system. Converter-based FACTS controllers when compared to conventional switched capacitor/reactor and thyristor based FACTS controllers such as Static Var Compensator (SVC) and Thyristor-controlled Series Capacitor (TCSC) have the advantage of generating/absorbing reactive power without the use of ac capacitors and reactors.

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This means X1 = X2 and V1pqmax = V2pqmax. Although in practice system1 and system2 could be likely different due to different transmission line voltage, impedance and angle. We assumed system1 is arbitrarily selected to be the prime system for which free controllability of both real and reactive line power flow is stipulated to derive the constraints the free controllability of system1 forces on the power flow control of system2. A phasor diagram of system1 illustrated in Figure 3 defines the relationship between V1s, V1r, Vx1 (the voltage phasor across X1) and the inserted voltage phasor V1pq, with controllable magnitude and angle. V1pq is added to the sending end voltage V1self = V1s + V1pq. So V1self –V1r, the difference sets the compensated voltage phasor or Vx1 across reactance X1. As angle is varied over its full 360 degree range, the end of phasor V 1pq moves along a circle with its center located at the end of phasor V1s. The area within this circle defines the operating range of phasor V1pq. Thus the line1 can be compensated. The rotation with angle of phasor V1pq modulates both the magnitude and the angle of phasor Vx1 and, therefore, both the transmitted real power, P1r, and the reactive power, Q1r, vary with 1.

Vj

DC common link Vi

SSSC

SSSC

Vi

Fig.1. IPFC model

With this scheme in addition to providing series reactive compensation, any converter Cn be controlled to supply active power to the common dc link from its own transmission line.

Fig. 1. Basic two inverter power flow controller

B. Operating principle and phasor diagram for interline power flow controller For simplicity for explaining of 3 phase IPFC a single phase IPFC was taken. The IPFC(Fig. 2) is designed with a combination of the two series connected VSC which can inject a voltage with controllable magnitude and phase angle at the fundamental frequency, while DC link voltage maintained at a desired level. The common dc link is represented by a bidirectional link (P 12 =P1pq = P2pq) for real power exchange between two voltage sources. Transmission line reactance represented by X1 has a sending end bus with voltage Phasor V1s and a receiving end voltage Phasor V1r. The sending end voltage Phasor of Line2, represented by reactance X2, is V2s and the receiving-end voltage Phasor is V2r. Simply, all the sending-end and receiving-end voltages are assumed to be constant with fixed amplitudes, V1s = V1r = V2s = V2r =1pu., and with fixed angles resulting in identical transmission angle s1 = s2 for the two systems. The two line impedances and the rating of the two compensating voltage sources are also assumed to be identical.

Fig.3. PHASOR Diagram Of System

This process requires the voltage source representing Inverter 1 (V1pq) to supply and absorb both reactive, (Q1pq), and real, (P1pq) power. Section III II. DESIGN O F F IVE LEVEL CONVRTER By using modern power electronics more revolution came in power generation and transmission. In the area of conversion (from AC- DC or DC to AC) the ability to continuous vary in output voltage, frequency and amplitude by selecting the right device. And their control. The high level inverters generate the ac voltages by switching at different levels at high frequency with semiconductor devices. The waveforms generated the inverter is differ from the general sinusoidal waveform because of rectangular switching.

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A. Three Phase 5 Level Inverter The above fig shows the three phase five level inverter which consists of totally twenty four IGBTS for three legs (Each leg consists 8 IGBTS) which are protected by anti parallel diodes. These anti parallel diodes are working as snubber circuits for protecting the IGBTS. For simplicity in explaining the operation of three phase inverter single leg was taken, the construction of single leg and design of capacitor explained in next paragraphs. One pole (or phase) of the five level inverter is shown in Fig.5. where two additional poles would be required for a three phase VSI. Each IGBT is equipped with average conducting diode and a diode clamp to ensure that the voltage across a single IGBT does not exceed the voltage cross the supply. The lower four IGBT require the complementary gating pulses of upper four IGBTS of the same number. That is if 43 is on, then 43' must be off. The gate logic to achieve the five voltage levels at the output Va is shown in Table 1.

Fig.5 Single leg five level inverter

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International Journal of Emerging Technology and Advanced Engineering Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 3, Issue 11, November 2013) B. Various Strategies for The Control Of The Output Of Five Level Inverter Voltage and frequency were investigated on the basis of number --of IGBT switching’s per fundamental cycle and the distortion factor defined as the rms value of the harmonic voltages normalized to the maximum fundamental voltage and divided by the harmonic number.

The dc voltage E can vary to control the output voltage. The first option (pulse width control) works well over very small ranges of output voltage, but over a large range, the distortion factor becomes prohibitively large for most transmission line applications.

Table1. Switching sequence for five level inverter

OUTP UT (VA)

+2E +E 0 -E -2E

I G B T 1 1 0 0 0 0

I G B T 2 1 1 0 0 0

I G B T 3 1 1 1 0 0

IGBT STATE I I I G G G B B B T T T 4 11 21 1 0 0 1 1 0 1 1 1 1 1 1 0 11 1

I G B T 31 0 0 0 1 1

I G B T 41 0 0 0 0 1

Fig. 6. Fundamentatal frequency waveform.

C. Capacitor voltages in the five level inverter Refer Fig. 5 all the capacitors are assumed to be equal and initially charged to a voltage of +E. If a single dc voltage of 4E is supplied to the inverter, then at full positive or negative output voltage the capacitor currents will be zero. However at an intermediate output voltage, the output is clamped to the point +E and the current iL2=iA, the output current. Similarly, at zero voltage, iL3=iA and at -E, iL4A=iA. If we define these three states as S2, S3 and S4 respectively, where S2 is 1 only during the time that the inverter output is clamped to +E and is 0 at all other times, then the three currents can be defined as: iLn=Sn*A where n=1,2,3,4…..n, In order to maintain a constant dc link voltage, the current iL2 must divide in the ratio 3:l with iC1=0.75*iL2 and iC2=iC3=iC4"=0.25*iL2. The capacitor currents for the other states can be calculated in a similar fashion to yield the following equations for the capacitor currents: iC1= ( 0.75*S2 + 0.5*S3 + 0.25*S4 )*iA iC2 =( -0.25*S2+ 0.5*S3 + 0.25*S4 )*iA iC3 = (-0.25*S2 - 0.5*S3 + 0.25*S4 )*Ia iC4 =(-0.25*S2 - 0.5*S3 - 0.7*S4 )*iA (1) iC1=0.75*iL2 and iC2=iC3=iC4=0.25*iL2. H(n)=4/x*1/n(cosnα1+cosnα2)……… (2) Where n=1, 3, 5, 7, 9, 11

All odd non-triple harmonics where considered. A low distortion factor implies low losses due to harmonic voltages and currents and a low torque ripple. Both fundamental frequency switching of the IGBTS with variable dc link voltages, and PWM techniques with fixed dc link voltages were studied. C. Fundamental Frequency Switching Fundamental frequency switching requires each device to be switched on and off just once per cycle of the fundamental frequency output and produces the staircase type waveform of Fig.6 There are a number of degrees of freedom that can be employed in arriving fundamental frequency switching at an optimum type of output voltage waveform. If we switch to the intermediate voltage, +E at αl, and to the full voltage, +2E at α2, the Fourier coefficients of the output voltage are calculated as the simple sum of the coefficients of the two rectangular waves. From equation (2) we can derive the various control options for the output voltage; E can remain constant and the angles α1 and α2 varied to control the fundamental voltage and minimize the distortion factor.

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International Journal of Emerging Technology and Advanced Engineering Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 3, Issue 11, November 2013) Section IV

A. Control Scheme of IPFC The above two figures shows the design of control scheme for two voltage source converters. The IPFC is designed to maintain the impedance characteristic of the two transmission lines. The inter line power flow controller mainly consists two voltage source converters 1. Main converter (master) and second one is slave converter. Depending upon the power flow (if power transmits from line one to line two the converter1 will work as converter and converter two work as inverter and vice versa.

A. Design of Inter Line Power Flow Controller in matlab/simulink

Xinj PID Vinja

abc alpha,beta,0

abc

R

PID Controller

Vinj_alpha abc1

X

abc -alpha,beta2 Z

PI Discrete PI Controller4

Rinj

alpha beta

Iabc_B1

alpha

alpha1

alpha

d

beta1

beta

q

o

o1

dq0 abc

beta

abc o

abc2

PHASE SHIFTER

Iline

Reference wave Generator RWG1

Design of control scheme for converter1 The converter 1 mainly consists the following parts Reference - compensator, alpha- bheta to d-q converter and PWM generator. The slave converter mainly consists of following parts. DC voltage controller, balancing controller, reactance controller, PWM generator. The major difference between the two control schemes are the dc voltage controller and (b) the balancing controller. Since the dc-link voltage is controlled by the slave system, the dc voltage controller and balancing the controller is no longer needed. However, here two control loops are required to regulate the d- and q-components in the synchronous reference frame in order to regulate both the reactance and resistance of the Line 1.

dq0_to_abc Transformation1

sin_cos

1

In1

z Unit Delay Subsystem

ALPHA TO DQ0

Freq In1 Out1

Vabc_B1

abc

Valpha

RWG1

Valpha

Vabc_B1

Vabc(pu) wt

In2 Sin_Cos

Lead lag 90

Discrete 3-phase PLL1

Fig.7 Control scheme for VSC2

ii Pulse Generation For VSC 1 The Fig.9 shows the triggering pulse generation circuit for voltage source converter 1. It generates totally 24 pulses are generated these pulses are applied to the 24 IGBTS which are connected in three legs of VSC1 iii Pulse Generation For VSC2 The Fig.10 shows the triggering pulse generation circuit for voltage source converter 2. It generates totally 24 pulses these pulses are applied to the IGBTS which are connected in three legs of VSC 2. B. Simulation Results The simulated power system (Fig.9) modeled with Simulink/Mat lab, consists of two identical transmission systems. The controller in vsc1 is designed to compensate 0.4Pu transmission line reactance and 0.2 Pu resistance of transmission line. In vsc2 designed to control the DC voltage and kept it at constant position and compensate the reactance of 0.4Pu.

Fig.8 Control scheme for VSC2

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International Journal of Emerging Technology and Advanced Engineering Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 3, Issue 11, November 2013) The system was designed in Mat Lab/Simulink with variable inputs at different time intervals. The output results are tabulated ate different time intervals (from 0s2.5s)

Fig.9 triggering pulse generator for vsc1 & Fig10. Triggering pulse generator for vsc1

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International Journal of Emerging Technology and Advanced Engineering Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 3, Issue 11, November 2013) B2

B3

B1 1 Rg=0.001pu

0.05pu

Xg=0.005pu 2

0.25pu

Ls

1

2

25MVA 6.6/36KV

Lp2

Lp1

230/33KV

v ariable power source1 230KV Iine1

300MVA

Generatin Station 1

+/-20MVA

LOAD1

MASTER VSC

LOAD2

Vdc LOAD1

P-1.5PU

LOAD2

P=0.4PU

Q=1.0PU Q=0.25PU

+/-20MVA SLAVE VSC

Lp1

Lp2

B4

25MVA

Rg=0.001pu

B5

B6

6.6/36KV Ls

1

2

1

Xg=0.005pu

2 0.25pu

0.05pu

v ariable power source2 230KV Generatin Station 2

230/33KV 300MVA

Line2

LOAD1

LOAD2

Fig 11. Single line diagram for inter line power flow controller

C. Inter Line Power Flow Controller With Five Level Inverter In Matlab

Discrete, Ts = 5e-005 s.

A

A

A

aA

aA

B

B

B

bB

bB

C

C

C

cC

cC

B12

B1

Subsystem9

powergui

A a2 b2 c2 B a3 b3 C c3

aA bB cC

B11

A

a

aA

bB

B

b

bB

cC

C

c

cC

cC

B3

B7

Cc

B2

Conn3 Conn6

Bb

230kvV / 230kvV2 T /F 2

aA bB

Subsystem2

A B C

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b

Conn2 Conn5

Aa Conn1 Conn4 a

aA

-

+

Subsystem3

Subsystem 1 out puts l oad1

+ v

-

Subsystem6

Vdc Goto

-

+

Subsystem2 i /p and o/p for l i ne 1

c

b

a

Subsystem4

A

aA

aA

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B

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bB

bB

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C

C

cC

cC

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Subsystem11

230kV 100 MVA 1

B13

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Conn3 Conn6

aA

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a

aA

aA

bB

B

b

bB

bB

cC

C

c

cC

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B6

B10

aA bB cC

Three-Phase Transformer (Three Windings)1

B9

B5

230kV / 230kvV2 T /F 1

A

C

a2 b2 c2 a3 b3 c3

C

A

B

B

A

cC

Conn2 Conn5

bB

aA

Subsystem5

Conn1 Conn4

Subsystem3 i /p and o/p for l i ne 2

l oad3

Fig.12.Interline power flow controller in matlab/simulink

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International Journal of Emerging Technology and Advanced Engineering Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 3, Issue 11, November 2013) D. Simulation waveforms in MATLAB/SIMULINK

Fig13.d.Injected active and reactive powers for line 2 Fig13.a Injected Voltages for line1 and 2

Fig13.e.Voltage across capacitor (vdc)

Fig13.b.Injected currents for line and 2

Fig13.c.Injected active and reactive powers for line1

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International Journal of Emerging Technology and Advanced Engineering Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 3, Issue 11, November 2013) Table 2. sending and receiving end powers

S.NO Real and reactive power analysis for line 1 and 2(sending end and receiving end)

1

LINE 1 REAL POWER SENDING END (W)

0-0.1s 1.1478 X108

0.1-0.2s 1.3773 X108

2

LINE 1 REACTIVE POWER SENDING END ((-Ve) VAR)

0.765 X108

0.9155 X108

3

LINE 1 REAL POWER RECEIVING END(W)

1.4348 X108

1.4348 X108

1.81732 1.81732 X108 1.4348 X108 1.4348 X108 1.4348 X108 1.4348 X108 X108

4

LINE 1 REACTIVE POWER RECEIVING END ((-Ve) VAR) LINE 2 REAL POWER SENDINDG END(W)

0.9565 X108

0.9565 X108

1.1955 X108

1.1955 X108 0.9565 X108 0.9565 X108 0.9565 X108 0.9565 X108

1.1478 X108

1.1478 X108

1.1478 X108

1.721 X108

6

LINE 2 REACTIVE POWER SENDING END((-Ve) VAR)

0.765 X108

0.765 X108

7

LINE 2 REAL POWER RECEIVING END(W)

1.4348 X108

1.4348 X108

5

8 9

0.2-0.3s 1.1478 X108

0.3-0.4s 0.4-0.5s 0.5-0.6s 0.6-0.8s 0.8-1.0s 1.1478 X108 1.1478 X108 1.1478 X108 1.81732 X108 1.1478 X108

0.765 X108 0.765 X108

0.765 X108

1.1953 X108

0.765 X108

1.1478 X108 1.1478 X108 1.81732 X108 1.1478 X108

0.765 X108 1.1478 X108

0.765 X108

0.765 X108

1.434 X108

1.4348 X108

1.434 X108 1.81732 X108 1.4348 X108

1.4348 X108

REAL LOAD AT RECEIVING 190 MW 190 MW 150 MW 150 MW END LINE 1,2 REACTIVE LOAD AT 125 125 125MVAR 125MVAR RECEIVING END LINE 1,2 MVAR MVAR

V. CONCLUSION

[2]

The design of an IPFC with five level inverter has presented in this paper. Two different control circuits were designed for generating triggering pulses for five level inverters. The IPFC system with two 5-level in MATLAB/SIMULINK was designed and results validated. The simulation waveforms presented in the paper. The real and reactive powers at sending end and receiving end at different levels are calculated and tabulated

[3]

[4]

REFERENCES [1]

0.765 X108

[5]

L.Cera ZanettaJr., R.L.Vasque-Arnez,”Steady- State multi-line power flow control through the generalized IPFC”, IEEE/PES

180

1.1956 X108

0.765 X108

190 MW

190 MW

190 MW

190 MW

125 MVAR

125 MVAR

125 MVAR

125 MVAR

M.Venkateswara Reddy,,Dr. Bishnu Prasad Muni,Dr. A.V.R.S. Sarma “design of controller for an interline power flow controller” PEIE 2011, CCIS 148, pp. 56–61, 2011. © Springer-Verlag Berlin Heidelberg 2011 N. Hingorani and L. Gyugyi, “Understanding FACTS: Concepts andTechnology of Flexible AC Transmission Systems,” New York, NY: IEEEPress, 2000..Brown, L. D., Hua, H., and Gao, C. 2003. A widget framework for augmented interaction in SCAPE. S.K. Lim, J. H. Kim, and K. Nam, “A DC-link voltage balancing algorithm for 3-level converter using the zero sequence current,” IEEE Power Electronics Specialists Conference, Vol. 2, pp. 1083 1088, June-July 1999 S. J. Lee, H. Kim, S. Sul, and F. Blaabjerg, “A novel control algorithm for static series compensators by use of PQR instantaneous power theory,” IEEE Trans. On Power Delivery, Vol. 19, No. 3, pp. 814-827, May 2004. Tavel, P. 2007 Modeling and Simulation Design. AK Peters Ltd.