using high-resolution Electron-Beam Lithography (EBL) over glass substrates ..... cured for 35 minutes, then was left in a freezer for 5 to 10 minutes to cool down.
statement of purpose. The general policy is to admit only those applicants judged
to have the highest potential for success as graduate students consistent with ...
Mar 14, 2011 ... Richard C. Dorf & James A. Svoboda, Introduction to electric circuits, 7th .....
manual) d. measured results, e. answers to Evaluation & Review ...
17 Feb 2011 ... them with microwaves, maybe a dozen times a second …” Pham Trinli,
thousands of years from now. Vernor Vinge,. “A Deepness in the Sky,” ...
are interwoven by mechanical, electrical and computer design engineers to create the. AUV. It is easy to see ..... forms. CREO lacks internal tutorials but has a link to an online tutorial website. Some ..... AI EDAM 2, 33â52 (1988). 16. Ball, L.J.
Jul 30, 2004 ... Home Page. Title Page. ◁◁. ▷▷. ◁. ▷. Page 1 of 100. Go Back. Full Screen.
Close. Quit. •First •Prev •Next •Last •Go Back •Full Screen ...
Feb 27, 2007 ... Instructor: Dr. Liang Cheng. CSE302: Compiler Design. 02/27/07. Recursive-
Descent Parsing. ▫ void A() {. Choose an A-production, A → X. 1.
Optimization problems that arise in engineering design are often characterized
by several features that hinder the use of standard nonlinear optimization.
Boolean Algebra, Digital Logic and Electrical Properties of. Logic Gates ...
Textbook: – “Fundamentals of Digital Logic with VHDL Design, third edition”, by.
Nov 4, 2007 - good effect for the design of groupware in an industry setting, (2) a new design method ..... investigations. A recruitment email was sent to all LEO-R ..... ways: (1) 700 posters marketing the CodeCOOP were placed in buildings ...
Synthesis of an RTL design using Synopsys Design Compiler (DC). • Using
Tetramax to ... Insert scan chain into a design using Synopsys DFT compiler.
Information Technology and Teacher Education (SITE) noted, .... Contemporary Issues in Technology and Teacher Education, 10(2). 171. SITE) and ...
efficient enough to make water reach steam point and air reach its hottest phase. ... Concentrating Solar Power (CSP) systems use lenses or mirrors and tracking ...
Feb 10, 2015 - A finger prosthesis is fabricated by pouring silicone resin into the mold. A finger prosthe- .... Journal of Craniofacial Surgery, 20, 1169-1172.
The George W. Woodruff School of Mechanical Engineering. Georgia ... material from a solid object; additive fabrication processes include Stereolithography,. Selective ..... automotive industries, medical engineering, and so on. The strong, stiff ...
Virtual Private Networks: Making the Right Connection. Dennis Fowler .... 2.6 Ethernet (802.3). 111. 2.6.1 Physical Prop
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Topics. ▫ Design rules and fabrication. ▫ SCMOS scalable design rules. ▫ Stick
diagrams. Modern VLSI Design: Chap2. 2 of 31. Sharif University of Technology.
Design Rules & Fabrication Somayyeh Koohi Department of Computer Engineering Sharif University of Technology Adapted with modifications from lecture notes prepared by author
Why we need design rules Masks are tooling for manufacturing Manufacturing processes have inherent limitations in accuracy Design i rules l specify if geometry off masks k which hi h will ill provide reasonable yields Spacing Minimum-width rule Avoid small negative feature
Design rules are determined by experience Sharif University of Technology
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Manufacturing problems Photoresist shrinkage tearing Variations in material mask Variations in temperature V i ti Variations iin oxide id thi thickness k Variation in Vt
Impurities Variations between lots Lot consists of multiple wafer
Variations across a wafer Sharif University of Technology
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Transistor problems Variations in threshold voltage: oxide thickness ion implantation poly variations
Changes in source/drain diffusion overlap Variation in effective channel length
Variations in substrate Sharif University of Technology
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Wiring problems Diffusion: Changes in doping
variations in resistance, capacitance
Poly, metal: Variations in height, width capacitance
variations in resistance,
Shorts and opens:
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Oxide problems Variations in height Lack of planarity step coverage metal 2 metal 2
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metal 1
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Via problems Via may not be cut all the way through Undersize via has too much resistance Via may be too large and create short
MOSIS SCMOS design rules 1. Designed to scale across a wide range of technologies 2 Designed to support multiple vendors 2. 3. Designed for educational use Therefore, fairly conservative
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and design rules 2 is the size of a minimum feature Specifying particularizes the scalable rules Parasitics are generally not specified in units µm-based design vs. -based design
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Scaling Scale all chip parameters by x: W’ -> W/x, L’ -> L/x, V’ -> V/x, etc.
Transistor current shrinks: I’/I = 1/x ((EQ. 2-28))
Capacitance shrinks Resistance unchanged So chip speeds up (C’V’/I’)/(CV/I) = 1/x
Shrinking makes chip faster and smaller
More later… Sharif University of Technology
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Wires 6
metal 3
3
metal 2
3
metal 1
3
pdiff/ndiff
2
poly
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Transistors 2 3
2 3 1
5
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Vias 4
4
Types of via:
1
metal1/diff metal1/poly metal1/metal2
2
No direct connection between metal2/metal3 and poly Connection through metal1 Sharif University of Technology
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Metal 3 via Type: metal3/metal2 Rules: cut: 3 x 3 overlap by metal2: 1 minimum spacing: 3 minimum spacing to via1: 2
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5 1 3
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Tub tie Tub to power supply 4 1
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Spacings Diffusion/diffusion: 3 Poly/poly: 2 Poly/diffusion: y 1 Via/via: 2 Metal1/metal1: 3 Metal2/metal2: 4 Metal3/metal3: 4 Diffusion/tub wall: 5 Sharif University of Technology
Stick diagrams Is a cartoon of a layout Shows All components/vias (except possibly tub ties) Relative placement
Not show Exact placement Transistor sizes Wire lengths Wire widths Tub boundaries Sharif University of Technology
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Stick diagrams (cont’d) Just horizontal & vertical lines Crossing materials: Similar: Connected Dissimilar: Unconnected Unless connection is established through a via
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Stick diagrams (cont’d) m2
m1
poly
ndiff
pdiff
Short
O
O
O
O
m2
O
Short
O
O
O
m1
O
O
Short
NMOS
PMOS
poly
O
O
O
Short
illegal
ndiff
O
O
O
O
Short
pdiff
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Stick layers metal 3 metal 2 metal 1 poly ndiff pdiff
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Dynamic latch stick diagram VDD
in
VSS
out
phi’
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phi Modern VLSI Design: Chap2
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Sticks design of multiplexer Start with NAND gate: +
out b
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a
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NAND sticks VDD a out
b
VSS Sharif University of Technology
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One-bit mux sticks VDD ai bi
a outt
N1 (NAND) b
a outt
select
select’
a
N1 (NAND) b
out
N1 (NAND) b
VSS Sharif University of Technology
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3-bit mux sticks select’
a2 b2
a1 b1 a0 b0
ai bi
ai bi ai bi
select’
select select
m2(one-bit-mux)
select’
select
m2(one-bit-mux) select’
Sharif University of Technology
select
m2(one-bit-mux)
Modern VLSI Design: Chap2
VDD oi VSS
o2
VDD oi VSS
o1
VDD oi VSS
o0
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Layout design and analysis tools Layout editors are interactive tools Magic L-edit
Design rule checkers are generally batch identify DRC errors on the layout
Circuit extractors extract the netlist from the layout Connectivity verification systems (CVS) compare extracted and original netlists Sharif University of Technology
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Automatic layout Cell generators (macrocell generators) create optimized layouts for ALUs, etc. Standard cell/sea cell/sea-of-gates of gates layout creates layout from pre-designed cells + custom routing Sea-of-gates allows routing over the cell
