Design rules for field plate edge termination in SiC ... - IEEE Xplore

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 12, DECEMBER 2001

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Design Rules for Field Plate Edge Termination in SiC Schottky Diodes Marc C. Tarplee, Member, IEEE, Vipin P. Madangarli, Member, IEEE, Quinchun Zhang, and Tangali S. Sudarshan, Senior Member, IEEE

Abstract—Practical design of silicon carbide (SiC) Schottky diodes incorporating a field plate necessitates an understanding of how the addition of the field plate affects the performance parameters and the relationship between the diode structure and diode performance. In this paper, design rules are presented for SiC Schottky diodes that incorporate field plate edge termination. The use of an appropriate field plate edge termination can improve the reverse breakdown voltage of a SiC Schottky diode by a factor of two. Reverse breakdown voltage values can be obtained that are up to 88% of the theoretical maximums. Index Terms—Avalanche breakdown, edge termination, field plate, Schottky diode.

I. INTRODUCTION

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HE reverse blocking capability of any diode is limited primarily by the onset of avalanche breakdown resulting from impact ionization. Impact ionization, in turn, is strongly dependent on the peak electric field within the device. Expressions have been derived that relate the reverse breakdown voltage to the wafer carrier concentration. For silicon carbide (SiC), an expression can be obtained by substituting the impact ionization parameters of SiC into an equation proposed by Baliga [1], as indicated below: (1) is the theoretical breakdown voltage and is the where wafer doping concentration. In real devices, the breakdown voltage is always less than that predicted by (1), since the material is not perfect (due to defects) and the edge termination is not optimized. A measure of success of any edge termination would be the degree to which it causes diode behavior to approach the limit set by (1). In real diodes, the highest electric field under reverse bias always occurs inside the depletion region, near the electrode corners due to electric field enhancement. These high fields can be

Manuscript received December 21, 2000; revised June 14, 2001. This work was supported by the ONR under Grant N00014-99-1-1099. The review of this paper was arranged by Editor P. Bhattacharya. M. C. Tarplee is with the Department of Electrical Engineering, University of South Carolina, Columbia, SC 29208 USA and also with York Technical College, Rock Hill, SC 29730 USA (e-mail: [email protected]) V. P. Madangarli is with the Department of Electrical Engineering, University of South Carolina, Columbia, SC 29208 USA and also with TestChip Technologies, Inc., Plano, TX 75074 USA. Q. Zhang and T. S. Sudarshanis are with the Department of Electrical Engineering, University of South Carolina, Columbia, SC 29208 USA. Publisher Item Identifier S 0018-9383(01)08358-7.

relieved using edge terminations surrounding the electrode periphery [1]. Edge termination may be provided in a variety of ways: guard rings [2], field plates [1], [3], [4], use of a mesa structure [5], [6] , a high resistivity layer [7]–[10] or some combination of techniques. From the viewpoints of using less real estate and a less complicated fabrication process, field plate termination is widely used in power device design. In this paper, we will focus on the use of field plates to provide improved reverse breakdown performance. Schottky diodes having edge terminations have been studied widely [1]–[10]. Simulation and experimental results have appeared in the literature for several structures. Schoen et al. [9] have looked carefully at n-type 4H–SiC devices fabricated with a resistive edge termination and have developed some design rules. While field plate edge termination is also known to reduce field crowding and enhancement, to the best of our knowledge, there has been no detailed study on this subject leading to device design rules. In this paper, a simple set of design rules will be developed for field plate edge termination of high voltage Schottky diodes. Simulations have been performed using the ATLAS device modeling software of a wide variety of field plate designs on vertical Schottky diodes fabricated using SiC since SiC Schottky diodes are poised to replace conventional Si based high power diodes used at high temperatures. Experimental studies were undertaken to calibrate and confirm the ATLAS model of field plate edge termination. II. SIMULATION RESULTS The diode structures in Fig. 1 consist of a p-type Al doped cm grown over a 300 SiC epitaxial layer with doping of m p -type SiC substrate with a doping of cm . The field plate consists of a metal-overlap over an oxide layer. To make the simulations more realistic, an interface charge density cm was added to the oxide/SiC interface. P-type of SiC devices were simulated because the authors were already examining p-SiC Schottky diodes to determine if they could be used for high power applications. The epitaxial layer thickness , oxide thickness , and the overlap , were varied to ascertain their effects on the breakdown voltage. is the radius of the metal contact. In particular, the epilayer thickness was varied to ensure that there is no punch-through up to the breakdown voltage during the simulations. The simulation results show that the maximum electric field in the epitaxial layer of both structures occurs directly under the corner of the Schottky contact. The electric field directly under the center of the Schottky contact is smaller than the value under

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Fig. 1. Schematic of simulated Schottky diode structures: (a) unterminated and (b) with field plate edge termination.

the corner and is very close to the value computed from the “parallel plate” approximation that appears in many texts [1], [11]. The relationship between the doping concentration and the peripheral and central electric fields that occur directly under the Schottky contact of unterminated and terminated diodes is m. The applied reverse bias illustrated in Fig. 2 for is in all cases was 400 V. The field enhancement factor defined as the ratio of the maximum field under the cathode corner to the field under the center of the contact at the same depth. The field enhancement factor for unterminated Schottky diodes varies from approximately two for highly doped devices cm to approximately 4 for diodes with a doping cm . For diodes with edge termination, the field level of enhancement factor varies from approximately 1.3 to 1.6 over the same range of doping levels. It is clear from Fig. 2 that the field plate does provide field relief at the Schottky contact periphery. The degree of relief for highly increases from approximately 35% doped devices to approximately 60% for lightly doped devices. This reduction may not be significant in absolute terms but it is sufficient to prevent avalanche breakdown. Besides reduction in the electric field magnitude, the field plate also shifts the location of the high field region away from the Schottky contact periphery. As shown in Fig. 3, the location of the high field region moves into the oxide layer in the presence of a field plate. m , it will comIf the oxide layer is sufficiently thick pletely contain the high field region that exists between the field plate and the semiconductor. It will also prevent the formation of a second region of high field stress in the semiconductor under the overlap corner. If the oxide layer is thin, large electric fields can occur in the oxide even at relatively low voltages. For example, simulation of a Schottky diode with a 100 thick oxide layer below the field plate indicates that at a potential of only 550 V the electric field in the oxide is 8 MV/cm. This field is quite large considering

Fig. 2. (a) Comparison of electric field strengths inside Schottky diodes (unterminated and terminated) and (b) field enhancement factor, as a function of epilayer doping concentration at a depth of 0:2 m under the cathode.

the maximum ideal breakdown strength of an oxide layer is only 8–10 MV/cm. Because the field plate’s corner is quite close to the semiconductor, it strongly influences the electric field, creating a second high field region inside the semiconductor under the corner. However, this region is fully depleted of carriers so impact ionization does not occur in this region. In this case, the device breakdown voltage is determined by oxide failure. For extremely thick oxide layers, the field plate is so far away from the semiconductor that it does not have much influence on the electric field distribution. In this case, there is also not much improvement in breakdown voltage. Hence, the optimum thickness of the field plate oxide is that which 1) will be sufficiently thick that the peak electric field inside the oxide will not exceed the breakdown strength of the oxide; 2) will be sufficiently thin that the field plate can influence the electric field distribution inside the semiconductor and provide sufficient field relief at the corner. In fact, from numerous simulation results on diodes with different epi-layer doping concentrations, an empirical relationship (as shown in Fig. 4) was obtained between the required

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Fig. 3. Effect of oxide thickness on electric field distribution.

Fig. 4. Relationship between breakdown voltage and oxide thickness; Na = 10 cm , t = 10 m.

thickness of the oxide layer and the optimized epi-layer thickness (which is determined by the depletion width at breakdown). Oxide breakdown field values were taken from [12]. Zhang et cm al. [12] observed that an interface charge density of could reduce the breakdown voltage of MOS capacitors. Simulations of Schottky diodes with field plates show a similar reduction in reverse breakdown voltage for values of oxide interface cm . charge density greater than Simulations of unterminated Schottky indicate that the field enhancement factor at the cathode corner depends on the epitaxial layer doping concentration. From this, we presume that the usefulness of a field plate will depend on the carrier concentration in the semiconductor. Fig. 5 shows the breakdown

Fig. 5. Variation of breakdown voltage with doping concentration for diodes with and without edge termination (t = 0:7 m).

voltages of unterminated and terminated SiC Schottky diodes obtained using ATLAS simulation for various doping concentrations. The field plate increases the reverse breakdown voltage to at least 65% of the theoretical maximum predicted by (1). For highly doped devices, the diode with field plate has a breakdown voltage that is over 80% of the theoretical limit.

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Fig. 6. Effect of metal overlap on breakdown voltage and field enhancement factor (Na = 10 cm ; no punch-through).

However, it must be noted that a field plate with 7000 thick oxide does not provide much absolute improvement when the cm (Fig. 5). concentration is greater than around For highly doped materials, the electric fields are so large everywhere because of the narrow depletion layer under the cathode that a field plate cannot provide sufficient relief to improve the breakdown voltage of the terminated device. It may be possible to improve the performance of the field plate by reducing the oxide layer thickness to increase the plate’s effect on the epitaxial layer. However, this leads to very large electric fields inside the oxide layer and an oxide breakdown could occur. Field plate performance is also affected by the field plate . Fig. 6 shows how the breakdown voltage and field overlap enhancement factor varies as a function of overlap. It is clear that increasing the field plate overlap up to a certain limit will raise the breakdown voltage. Beyond that limit, the breakdown voltage becomes almost independent of its overlap. Fig. 6 also shows that for a particular doping concentration, the field enhancement factor decreases progressively from the value to with increasing for the unterminated diode is approximately equal to the defield plate overlap until m for Na cm pletion width at breakdown ( doping concentration). Further increases in the overlap do not result in any decrease in the field enhancement factor. This is reasonable considering that the lateral spread of the depletion region is comparable to the depth of the depletion region in the vertical direction. The electric field in the semiconductor is significant only in the depleted regions, so field relief is necessary only in these areas. Extending the field plate into undepleted regions where the electric field is small does not result in any significant decrease in field enhancement or increase in breakdown voltage. Hence, for a particular carrier concentration and avalanche breakdown conditions, there is a maximum breakdown voltage that can be achieved with the cathode/field plate combination shown in Fig. 1. The optimum field plate overlap for achieving the maximum breakdown voltage for a given doping concentration is roughly equivalent to the optimized epilayer thickness (which is determined by the depletion overlap at breakdown).

Fig. 7. Flow-chart for designing field plate edge termination for a nonpunch through SiC Schottky diode.

III. DISCUSSION The ATLAS software package has three models for impact ionization: Grant’s model; Selberherr’s model; Crowell-Sze model. All three models depend in some way on the reduced field variable (2) where is the impact ionization coefficient and is the electric field. Selberherr model was chosen for simulations that appear in this paper to make the simulations consistent with equations presented earlier. Using this impact ionization model, a series of simulations was carried out on devices with and without field plates. The results of these simulations showed that the field relief provided by the edge termination was limited to about 30–60%, it was not obvious how the breakdown voltage could be increased by approximately a factor of two. However, several discoveries were made about impact ionization processes in SiC. First, the onset of impact ionization was extremely dependent on free carrier concentration. There were areas directly under the field plate inside the epi-layer where the electric field approached the breakdown field necessary for avalanche, but no carrier generation took place. These areas were completely devoid of carriers because of the formation of a depletion region below the MOS structure created by the metal overlap under reverse bias. Second, impact ionization was extremely dependent on the magnitude of the electric field inside the epitaxial layer. At the breakdown field strength, approximately 2.5 MV/cm, the current multiplication factor predicted by a simple analytic one-dimensional impact ionization model was more than 1000. If the

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Fig. 8. Comparison of simulated and experimentally observed reverse breakdown characteristics for unterminated and field plate edge terminated p-type 6H-SiC Schottky diodes.

Fig. 9. J –V characteristics of Schottky diodes with different oxide thickness, under reverse bias. Note: these J –V curves were obtained from pulse measurements on a different sample other than the one shown in Fig. 8.

field value was reduced 25%, to 1.88 MV/cm, the current multiplication factor plummeted to 1.1. Only a small field relief was required because the impact ionization process was so sensitive to the local electric field. This also helped explain the diminishing effect of field plates on heavily doped devices. In such devices, the depletion regions are very narrow, resulting in extremely high electric fields. The field plate cannot provide sufficient relief to improve the breakdown performance. In principle, the field plate could be moved very close to the semiconductor to increase its influence on the electric field. However, when the oxide spacer is made thinner to reduce the separation between the field plate and the semiconductor, the electric field within the oxide becomes very large. At moderate reverse voltages, the field within the oxide will be sufficient to produce oxide breakdown.

The simulation work presented above for a nonpunch through Schottky diode can be summarized in a series of simple design rules as outlined in the flow-chart shown in Fig. 7. These correlate the required doping concentration, drift region thickness and field plate parameters to the desired breakdown voltage. IV. COMPARISON

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SIMULATION RESULTS

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EXPERIMENTAL

The validity of the design rules for field plate edge termination in SiC Schottky diodes were verified by fabricating p-type 6H–SiC Schottky diodes as described in [12]. In Fig. 8, the simulated and experimental results are compared for both unterminated and terminated Schottky diodes. It is noteworthy that though the simulations were calibrated using the unterminated

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diode, the simulated breakdown voltage V (predicted value) for the diode with edge termination compares reaV. sonably well with the measured (dc) value of In addition, the prediction from simulated results that the breakdown voltage of Schottky diodes with a very thin oxide layer field plate will be lower than that of the unterminated Schottky diode (Fig. 4) is confirmed by the experimental results shown in Fig. 9. V. CONCLUSIONS A simple set of design rules for field plate edge termination in SiC Schottky diodes has been presented. The rules focus primarily on designing a device with a specific reverse breakdown voltage. The validity of the proposed design rules has been verified by experimental results. Both experimental and simulation data indicate that the reverse breakdown voltage of a SiC Schottky diode with a field plate over a 7000 thick oxide edge termination was approximately two times higher than a Schottky diode without any edge termination. ACKNOWLEDGMENT The authors are grateful for the support and encouragement of Dr. C. Wood and Dr. M. Yoder of ONR. REFERENCES [1] J. Baliga, Power Semiconductor Devices. Boston, MA: PWS, 1996. [2] T. N. Oder, C. C. Tin, J. R. Williams, V. Madangarli, and T. S. Sudarshan, “The response of high voltage 4H–SiC p–n junction diodes to different edge termination techniques,” in Proc. Materials Research Soc. Symp., vol. 512, 1998, p. 101. [3] G. Brezeanu, J. Fernandez, J. Millan, M. Badila, and G. Dilimot, “Medici simulation of 6H–SiC oxide ramp profile Schottky structure,” Mater. Sci. Forum, vol. 264–268, p. 941, 1998. [4] V. Saxena, J. N. Su, and A. J. Steckl, “High voltage Ni-and Pt-SiC Schottky diodes using metal field plate edge termination,” IEEE Trans. Electron Devices, vol. 46, p. 456, Mar. 1999. [5] P. G. Neudeck, D. J. Larkin, A. Powell, and L. G. Matus, “2000 V 6H–SiC PN junction diodes grown by chemical vapor deposition,” Appl. Phys. Lett., vol. 64, no. 11, p. 1386, 1994. [6] S. Ortolland, “Study of different edge termination used for 6H–SiC power diodes,” J. Phys. III France, vol. 7, p. 809, 1997. [7] C. E. Weitzel, J. W. Palmour, C. H. Carter, K. Moore, K. J. Nordquist, S. Allen, C. Thero, and M. Bhatnagar, “Silicon carbide high-power devices,” IEEE Trans. Electron Devices, vol. 43, p. 1732, Oct. 1996. [8] D. Alok, B. J. Baliga, and P. K. McLarty, “A simple edge termination for silicon carbide devices with nearly ideal breakdown voltage,” IEEE Electron Device Lett., vol. 15, p. 394, Oct. 1994. [9] K. J. Schoen, J. M. Woodall, J. A. Cooper Jr, and M. R. Melloch, “Design considerations and experimental analysis of high-voltage SiC Schottky barrier rectifiers,” IEEE Trans. Electron Devices, vol. 45, p. 1595, July 1998.

[10] D. Alok and B. J. Baliga, “SiC edge termination using finite area argon Ion implantation,” IEEE Electron Device Lett., vol. 44, p. 1013, June 1997. [11] M. Shur, Physics of Semiconductor Devices. Englewood Cliffs, NJ: Prentice-Hall, 1990. [12] Q. Zhang, S. Soloviev, V. Madangarli, I. Khlebnikov, and T. S. Sudarshan, “High voltage Schottky barrier diodes on p-type SiC using metaloverlap on a thick oxide layer as edge termination,” in Proc. Mater. Res. Soc. Symp., vol. 572, 1999, p. 75.

Marc C. Tarplee (M’96) received the B.Sc. degree in 1981 from the State University of New York at Brockport, the M.Sc. degree in 1987 from Rochester Institute of Technology, Rochester, NY, and the Ph.D. degree in 2001 in electrical engineering from the University of South Carolina, Columbia. He is the Dean of the Engineering Technologies Division, York Technical College, Rock Hill, SC. His research interests include semiconductor device modeling and computational electromagnetics.

Vipin P. Madangarli (S’90–M’91) received the B.Tech. degree in electrical engineering from the University of Kerala, India, in 1988, and the Ph.D. degree in electrical engineering from the University of South Carolina, Columbia, in 1996. His area of specialization is high field characterization of wide band gap semiconductors such as SiC and GaN, specifically SiC MOS capacitors and GaN HFETs. His research interests also include investigations on high field effects in semi-insulating materials, such as surface flashover studies on high resistivity photoconductive Si and aging studies on high voltage ZnO metal oxide surge arrestors (MOSA). Currently, he is a Product Characterization Engineer at TestChip Technologies, Inc., Plano, TX.

Qingchun Zhang received the B.S. and M.S. degrees in electrical engineering from Tsinghua University, Beijing, China, in 1992 and 1997, respectively, and the Ph.D. degree in August 2001 from the Department of Electrical Engineering, University of South Carolina, Columbia. His doctoral research work involved the study of SiC power devices for high power and high temperature applications. He has authored six journal papers, holds eight patents, and disclosures in power semiconductor devices.

Tangali S. Sudarshan (MS’73–M’74–SM’84) received the B.Sc. degree in 1968 from the University of Bangalore, Bangalore, India, and the M.Sc. degree in 1970 from the University of Mysore, Mysore, India. He received the M.A.Sc. degree in 1972 and the Ph.D. degree in 1974 in electrical engineering from the University of Waterloo, Waterloo, ON, Canada. He was with the National Research Council of Canada from 1974 to 1979 as a Research Officer in the Power Engineering Section. He joined the faculty of the University of South Carolina, Columbia, in 1979, where he is currently a Professor of electrical engineering and a Carolina Distinguished Professor. His research interests include silicon carbide crystal growth and material and device processing.