DEVELOPMENT OF A CUSTOMIZED SSC PIXEL DETECTOR ...

SLAC-PUB-5358 LBL29792 October 1990 WE)

DEVELOPMENT OF A CUSTOMIZED SSC PIXEL DETECTOR READOUT FOR VERTEX TRACKING* Ozdal Barkan,EugeneL. Atlas, WayneL. Marking, ShmrtWcrley, GhassanY. Yacoub HughesAircraft Company,Carl&ad, CA 92009 GordonKramer HughesAircmft Company,El Segundo,CA 90245 JohnF. Arens,J . GarrettJemigan SpaceSciencesLaboratory,University of California Bakeley, CA 94720 StephenL. Shapiro StanfordLinear AcceleratorCenter, StanfordUniversity, Stanford,CA 94309 David Nygren, Helmuth Spieler,M ichael Wright Lamnce BerkeleyLaboratory,Berkeley,CA 94720 Abstract We describethe readoutarchitectureand progressto datein the developmentof hybrid PIN diode arraysfor use as vertex detectorsin the SSC environment. The architecturesupportsa self-timedmechanismfor time stampinghit pixels, storing their xy coordinatesand later selectivelyreadingout only thosepixels containinginterestingdata along with their coordinates.The peripherallogic resolvesambiguouspixel ghostlocationsand controlspixel neighborreadoutto achieve high spatial resolution. A test lot containing64 X 32 pixel arrayshasbeenprocessedand is currentlybeing tested. Eachpixel contains23 transistorsand six capacitorsconsumingan areaof 50 p by 150pm and dissipatingabout20 l.tW of power. Introduction Pixel arrays (2-dimensionalarray of small semiconductor detectorelements)provide significant technicaladvantages for useas vertex detectors[ 1.21.Theseincludegoodtrack resolution,small capacitance,high signal-to-noiseratio, increasedradiationresistance13.41.High interactionrates and the increasedquantity of data (lOg datachannelsfor a typical vertex detector [3]) necessitatesparsereadout circuitry within the detectorchips. We havedevelopeda pixel array chip architecturethat supportsa self-activated mechanismfor time stampinghit pixels, storing their xy coordinate-s and later selectivelyreadingout only those pixels containing interestingdata along with their coordinates.Test chips that containa 64 x 32 array of pixels (50 pm x 150pm each)havebeenPM. Requirements/Assumptions Concerning SSC Detectors Our chip architecturewas d&eloped with the goal of being able to handlethe worst caseassumptionsabout SSC interactionxatesand backgroundradiation. Pixels and the peripheryarchitecturecan be simplified if less demanding assumptionsale made. It is assumedthat every 16 ns thereis a beamcrossing.On the averagethereare 1.5 event&earn crossingand only 1 percentof them will be interesting. A I cm2 chip at a radiusof 3 cm from the beamaxis will be hit during 30

different beamcrossingswhile waiting for the Trigger level 1 signal. (A Trigger level 1 signal is externally generated,signalsthe occurrenceof an interestingeventand hasa delayof 1-2 w from the beamcrossing.This delay will be fixed once the calorimeterdesignis completed.) For eachbeamcrossingwhen the anay is hit, up to 25 pixels will be hit or will be a neighborof such a hit pixel. (It is desirableto read neighborsof hit pixels to determinethe centroidof a particle track). It is also assumedthat these 25 pixel locationswill not be hit again until the data is reador discarded. Requirements/specification for the chip include [5,6] quiescentpowerdissipationof 0.1 - 1.0 W/cm2, dynamic rangeof 500 (determinedby 100,000holes maximuminput chargeand 200 electronrms noise),time stampingwith 16 ns time resolution,readoutof the chargestoredand xy addresses in about I ps, radiationhardnessto IO MRad, and testability. Prototype Architecture and Block Diagrams A fvst prototype array for the final SSC vertex detector hasbeendesignedand will be going into fabricationin December1990. Figure 1 showsthe peripheryarchitecture and Figure 2 showsthe pixel architecture. A numberof prototyping stepsare envisionedto reach the final radiation hardversionof the SSC array.

*Work rupportad by the U.S. Department of Energy, contract number DEACM-‘rsSFooO9B(LB~) a+DE~ACO3-76SF00515(SLAC) _

Contributed to the Symposium on Detector Research and Development for tbe Superconducting Super collider, Fort Wortb, Texas, October 15-18, 1990.

CONTROL

LOGIC

SSC PROTOTYPE ARCHITECTURE

Figure 1. Pixel Detector SSC Prototype Architecture. (RAM). The array keeps storing new hit information until the arrival of a Trigger level 1 signal. At that time the chip searchesthe CAM for a hit at the time of interest indicated by the Trigger level 1 signal. If a hit exists, it readsthose hit locations one at a time and sendsthe stored charge information and addressto be processed. Hit data that does not correspondto the time of interest is not read out and pixels are reset to receive future hits.

Figure 2. Simplified Unit Cell (Pixel) Architecture. A brief overview of chip operation is as follows: If the array is hit, the time of the hit is stored in the content addressablememory (CAM), along with the hit pixel locations that are stored in the random accessmemory 2

This architecture resolves ambiguous hit locations (due to multiple pixels hit at one time) and does not require continuous clocking of pixels or periphery logic, eliminating switching noise and power dissipation. All control signals are generatedinternal to the chip using p-programmed control logic. The CAh4 and the RAM do not require encodingand decoding. Dynamic storagewith no refresh circuitry could also be used since, typically, we are no longer interestedin data after a few microseconds. These characteristicsresult in a smaller periphery and an improved fill factor (> 90%). The chip has a test mode of operation for production testing, as well as an inside-SSC test mode to disconnect bad pixels from the logic.

FY91 Plans The unit cell has within it a transimpedanceamplifier, charge storageand analog buffering, and a fast comparator to signal hits to the row and column circuitry.

We plan to process our current prototype design in early 1991. A6 design with AC coupled detectors (to eliminate dark current buildup due to radiation damage induced leakage) will be processedduring the second half of FY9 1. A rad hard SOS version of this seconddesign will also be processedafter verification of the non-rad hard version.

The pixel has both digital and analog parts in close proximity due to the density required. Great care has been taken to minimize the coupling of the digital signals to the sensitive analog portion of the circuit. Separateanalog and digital supply rails are provided in the unit cell to isolate the analog circuitry from any spikes resulting from digital switching. DC bias lines are used at the cell edgesto prevent cell-to-cell crosstalk.

References: [l] S. Shapiro,W. Dunwoodie, J. At-ens,and S. Gaalema, “Silicon PIN Diode Array Hybrids for Charged Particle Detection,” Nucl. Instrum. Methods A275: 580 (1989).

Several capacitor types are used; PSl to Metal 1 and Metal 1 to Metal 2 for low value capacitors (2.5 - 10 fF) and PSlPwell for higher values (50 - 300 fF).

[2] J. G. Jemigan,J.F. Arens, G. Kramer, T. Collins, J. Herring, S.L. Shapiro, and C. Wilbum, “Performance Measurementsof Hybrid PIN Diode Arrays,” Presentedto the 1990 Int. Industrial Symposium on the Supercollider, Miami Beach, FL (1990) SLAC-PUB 5211.

In the near future we expect advancesin both scaling and silicon-on-insulator (SOI) multilevel technologies to allow the unit cell size to shrink to 50 pm X 50 ttrn or smaller with current circuit complexity. We also expect the advances to result in a faster, better performing unit cell.

[3] H. Spieler, “Integrated Microsystems as a Driving Force in Modem Detector Designs,”Proceedings of the International Conference on the Impact of Digital Microelectronics and Microprocessors on Particle Physics, Trieste, Italy, March 28-30, 1988.

Preprototyping Arrays Before committing to full prototype production we have decided to process test chips to verify the pixel functionality and the speed of time stamping and analog readout. We have used an L,K = 1.2 pm single poly, double metal (pitch - 3.5 pm) CMOS process which guarantees 100 MHz operation at room temperature for worst case process conditions. We are also going to relayout and process a single pixel at Hughes Aircraft using a Hughes radiation hard SOS technology to evaluate the radiation hardnessof the design. None of these test chips contains detectors. Instead, electrical voltage inputs to pixels are used for test and verification of operation. The prototype will contain PIN detectors to be built by LBL.

[4] D. R. Nygren, “Silicon Tracking Devices for the SSC.” Proceedingsof the Summer Study on High Energy Physics in the 199Os,pp 754-761, Snowmass,Colorado, June 27 July 15,1988. [53 G. Kramer, et al, Memorandum of Understanding SSCPC-025 “Proposed Plan for Pixel Array Development for the SSC,”(1989) as modified by 0. Barkan, Preliminary Design Review HTC, Carlsbad, CA, May 2,199O. [63 G. Kramer, et al, “The Pixel Detector Development Collaboration,” Summary Report for FYI90 and Proposed Effort for FY’91, Presented to the SSC Laboratory, September1.1990.

Test Data The test arrays have arrived and are under test.

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