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Development of the protocol of the interface of data exchange with the GBTX chip
This content has been downloaded from IOPscience. Please scroll down to see the full text. 2017 J. Phys.: Conf. Ser. 798 012196 (http://iopscience.iop.org/1742-6596/798/1/012196) View the table of contents for this issue, or go to the journal homepage for more Download details: IP Address: 191.101.234.13 This content was downloaded on 21/03/2017 at 02:31 Please note that terms and conditions apply.
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International Conference on Particle Physics and Astrophysics IOP Conf. Series: Journal of Physics: Conf. Series 798 (2017) 012196
IOP Publishing doi:10.1088/1742-6596/798/1/012196
International Conference on Recent Trends in Physics 2016 (ICRTP2016) IOP Publishing Journal of Physics: Conference Series 755 (2016) 011001 doi:10.1088/1742-6596/755/1/011001
Development of the protocol of the interface of data exchange with the GBTX chip O V Shumkin, D D Normanov and P Ya Ivanov National Research Nuclear University MEPhI (Moscow Engineering Physics Institute), Kashirskoe highway 31, Moscow, 115409, Russia E-mail:
[email protected] Abstract. The structure of the interface of data exchange with the GBTX chip for the CBM experiment is considered. The interface generates a data package, consisting of the digital codes of signal amplitude, signal superposition in peak detector, signal arrival time and channel number, wherein the event has occurred, all these codes being generated by the readout blocks of IC. The created data package is coded according to the 8b/10b format for transferring to the GBTX chip. The packages register of controlling data (warnings on error and desynchronization) are generated for a correct exchange (correspondence) under the GBTX protocol. The adjustment of the quantity of channels, generating data packages and being connected to the GBTX chip, is possible. The interface has been designed according to the 180 nm CMOS technology of UMC.
Introduction The paper describes the elaboration of the 32-channel system of processing the asynchronous data from the CBM muon chambers at the FAIR.. The total number of channels exceeds 106, while the minimal inter-event time is 100 ns. For each channel the ASIC should provide the measurements of signal amplitude, its arrival time and channel number, keeping power consumption within 10 mW/channel. An 8-channel prototype of system was elaborated for debugging the functional model. It comprises the blocks, performing the following functions: load of initial data and control commands, picking up the information about input signals as well as the high-speed (320 MHz) serialization of output data. Protocol The structure of the interface of data exchange with the GBTX chip for the CBM experiment is considered. The interface generates a data package, consisting of the digital codes of signal amplitude, superposition signal in peak detector, signal arrival time and channel number, wherein the event has occurred, all these codes being generated by the readout blocks of IC. the interface part is shown in figure 1.
Figure 1. The sent frame
Content from this work may be used under the terms of the Creative Commons Attribution 3.0 licence. Any further distribution of this work must maintain attribution to the author(s) and the title of the work, journal citation and DOI. Published under licence by IOP Publishing Ltd 1
IOP Publishing doi:10.1088/1742-6596/798/1/012196
International Conference on Particle Physics and Astrophysics IOP Conf. Series: Journal of Physics: Conf. Series 798 (2017) 012196
The created data package is coded according to the 8b/10b format for transferring to the GBTX chip. The packages register of controlling data (warnings on error and desynchronization) are generated for a correct exchange (correspondence) under the CBM_MUCH protocol. The adjustment of the quantity of channels, generating data packages and being connected to the GBTX chip, is possible. The interface has been designed according to the 180 nm CMOS technology of UMC.
DATA[28:0]
CRC CALC + reg
14b Frame[31:0]
27b 5b
RO_Ctrl_ActChNum[1:0]
RST[2:0]
K28.5
K28.1
Frame Constructor
Word[39:0]
EOS
Uplink_GBT x5
ADDR[7:0] WEN
DAC1,DAC2 ...
Alert, Bad_Synch W_OR_R[1:0] Control_Reg [2:0] Control_to_Uplink [2:0]
K Mx_2[1:0]
[7:0] OUT_PAYLOAD
SOS
Decoder _8b10b [2:0] To_Control, [2:0] TYPE_ERROR, Flag_Done CRC_de
Frame Handler
MUX_2
FRAME8[39:0]
WDAT[7:0]
I2C
Register Block
Control box
3b
Word[31:0]
8b/10b encoding + delay reg
I2C Slave
Uplink Control
Mx_1[1:0]
MUX_1
Control Sequence_Number [3:0]
RegBlk DataOut[7:0]
FULL[4:0]
TS_Grey_Cnt_En, TS_Grey_Cnt_Wr_En
[14:0] Register_content, Ack [1:0], Status [3:0]
10b 5b
EMPTY
RE_EN
EDREAD
Downlink Control
c
work
FRAME[59:0]
Synch GIVE
Serialaizer_ x5
Synch_Error
Phase-aligner Deserializer
SH_EM_OR_FULL EDLOAD [4:0]
out
D
E-link
E-link
Control_Des[2:0] 40
160
Frequency block
SDA SCL rst_n_I2C DataOut [4:0]
DataIn
320
CLK 160MHz On_Off
TO GBTX
I2C_En Ctrl [2:0]
Reset_ALL
FROM GBTX
Chip ID [2:0]
Figure 2. Interface part. The discussed protocol describes the operation of the protocol of exchange with the GBTX chip for a variety of nuclear physics experimental. The entire protocol can be divided into two parts. That are synchronization and data exchange. Synchronization protocol is shown in figure 3. Downlink
Uplink
SOS
SOS
SOS
SOS
SOS
K28.5 K28.5 K28.5 K28.5 K28.5 K28.5 K28.5 K28.5 sos
sos
SOS
sos
sos
Regular link synchronization procedure K28.1
sos
sos
K28.1
sos
K28.1
K28.1
EOS
EOS
EOS
sos k28.1 k28.1 k28.1 k28.1 k28.1 k28.1 k28.1 k28.1 EOS
EOS
Quick link synchronization procedure Downlink
Uplink
K28.1
K28.1
K28.1
K28.1
EOS
EOS
EOS
EOS
FRAME
FRAME
FRAME
FRAME
K28. K28. K28. K28. K28. K28. K28. K28. K28. K28. K28. K28. K28. FRA FRA FRA EOS EOS EOS EOS EOS EOS EOS EOS 5 5 5 5 5 5 5 5 5 5 5 5 5 ME ME ME
Figure 3. Regular and Quick synchronization.
2
EOS
EOS
EOS
FRAME
EOS
EOS
FRAME
EOS
FRAME
EOS K28.5
FRA ME
FRAME FRA ME
FRA ME
International Conference on Particle Physics and Astrophysics IOP Conf. Series: Journal of Physics: Conf. Series 798 (2017) 012196
IOP Publishing doi:10.1088/1742-6596/798/1/012196
The information exchange mode consists of downlink and uplink. The messages SOS and EOS are not subjected to 8b10b coding in contrast to the following types of messages. SOS – start of synchronization, EOS – end of synchronization. Other types of messages use the 8b10b encoding. The main useful information transmitted via the HIT Frame. It consists of a 5-bit channel number, the superposition signal, an 8-bit ADC, 14-bit timestamp and 3 bits of serving bits. All serving information (such as register values) is transmitted through the Ack frame. S – superposition, CP – config parity, Res – reserve. Table 1. Coded by the 8b10b coder. TYPE K28.5 K28.1 Dummy HIT HIT
ACK
BYTE0 BYTE1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 0 1 1 1 1 0 0 1 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BYTE2 15 14 13 12 11 10 9 8 1 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0
BYTE3 7 6 5 4 1 0 1 1 0 0 1 1
3 2 1 0 1 1 0 0 1 1 0 0
0 0 0 0 0 0 0 0 0 0 0
0 0 0 0
0 0 0 0
5-bit Number of S 8-bit ADC 14-bit time stamp channel 4-bit 2-bit 4-bit status 1 0 Sequence CP 15-bit register content ACK value number 0 1
Res 4-bit CRC
The uplink messages use Dummy HIT, HIT, ACK. These messages are subjected to 8b10b coding. The message K28.5 is sent at a frequency of 122 Hz. The k28.5 frame is used for synchronization control. The downlink data use one type of frame. This frame has an 8-bit payload (expandable) and CRC protection. Table 2. Downlink messages. BYTE0
BYTE1
BYTE2
BYTE3
BYTE4
BYTE5
47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Comma characted
Frame ID Address
&
Chip
K28.5
chip address, Request type sequence , Reserve Payload number
Request type/Reserve
Payload
CRC
CRC
CRC
CRC
5 independent communication lines send data to the output. Possible modes are 5, 2, 1 signal lines. GBTX can handle a maximum of 40 lines, therefore the maximum number of CBM_MUCH chips are 8. There is 1 type of frame, where one can configure its function: the dummy frame, writing the address, writing the data or reading them out. To detect errors, a 16-bit CRC polynomial 0x8005 is used. An 8-bit physical address space covers not only the registers of interface chips, but also the virtual registers triggering special functions (for example, the reset of each part separately, and the like). Since the loading link channel is divided into 8 chips the addressing occurs by using a 4-bit address of the chip being used to turn on and translate commands. All special instructions are executed by accessing the registers.
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International Conference on Particle Physics and Astrophysics IOP Conf. Series: Journal of Physics: Conf. Series 798 (2017) 012196
IOP Publishing doi:10.1088/1742-6596/798/1/012196
Conclusion A 32-channel system for processing asynchronous data from the GEM detectors has been developed. Elements of digital block structures have been developed and tested on the basis of the previous chip prototype. Test signals are applied to the system by built-in ADC emulators. The prototype has a pyramidal structure, consisting of several FIFO blocks and a control one. It was manufactured via Europractice in the UMC CMOS 180 nm process. The designed for lab tests board includes the input/output analog and digital interfaces for data exchange with an FPGA processing board. The tests showed the following characteristics: maximal speed for 5-bit data - 50 MHz, the readout one from the FIFO output - 320 MHz. Power consumption and chip area are 43 mW and 450x450 μm sq correspondingly. As result of testing one may conclude that in a full scaled version it is expedient to use the single-level pyramidal structure of data acquisition based on FIFO. The interface block accomplishes a multilevel synchronisation with the GBTX chip, according to its exchange protocol. Synchronization errors are checked by CRC codes and control commands. The reference frequency is set by an external clock of 160 MHz. The control of the ASIC parameters and output data transmission is carried out at a speed up to 320 MHz. Thus, the results of laboratory tests of the prototype chip as well as development of the backend part have proved the relevance of the presented system design. The next step is expected to be the manufacture and test of the full-scaled 32channel version.
Acknowledgments This work was supported by the Ministry of Education and Science of the Russian Federation in the frames of the Competitiveness Program of National Research Nuclear University MEPhI and grant no.14.A12.31.0002 in accordance with the RF government resolution no. 220.
References [1] [2] [3]
Friman B et al. 2010 The CBM Physics Book (Berlin: Springer, New York: Heidelberg) Johann M 2013 Heuser The Compressed Baryonic Matter Experiment at FAIR Nuclear Physics A 904–905 941 Geronimo G De et al. 2002 Analog Peak Detector and Derandomizer for High-Rate Spectroscopy Nucl. Instrum. Meth. A 484 533–43
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