Development of Voltammetry-based Techniques for ...

ECS Transactions, 35 (4) 757-771 (2011) 10.1149/1.3572318 © The Electrochemical Society

Development of Voltammetry-based Techniques for Characterization of Porous Low-k/Cu Interconnect Integration Reliability Choong-Un Kima), L. S. Chena), N. Michaelb), W. H. Banga), Young-Joon Parkc), E. Todd. Ryand), and S. Kinge) a)

Mat. Sci. & Eng., University of Texas at Arlington, TX 76019; Mech. & Aerospace Eng., University of Texas at Arlington, TX 76019; c) Texas Instruments Inc., 13121 TI Boulevard, MS 366, Dallas Texas 75243 d) GLOBALFOUNDRIES, 255 Fuller Rd, Albany, NY 12203 e) Logic Technology Development, Intel Corporation, Hillsboro, OR 97124 b)

contact email: [email protected]

This paper concerns the new method of detecting the integration failures in porous low-k (PLK)/Cu interconnects using simple voltammetry-based techniques. In essence, the technique takes advantage of the fact that pores in PLK allow permeation of liquid, including electrolyte, into interconnect structures. The infiltration of electrolyte allows the formation of a micro-cell, consisting of two mating Cu interconnect electrodes and the electrolyte in PLK, where simple linear voltammetry can examine various integration reliability issues pertinent to PLK/Cu interconnects. Specifically, the technique is proven to be effective in detection of 1) failure in Ta barrier, 2) cracks in the capping layer, and 3) trapped impurity in pores in PLK. The working principle of the voltammetry technique and demonstration of its effectiveness is introduced in this paper.

Introduction Continuing miniaturization of microelectronic devices makes it necessary for back-endof-line (BEOL) interconnects to incorporate radically different materials and process techniques. Among many planned material and process changes, introduction of porous low-k (PLK) dielectrics has proven to be highly challenging in their integration into Cu interconnects, partly because of newly found reliability failure threats [1-4]. One example is the interconnect failure instigated by a defective barrier which exposes underlying Cu to the dielectric. In a conventional BEOL interconnect, where dense dielectrics are employed, barrier failure and its impact on interconnect reliability is not as serious a concern. Material redundancy both in the barrier and dielectric protects the barrier from defect generation during deposition and later processes. However, a robust barrier does not exist in the case of PLK integrated interconnects; rather, barrier failure is a central reliability concern. This is because the etched surface of PLK dielectric is bound to be irregular, resulting in incomplete coverage by the barrier layer. The problem is further exacerbated by the fact that there exists very little material redundancy in the barrier layer as it has to be just a few nanometers thick. Thermal and mechanical load on the barrier, common during interconnect processing, can easily compromise the integrity of the

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ECS Transactions, 35 (4) 757-771 (2011)

barrier layer, and the resulting barrier layer failure can instigate various physical failures that may slowly develop in the later processes or device operation [5-7]. A striking example of interconnect failure instigated by the barrier failure is the massive outmigration of Cu into PLK, leaving a large void behind in the Cu, exhibited by the dummy metallization in Fig 1. It is found that Cu out-migration occurs via defects in 20nm thick Ta barriers when the interconnect is exposed to oxidation potential. Another serious reliability concern unique to PLK/Cu interconnects stems from the fact that PLK dielectrics are known to have an open pore structure when the porosity exceeds about 25%. With an open pore structure, process gases and liquids can infiltrate the interconnects and may react with components including the barrier. Furthermore, there is a possibility that the infiltrated gas or liquid may not be entirely removed from the pores, resulting in trapped impurities in the PLK dielectrics. Such impurities may become the source of slowly developing failure mechanisms.

Cu

Figure 1. Transmission Electron Microscopy (TEM) micrograph showing an example of Cu outdiffusion by oxidation potential in PLK/Cu interconnects. Notice that a significant fraction of the dummy metallization lost Cu to surroundings.

The newly identified reliability concerns, including barrier failure and trapped impurities, are becoming central issues in PLK technology as they pose significant threat to the success of PLK technology. While extensive developmental efforts have been made to negate the problems, the progress is seriously hindered by the lack of quick, yet accurate, detection techniques for the conditions which lead to the new reliability threats. Standard measurement techniques, ritualized over the years, for characterization of integration success, including microscopic inspection of interconnect structure and series of long-term reliability testing, cannot be effective in revealing the newly problematic features. For instance, microscopic examination of random barrier interface can visualize only a small fraction of the entire interface, but a single tiny failure in any place can be fatal in PLK/Cu interconnects. Moreover, common analytical techniques utilized for chemical inspection of interconnects do not have adequate spatial resolution and sensitivity to detect trapped impurities that may be of small amount and share the same elements with dielectrics. On the other hand, the long-term reliability testing, including electromigration (EM), stress-migration (SM), and dielectric breakdown (DB), may reveal the impact of the concerned defects through exaggerated conditions. However, it not only takes a long time to gain meaningful results, but also often requires extensive additional analysis to identify the failure source. Therefore, the availability of a simple and effective technique that can detect the targeted reliability threats in PLK/Cu



interconnects in an as-processed condition is critically important for the desired progress in implementation of PLK technology. This paper introduces the voltammetry-based interconnect characterization (VBIC) that has been under development in our research for the past few years [8]. The technique is being developed with an aim of accurately detecting component failures in PLK/Cu interconnects without having to rely on complex analysis and sophisticated instrumentation. Specifically, it is proven to be highly effective in detecting failures in the barrier layer, capping layer and the presence of trapped impurities. In this paper, we detail the technique and its working principles, and give examples of how voltammetry is able to detect the defects in advanced interconnect structures provided by various industrial sources.

Background and Experiment The VBIC methods developed in our research is based on the active utilization of four simple facts. The first is the open-pore property of the PLK dielectrics. With an openpore structure, PLK dielectrics allow intentional infiltration of any gas or liquid, including an electrolyte solution. This means that an electrolyte containing selected ions can be injected and used as tracers for characterizing failures in interconnect structures. Secondly, the interconnect patterns common in the test and even in the actual devices can be used for voltammetry. For example, common interconnect test wafers contain an inter-digitized comb structure where two Cu interconnect lines are placed in parallel with a dielectric layer in-between. The original intention of such a pattern is for the electrical characterization of PLK dielectrics, such as the measurement of leakage current and DB. However, it also offers an ideal test structure for the application of VBIC. When the PLK layer in such a structure is infiltrated with an electrolyte, the pattern becomes essentially a two-electrode electrochemical cell consisting of two Cu/barrier electrodes and an electrolyte (in PLK). The two-electrode electrochemical cell concept formed in a comb structure is schematically shown in Figure 2. Third is that the motion of ions in electrolyte and electrochemical reaction at interconnects can be controlled and monitored by the application of external potential and measurement of the cell current. Because the pattern offers very large interface area, the resulting electrical current is sizable and can be measured without sophisticated electronics. The fourth idea that makes VBIC applicable to Cu PLK interconnects is that the structures are designed to isolate Cu completely from contact with PLK by barrier or capping layers. Thus, any infiltrated liquid in the electrochemical cell as described above should not find contact with Cu. The application of voltage to the cell creates the conditions for oxidation/reduction of any Cu exposed to the electrolyte. The first two VBIC methods used here have in common the search for this reaction current as an indication that barrier or capping layers are inadequate to keep Cu isolated from the PLK. The third technique expands the concept to find impurities trapped in PLK, rather than inspect for Cu exposure. The instrumentation required for VBIC is simple and consists essentially of a function generator to modulate the potential of the cell and pico-amp meter to track the resulting current. Figure 3 is a schematic representation of the essential instrumentation needed for the voltammetry system. The functional generator can be of any type as long as it can generate a saw-tooth wave signal at variable rates, but a computer controlled function



generator offers many advantages. In our research, both the function generator and picoamp meter are interfaced with a computer for the convenience of the signal control and data acquisition. One special requirement is an EMI shielding box to reduce the environmental noise during voltammetry measurement.

a)

b)

+/+/-

-/+

-/+ PLK

Cu

Ta

Figure 2. Schematic representation of an interdigitaed comb structure (a) and the formation of two-electrode chemical cell when PLK layer is filled with an electrolyte (b).

function generator

probe

pA meter EMI shield box

Figure 3. Schematic representation of measurement apparatus used for the Voltammetry.

One of the essential steps for VBIC techniques is the infiltration of the test solution (electrolyte or pure water) into the interconnect structure. In normal circumstances, a guard-rail within the chip surrounds the PLK/Cu test patterns, and liquid infiltration into the interconnect structure is not possible. In order to allow infiltration, therefore, it is necessary to open holes near the test pattern (within the guard rail) or cut through the guard-rail to expose the test structure to the ambient. Our research finds that the latter method works better because it is relatively simple and can be done safely without damaging the test structure. Once the cut is made, the infiltration is done by simply immersing the chip into the test solution. The time to complete infiltration depends highly on the PLK porosity, PLK type (MSSQ vs. SiCOH), test structure, and ambient temperature. For a common comb structure, complete infiltration at room temperature takes place within 2 hours for highly porous PLK (k=2.2-2.4) while it can reach up to several days for less porous PLK. It should be noted that the infiltration is possible even if the dielectric layer does not have an open pore structure. For instance, our research finds that electrolyte infiltration into FSG (fluorosilicate glass) having less than 10% porosity is possible when the chip is immersed into solution for a week. In this sense, the VBIC introduced in this paper are not limited to highly porous low-k interconnects, but



can be applied to almost all types of low-k dielectrics. Inducing infiltration at elevated temperature can significantly speed up the process, but the temperature should be below 70oC for protection of the test chip. Once infiltration is completed, the chip should be subjected to the voltammetry immediately to minimize the loss of liquid through vaporization. While voltammetry can be conducted at any ambient temperature, room temperature testing is found to be the adequate for most purposes. Results 1. Detection of Barrier Failure As mentioned above, the detection of failed barrier is extremely difficult by any conventional means. Cyclic voltammetry with 1-2% KCl electrolyte solution offers an unconventional resolution to this challenge. The principle idea behind the technique is the fact that Cu makes contact with electrolyte solution only through defects in the barrier and is electrochemically active. Importantly, the normal barrier material (Ta) is electrochemically inactive with an immediate passivation of its surface upon contact with ambient. It is therefore possible to induce reduction or oxidation (redox) reaction of Cu using an external potential and detect the presence of Cu (and thus presence of barrier defects) from the reaction current. The best condition for the detection of barrier defects is found to be cyclic linear voltammetry, where the external voltage applied to the cell swings linearly between negative and positive values. The ideal voltage range that can be safely employed is +/1V with ramp rate ranging from 1-200mV/s. This condition works the best because the cycling bias causes the Cu redox reaction to repeat with each cycle and the resulting current appears as peaks, ideally at the redox potential of Cu, in an IV diagram. In order to better understand the voltammetry behavior of the cell, it may be necessary to consider various barrier conditions and the resulting voltammetry signals. There are three possible variations in the barrier condition: 1) no defect in barrier at both electrodes; 2) equal density of barrier defect at both electrodes (symmetrical defect density); 3) one interface contains more defects than the other (asymmetric defect density). The voltammetry signal varies uniquely with each barrier condition as detailed below. capping layer

Cu

PLK

(a) zero defect

Cu

Cu

PLK

Cu

(b) symmetrical defect

Cu

PLK

Cu

(c) asymmetrical defect

Figure 4. Schematic representation of three different barrier conditions in PLK/Cu interconnects.

The first to consider is the case of no barrier defect at both electrodes (Fig.4-a). In this case, the cell behaves like a capacitor and it shows a simple and symmetrical IV hysteresis exemplified in Fig. 5. This figure shows the IV hysteresis of the cell formed by comb pattern Cu integrated with k=2.7 FSG dielectric measured under two different



voltage ramp rates. It can be seen that the hysteresis quickly becomes steady state (no change with cycles) and that the hysteresis becomes larger under faster ramp rate. The voltammetry data taken from the comb pattern with PLK dielectrics (k=2.2~2.5), regardless of PLK type, shows the same hysteresis pattern when the barrier is not defective. This type of hysteresis forms simply because the cell current is dictated only by the ionic current. In the given voltammetry situation, there are two current components and they are the current by ion migration (K and Cl) and by any reaction that injects additional charges to the cell. When the barrier is defect-free and thus no electrochemical reaction occurs at the Ta interface, the cell current comes only from ion migration (or polarization of electrolyte). In this case, the internal field due to ion migration and the external field work together in determining the total cell current, resulting in the behavior of current saturation with applied bias in each half cycle. The hysteresis becomes larger with increasing ramp rate because the influence of the internal field becomes weaker, as in the case of an electric capacitor. Regardless of the exact mechanism, the formation of a simple hysteresis without peak current indicates the absence of ion injection/drainage at the barrier interface, indicative of intact barrier. 1

Current, nA

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Voltage, V Figure 5. Example of voltammetry singal under two different ramp rates, showing a simple and symmetrical IV hysteresis. This data is taken from Cu interconnect comb structure integrated with FSG (k~2.9) dielectric layer. The width of dielectric layer is 0.15μm, and the thickness of Ta barrier is 20nm.

The second type of voltammetry signal is from interconnects with equal density of barrier defects on the mating interfaces (Fig.4-b). According to our testing on various samples from a few industrial sources, this is the most common type of barrier failure in PLK/Cu interconnects. In this case, the electrolyte can reach the underlying Cu electrode through the holes and cracks in the barrier, making it possible for Cu to react with electrolyte under bias. With an equal area of Cu exposure to the electrolyte on both electrodes, the cell configuration essentially becomes similar to electroplating. In one electrode, Cu dissolves into the electrolyte (oxidation), while Cu plating occurs at the opposite electrode (reduction). The dissolution and deposition of Cu introduces new ions to the electrolyte, not only resulting in an increase in the overall current magnitude, but also a peak in the voltammetry signal because the reactions should occur at a specific redox potential. An example of the resulting voltammetry signal is shown in Fig. 6, and is one of numerous examples we have collected from interconnects of varying PLK



types, porosity, pattern density, and barrier thickness. This particular data is taken from Cu interconnects integrated with MSSQ type PLK having 40% porosity and 10nm thick Ta as a barrier layer. The electrolyte used for this measurement is 2% KCl solution. It can be seen that the voltammetry shows markedly different characteristics from the one shown in Fig. 4. The first difference to notice is the overall level of cell current, which is more than an order of magnitude higher. The second is the presence of current peaks at each half cycle of IV hysteresis (marked with an arrow). Testing on various samples reveals that the peak generally appears at +/-0.3-0.4V. Since these two features would not appear without reaction at an electrode and the only known component that can react with the electrolyte in PLK/Cu interconnect is Cu, it is not unreasonable to conclude that the barrier under testing is defective and Cu electrode is exposed for reaction. It is worth mentioning here that we fail to visualize defects in the Ta barrier using microscopic inspection of failed samples, using both scanning electron microscopy (SEM) and TEM. Nonetheless, the presence of defects is confirmed after high temperature baking experiments in which Cu out-migration (as in Fig.1) is observed from the interconnects that voltammetry indicates have defective barriers. These results evidence the near impossibility of detecting barrier defects using microscopic inspection and the effectiveness of the VBIC technique. 0.15

media: 2%KCl; ramp rate: 40 mV/s

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Figure 6. Example of voltammetry singal showing a symmetrical IV hysteresis with reaction peaks at each half cycle. The data is taken from Cu interconnect comb structure integrated with MSSQ (k~2.2) having 40% porosity and 10nm Ta barrier. Note the presence of the current peaks near at +/-0.3V. The fact that the current peak occurs near at +/-0.3-0.4V appears to suggest that the reaction at the electrode involves a reduction/oxidation of Cu into cuprous ions because: Cu→Cu+++2e E°=0.34V

[1]

where E° represents the standard oxidation potential measured against a hydrogen electrode [9]. Our investigation indicates that it is indeed the case [10]. In the given cell configuration, oxidation reaction occurs at the anode and reduction reaction occurs at the



cathode. Among these two reactions, it is found that the anode reaction, that is the oxidation reaction, is the rate controlling reaction. This occurs because the oxidation (dissolution) requires external potential in order for it to proceed, while the reduction reaction (deposition) occurs spontaneously. This is indicated by the positive sign of the standard half-cell potential shown in eq.(1). In the two-electrode configuration, the true potential at each electrode is impossible to measure accurately, however, since reduction occurs without impedance, it is likely that the potential drop at the cathode electrode is near zero. This causes the external potential to be applied mostly to the anode electrode, resulting in the peak potential being close to the half-cell potential of Cu oxidation. It is not yet clear why the redox reaction in the PLK voltammetry does not involve the usual two-step reaction path of Cu, involving cupric (Cu+) ion formation, namely Cu→ Cu++e E°=0.52V Cu+→Cu+++e E°=0.15V

[2] [3]

We speculate that this is related to the sluggish motion of ions in PLK structure and the unstable nature of cupric ions, but it remains to be investigated. 0.4

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Voltage, V Figure 7. Example of voltammetry signal at the quasi-steady state (after 10 cycles) showing an asymmetrical IV hysteresis resulting from an extreme difference in barrier defect density at two mating electrodes. This data is taken from a comb structure made of Cu interconects with 20nm barrier and FSG low-k dielectrics.

The third type of voltammetry signal, which is found to be rather rare in real interconnects, occurs when the mating electrodes have dissimilar density of barrier defects (Fig. 4-d). In this case, which includes the situation where one side of barrier is completely intact and the other side is defective, the amount of cuprous ions injected by oxidation and drained by reduction is no longer balanced. This leads to development of asymmetrical IV hysteresis as a reflection of the unbalanced reactions at two electrodes. Our investigation using a simulation cell, which is made of two Cu plates with different coverage of Ta, reveals numerous insights helpful in understanding the formation of IV hysteresis under dissimilar defect density. It is found that the level of peak current at each half-cycle is no longer the same when the difference in defect density is small. Also, peak potential starts at the oxidation potential of Cu during early cycles, but drifts



away from it. This is attributed to the development of sizable voltage drop at the cathode electrode due to unbalanced cuprous ion drainage compared to its injection rate. When the defect density is excessively dissimilar, the current peak can disappear completely. Rather, the IV hysteresis shows the extreme asymmetric behavior displayed in Fig. 7. This data is obtained from FSG (k=2.9)/Cu interconnects with 10nm Ta barrier after infiltration of 2% KCl. It can be seen that the hysteresis lacks the peak but develops distinctive asymmetricity. Another noteworthy behavior of the asymmetrical hysteresis is the fact that, unlike in the first two cases, it does not reach steady state within the first few cycles. It often takes a few tens of cycles before it reaches the quasi-steady state. We believe that this behavior is result of excessive cuprous ions injected in the first few cycles that cannot be effectively drained. Such behavior is also visible in the hysteresis shown in Fig. 7. Note that the long-tail end of hysteresis varies with cycle. Many variations in voltammetry signal can exist with variation in interconnect structure, PLK types, and barrier condition in mating electrodes. With such variations, the detection of barrier defect may appear to require complex analysis of the IV signal. However, it turns out that detection is rather simple. Any interconnect with IV hysteresis that deviates from Fig. 5, that is, a simple and symmetrical hysteresis, can be declared to contain defective barrier in one or both of the mating electrodes if the interconnect test structure has symmetrical interface area (a comb structure, for example). When the interface area is not the same, further analysis may be necessary to include the influence of the different electrode area on the hysteresis shape. However, it is found that the number of cycles to reach the steady state hysteresis can be used as an alternative criterion. For an intact barrier, the hysteresis reaches the steady state within the first few cycles even though the interface area is not the same. On the other hand, when the barrier is defective, the voltammetry signal resembles that seen in Fig.7. 2. Detection of Capping Layer Failure One of the newly arisen concerns of PLK technology, which is as equally vexing as barrier failure, is the possibility of developing cracks in the capping layer. The capping layer refers to the dielectric layer that covers the top of the interconnects of one layer for the purpose of providing electrical isolation from other layers in multi-level structures. The capping layer is subjected to a significant level of mechanical stress during CMP (chemical mechanical polishing) and thus prone to failure by cracking. Similar to the case of barrier failure, cracks in the capping layer can not be characterized by any normal microscopic means because they can be randomly located and they do not produce sufficient contrast to be detectable. Nevertheless, because such crack can allow permeation of process gases and liquids, especially CMP solution, they need full characterization before qualification of PLK integration processes. The voltammetry technique has proven to be highly effective in detecting cracks in the capping layer. The characterization method is simple and shares many similarities with the technique used in barrier characterization. It starts with the infiltration of an electrolyte solution, typically 2% KCl, into multi-layer interconnect test chip. Then, two interconnect patterns facing across the capping layer are chosen for application of the cyclic bias. Figure 8-(a) shows one of many electrode configurations possible for capping layer integrity characterization. In this particular case, the comb structure at M1



and a large dummy Cu electrode at M2 are chosen. However, any two sets of electrode, one from the bottom and the other from top, can be chosen. b)

Cu

Ta

layer

2 1

+/M2 Via layer PLK

Current, nA

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failure

M1 -4 -0.8 -0.6 -0.4 -0.2

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Figure 8. (a) Schematic diamgram showing one possible electrode configuration ideal for capping layer voltammetry characterization in multi-level interconnects; (b) the resulting IV hysteresis conducted on Cu/PLK (SiCOH: k~2.6, ~35% porosity) with 40nm SiCN capping layer using the electrode configuration of (a). Two different cases, indicating intact and failed capping layer, are compared in this plot.

After infiltration, PLKs both at M1 and via layer (and also M2 layer) are filled with the electrolyte. When the capping layer is intact, ion migration across the capping layer is physically prohibited. This means that the conduction circuit by ion migration between M1 and M2 does not exist, leading to open circuit behavior in the IV hysteresis. Specifically, no current flows under any external bias during voltammetry. However, when the capping layer contains physical cracks, ion migration can take place across the capping layer, making the M1 and M2 electrode form a two-electrode electrochemical cell. The exact IV hysteresis can vary significantly with the choice of electrodes, crack density, and location of the crack. However, any hysteresis in current other than zero is an indication of the failure in the capping layer. Figure 8-(b), where voltammetry results are shown from Cu/PLK (SiCOH: k~2.6) interconnects with 40nm SiCN capping layer, presents an example IV hysteresis indicating the failure in the capping layer. Because the electrode configuration in Fig. 8-(a), in which the electrode interface area is asymmetrical, is used for this measurement, the IV hysteresis deviates from a simple and symmetrical hysteresis. However, the simple fact that a sizable amount of current flows with hysteresis formation evidences the conduction by ion migration across the capping layer. Also noteworthy is the fact that the hysteresis contains current peak at the right hand side, marked with an arrow. We believe that the peak originates from a Cu oxidation reaction which occurs because the capping layer crack formed directly on top of the M1 Cu interconnects. Therefore, it may be possible to identify the crack location when the detailed analysis on the hysteresis shape becomes available. 3. Detection of Trapped Impurities The possibility of trapped impurity is another persistent but less well addressed concern in PLK/Cu interconnection technology. As previously mentioned, the pores in PLK dielectrics are interconnected, increasing the likelihood of infiltration of process



chemicals through the pore network and leaving chemical residues on the pore surface. Aqueous chemicals, such as solutions for resist cleans, electroplating, or CMP (chemicalmechanical-polishing), are particularly troublesome, as there are no practical methods of removing the solution without leaving ionic residues. Equally troublesome is the lack of an effective method of detecting it. Common analytical techniques, such as EPMA (electron probe micro analyzer) and SIMS (secondary ion mass spectrometry), are often inadequate for characterization of such ionic residues. Both the limitations in detection resolution and their inability to detect ionic states of elements make them ineffective for impurity detection, especially when contaminants have the same elements as the interconnect components themselves (Cu, barrier, PLK). Our research finds that a simple extension of this VBIC technique can provide an effective resolution to this characterization challenge. The second VBIC technique utilizes water as a testing media instead of an electrolyte. Since ionic contaminants on pore surfaces of the low-k dielectric can react with the infiltrated water to become mobile ions, the water can become electrically conductive in proportion to the mobile ion concentration. Therefore, the presence of ionic chemicals on pore surfaces can be determined by measuring the level of electrical conduction across any two sets of mating Cu interconnects like the one used for the barrier characterization. The detection works best when the measurement is combined with the cyclic voltammetry technique. With an electrochemically inert Ta barrier, the motion of ions is confined between the two electrodes. Cyclic bias forces ions to move back and forth between the two electrodes, and thus, allows more reliable measurement of conductivity with less interference from the capacitive behavior of the circuit. 0.3

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Figure 9. A plot comparing two different I-V voltammetry responses of comb structure taken from the same wafer. The samples used for this characterization is taken from Cu/PLK (SiCOH: k~2.6) comb structure.

The data shown in Figure 9 exemplify the effectiveness of the linear cyclic voltammetry technique in detecting pore contamination when it is conducted on a comb structure after water penetration. The samples used for this test are taken from a standard 2-level interconnect test wafer having PECVD SiCOH as the interlayer dielectric. Two contrasting voltammetry responses from two identical comb patterns from the same wafer



are compared in the figure. The first response is the near zero current under linearly cycling voltage. Since de-ionized and degassed water is highly insulating (>10MΩ-cm), its penetration into contaminant-free pores does not impact the electrical conductance of the dielectric, and the cell current remains unchanged by water penetration. Contrasting with this is the second response, which exhibits a simple IV hysteresis with large current, resembling the one in Fig. 5. Within a few cycles, the IV hysteresis reaches a steady state and does not change with further cycling. This is the characteristic voltammetry behavior of an electrolyte cell with non-reacting electrodes. In our developmental research, a large number of industrial samples at the various stages of integration are examined to determine the effectiveness of water-based VBIC in characterizing the trapped impurities. The technique has proven very successful because it offers extreme sensitivity to the trapped impurity with unprecedented speed. For instance, after infiltration, contamination characterization of test chips in 8" wafer can be completed within an hour even without using automated sample scanning apparatus. Such scanning often showed that the contamination was not universal but located at particular places within a wafer, which may be important information for process engineers. The most time consuming part is the infiltration, as it involves the creation of cut to allow infiltration and the time to complete infiltration. Further development in instrumentation and test process will certainly improve the speed. The technique needs substantial improvements in two critical areas. The first is a technique for identification of the contaminants detected. In order to prevent the contaminant from entering the PLK, it is important for process engineers to know where those contaminants originate. Our attempts to identify the detected impurity shown in Fig.8 using SIMS (secondary ion mass spectrometry) and EELS (electron energy loss spectroscopy) fail to produce convincing results. Although both characterizations do find near background level of fluorine, which may originate from CH4 etch gas residue, as a foreign element in PLK, the result is not highly convincing as the spectroscopy signal is too close to the resolution limit. The extreme detection resolution of the voltammetry is possible because it detects the presence of impurities through electrical measurement where the signal can be amplified. Hence, it is desirable to develop an identification method based on a similar approach. One possible route is to combine titration and voltammetry. When contamination is detected, a series of known ions can be added to water and injected to the contaminated pattern. When the injected ions react with impurity ions and produce precipitates, the number of mobile ions decreases, and so does voltammetry signal. Although this approach may require extensive developmental efforts before implementation, it may be the most sensitive method for the contaminant identification. The second area that requires further development is the quantification of the contaminant. Voltammetry can reveal only the presence or absence of contaminant. The result as given in Fig. 8 cannot provide any indication as to the amount of contaminant. It is, of course, possible to gain a comparative quantification from the strength of voltammetry signal. The chip producing the larger IV hysteresis contains more contaminants when measured at the identical ramp rate and voltage range. However, as knowledge of the exact amount is often desired, it is important to develop a technique for quantification. Among many routes explored in our research, the voltammetry signal itself appears to offer the best route. The voltammetry hysteresis is determined by the ion



mobility and quantity. It is therefore possible to determine the ion quantity if the mobility is known. However, if the identity of the ion and its diffusivity in the given PLK media are unknown, the ion mobility is an unknown parameter. Thus, it is necessary to extract both the ion mobility and the quantity from the voltammetry result. In an ideal case, such determination can be done by way of simulating the ion motion and the resulting signal under voltammetry condition. This simulation requires solving the Nernst-Planck equation for a given geometry of PLK/Cu and voltammetry conditions [11-12]. At the present moment, with a lack of suitable analytical solution, the quantification is not yet possible, and further efforts appear to be necessary. Discussion As is introduced in this paper, VBIC offers effective resolution to the characterization challenges ahead in PLK/Cu interconnection technology. The methods are extremely simple to apply yet the result is highly accurate. Such accuracy is possible because the technique is specifically tailored to characterize a targeted defect. This eliminates characterization ambiguities and background interference common in other microscopic and spectroscopic techniques. It should be also noted that the technique is probably the only technique that can carry out such characterization for the as-processed condition of the interconnects. While the usefulness of VBIC has been demonstrated in the case of defects in barrier, capping layer, and PLK (contamination), it can be easily extended to other characterization targets. Two examples can be mentioned here. The first is the characterization of the pore-seal layer that may be deposited prior to the barrier layer with the aim of improving the integrity of the barrier and preventing PLK contamination. One of the critical requirements of the pore-seal layer, created by polymer deposition, is the complete coverage of the PLK surface without pin-holes or cracks. Similar to the case of the barrier and capping layer, flaws in the seal layer are impossible to detect by any microscopic techniques. However, the pore-seal layer can be inspected with the electrolyte based voltammetry technique. The idea behind the characterization is again simple. When the pore-seal is flawless, an electrolyte cannot make contact with the underlying Ta or Cu layer, making the cell an electrically open circuit. No hysteresis formation in voltammetry signal is expected. On the other hand, in case of flaws, the cell becomes electrically conductive because the ions in the electrolyte can reach the Ta/Cu electrode. The voltammetry should yield IV hysteresis with the signal strength reflecting the density of the flaws. Our trials with a few samples from the early developmental stage of pore-seal layer, although limited, do find that such characterization is indeed possible. The second possible extension of the VBIC is the characterization of the pore structure (size and pore density) in PLK dielectrics, not necessarily in a blank film but at as-processed condition. This capability is important because the pore structure may vary significantly even within a chip, for example, with variation in the pattern density. An extension of the VBIC has the potential to be useful for this purpose as the ions in an electrolyte can be used as a mobility tracer. In this case, another mode of voltammetry can be used, such as step-mode voltammetry after infiltration of 2% KCl as an electrolyte. In the step-mode, the infiltrated comb interconnect pattern with known PLK dimension is subjected to a constant bias until complete polarization of ions by electric field takes place. When the polarization is complete, the cell current becomes zero due to



a balanced potential between the external field and the internal field. When the bias is removed at this point, the force to restore chemical equilibrium induces diffusion of polarized ions until attainment of uniform ion composition across the cell. The restoration process produces exponentially decaying current in the opposite direction that can be measured using an ammeter. Since the kinetics of the decaying current are not affected by external field (no external field exists) and governed only by internal diffusion, diffusivity can be computed based on Fickian diffusion model. Then, the pore structure can be indirectly characterized from the ion diffusivity using its sensitivity to pore size and porosity, as is presented elsewhere [13]. The final note on the potential extensions of VBICs is the necessity for more fundamental understanding on voltammetry behavior. As is demonstrated, VBIC fails to yield quantitative data on the characterization target, such as the defect density in the barrier and capping layer. This limitation stems from the difficulty in developing a suitable electrochemistry model because the majority of electrochemical theories are developed for the three-electrode configuration, that is, the cell with working, counter, and reference electrodes. Because the three electrode configuration allows the tracking of the chemical potential at the working electrode, quantitative model relating the measured current to the reaction or ion polarization is possible. However, the VBIC techniques are based on two-electrode configuration where each electrode serves as a working as well as a counter electrode for the other electrode. This is rarely considered in the field of electrochemistry, but our research appears to suggest that two-electrode electrochemical cells can yield useful information and that the theory needs attention.

Summary This paper introduces the working principles of VBIC for detecting the presence and absence of defects in PLK/Cu interconnect structure. Specifically, the technique of detecting 1) the defects in the barrier, 2) the defects in capping layer, and 3) contaminants trapped in PLK, is shown. As is demonstrated, VBIC allows simple yet effective characterization of component failures in PLK/Cu interconnects without having to rely on complex and sophisticated analysis, yet it needs further development in order to reach its full potential as a characterization metrology. Presenly, developed VBIC methods are incapable of providing quantitative data on the characterization target such as the defect density in the barrier and impurity concentration. Quantitiatve characterization may become possible when suitable models relating electrochemical reaction and electrolyte motion to the resulting voltammetry signal in two-electrode cell are developed.

Acknowledgements This research is supported by SRC (Semiconductor Research Corporation) under contract #1292.052 and 2071.009.

References



1. K. Maex, M. R. Baklanov, D. Shamiryan, F. Iacopi, S. H. Brongersma and Z. S. Yanovitskaya, J. Appl. Phys., 93, 8793 (2003). 2. M. Morgen, E. T. Ryan, J.-H. Zhao, C. Hu, T. Cho and P. S. Ho, Annu. Rev. Mater. Sci., 30, 645 (2000). 3. International Technology Roadmap for Semiconductors, 2006 ed. (Semiconductor Industry Association, San Jose, CA, 2006) (http://public.itrs.net). 4. M. Fayolle, G. Passemard, O. Louveau, F. Fusalba and J. Cluzel, Microelectron. Eng., 70, 255 (2003). 5. N.L. Michael, C.-U. Kim, P. Gillespie, and R. Augur, "Mechanism of reliability failure in Cu interconnects with ultralow-k materials", Appl. Phys. Lett., 83, 1959 (2003). 6. N.L. Michael, D.M. Meng, C.-U. Kim, S.H. Kang, and Y.J. Park, Proceedings of Advanced Metallization Conference, (MRS, 2004), pp.269-273. 7. L.S. Chen, W. H. Bang, Choong-Un Kim, Young-Joon Park, "Observation of space charge limited current by Cu ion drift in porous low-k/Cu interconnects", Appl. Phys. Lett. 96, 091903 (2010).

8. C.-U. Kim, D.M. Meng, N. Michael, Y.-J. Park, and S. Satyanarayana, Proceedings of Advanced Metallization Conference, (MRS, 2004), pp.679-685. 9. See for example, Standard Potentials in Aqueous Solutions, A. Bard, R. Parsons, eds., (Marcel Dekker, New York, 1985), p. 292. 10. D. M. Meng, N. L. Michael, Y.-J. Park and C.-U. Kim. J. Electron. Mater., 37, 429 (2008). 11. Malcolm Smyth and Johannes G. Vos, eds., Analytical Voltammetry, (Elsevier, Amsterdam, 1992). 12. David K. Gosser, Jr., Cyclic Voltammetry, (Wiley-VCH, New York, 1993). 13. D. M. Meng, N. L. Michael, C.-U. Kim and Y.-J. Park, Appl. Phys. Lett., 88, 261911 (2006).


Development of Voltammetry-based Techniques for ...

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