Digital compensation of memory errors in passive Sigma-Delta modulators employing FIR filter Rasoul moradi1,*, Ebrahim Farshidi2, and Mohammad Soroosh3 Department of Electrical Engineering, Shahid Chamran university of Ahvaz, Ahvaz, Iran *corresponding author:
[email protected], telephone number: 00989171454749 2 Department of Electrical Engineering, Shahid Chamran university of Ahvaz, Ahvaz, Iran email address:
[email protected], telephone number: 00989166148163 3 Department of Electrical Engineering, Shahid Chamran university of Ahvaz, Ahvaz, Iran email address:
[email protected], telephone number: 00989122965969 1
ABSTRACT This paper propose a finite impulse response filter for compensation method to improve resolution of passive discrete-time sigma-delta modulators. The passive integrator transfer function leading to gain and phase errors, degenerates the modulator performance because of signal attenuation in modulator loop. The error of passive integrator is modeled as an output-referred model and Finite Impulse Response filter is employed for compensation. The method is applied to the first and second order passive sigma-delta modulator to achieve low-power and high resolution. Result of simulation demonstrated that the gain and phase errors compensation by the method is effective. Keywords: Analog to digital converter (ADC), Digital compensation, Finite impulse response filter, Passive sigma-delta
1.
INTRODUCTION
Technology scale has greatly reduced the digital power at complex signal systems. However, the front-end analog circuits do not take advantage of this property. Due to using oversampling and noise shaping properties, ΔΣ modulators have a better trade-off between sampling rate and signal to noise ratio (SNR) [1]. Compared with Nyquist rate modulator, to achieve high resolution, high oversampling rate, higher order modulator or multi-bit quantizer is used. An integrator is required to increase the modulator order and to create an extra zero in the noise transfer function. High order and multi-bit quantizer lead to the complexity and increase the power. Also increasing the sampling rate increases the power consumption. The power consuming active integrators is replaced with passive switched capacitor integrators that have low power consumption to reduce the power consumption of modulator [2]–[4]. This replacing reduces the power consumption greatly. While passive integrators have very low power consumption, they attenuate the signal and cause phase and gain errors [5]–[8]. One solution can be digital calibration. Different works have been done for active ΔΣ modulator compensation, some for limited amplifier gain and some for capacitance mismatch [9]–[11]. In this work, calibration technique using adaptive filters for compensating the error caused by switch capacitors based passive integrators is presented. The suitability of the proposed technique is shown for first and second order passive modulator. In this research, the error caused by passive modulator for first and second order modulator is modeled, and then a technique by using adaptive filters is proposed for compensation error caused by S.C passive integrator. The rest of the paper is organized as follows: in section 2, S.C passive integrator is discussed, and then an account is given of the integrator transfer function, first and second order modulator. The error caused by passive modulator in first and second modulator is modeled at section 3. Digital compensation and the simulation results are presented in section 4 and 5 respectively. Finally, conclusion comes in section 6. 2. CIRCUIT ERROR MODELING In this section, switch capacitor passive integrator (SCPI) and its errors are introduced first, and then an error model is proposed for it. Gain and phase errors of integrator are written based on integrator output by using this model. 2.1 Passive Integrator The basic passive integrator is shown in Fig. 1 It has optimum power but its transfer function has error. Its transfer function is
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H p z which α
z 1
)1(
1 ßz 1
Cs and 1 .The transfer function implies both gain and phase error compared with ideal transfer Cs Ci
function H z
z 1 . 1 z 1 Vin
Cs
ɸ1
ɸ2
ɸ2 vcom ɸ1
Voutp
Ci
ɸ1 vcom
ɸ2
Fig. 1. Basic passive integrator for single ended
Time domain output- input relation for the PI is as follows:
Voutp n
Cs Ci Voutp n 1 Vin n 1 Voutp n 1 Vin n 1 Ci Cs Ci Cs
)2(
where vout and vin are output and input voltage of passive integrator respectively. There are two states to make a passive transfer function more similar to the ideal active transfer function. First, Cs should be higher than Ci to reduce gain error, which increases phase error. Second, Ci should be higher than Cs to improve phase error, which increases gain error. Therefore, there is a trade-off between Ci and Cs in terms of phase and gain errors. Both of them are important, but phase error moves the pole of the integrator, and as a result, the NTF zero of the ΔΣM moves. Consequently, noise shaping does not happen properly and the phase error has the highest priority. Integrating and sampling capacitors ratio determine the quantizer equal gain and hence, affect the modulator performance [9]. In order to improve the phase error, this ratio should be high and severe attenuation occurs in the modulator. However, there is thermal noise limitation for the minimum of Cs as: Cs
KT 2
N
)3(
OSR (V FS ) 2
where k is Boltzmann constant, T stands for absolute temperature, N is effective number of modulator bits and V FS is the full-scale input. 2.2 First Order Passive ΔΣ Modulator A typical passive ΔΣ modulator has the customary active ΔΣ modulator except that integrator loop filter is replaced with SCPIs. However, the basic feedback structure is a better choice due to less interconnections and lower loading effect. Eq X
+ -+
α
++ +
𝑧 −1
+
D
β
Fig. 2. Conventional error modeling of the passive integrator
Fig. 2 shows the linear model for the cascade of integrators feedback (CIFB) architecture. Phase and gain errors of the PI dislocate zero and pole of the signal and noise of transfer function.
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D Z
Z 1 1 Z 1 X z E q (z ) 1 Z 1 1 Z 1
)4(
The dependency of integrator output upon α and β motivates modeling the output-dependent error represented in Fig. 3 inspired by [8]. Ea X
+ + Vin + + +
𝑧
−1
Vouti
Eq
+
Voutp
+
D
Fig. 3. Proposed accumulative error modeling of the PI
The additive error signal is and the rest of the modulator is considered ideal. Modulator output can be obtained as:
d n x n 1 ea n eq n eq n 1
)5(
error is the difference between ideal and passive integrator outputs. It is preferable to calculate the error based on digital output modulator. Ideal integrator output-input relationship is:
V outi n V outp n -1 V in n -1
)6(
The error model shown in Fig. 3 is explained using a switched capacitor realization of the passive integrator in Fig. 1 where the assumption is that it operates in non-overlapping two-phase sampling and integration. In the φ1 phase of the clock cycle n-1, the integrator output V out n 1 is stored on Ci and the input is sampled on Cs, in the next clock phase of the cycle n, the previous cycle output is integrated with a coefficient of less than one ofV in n 1 . According to (2) and (6), modulator error can be obtained as
ea (n ) Vin (n 1) Voutp (n 1) [Vin (n 1) Voutp (n 1)]
)7(
Substituting V in (n 1) in (6), the error (7) is rewritten as
e a (n )
C C s C 1 V (n ) Voutp (n 1) i Voutp (n ) i Voutp (n 1) outp Cs Cs
)8(
Note that each of the two terms in (8) is instantaneous with respect to the corresponding output i.e, a transversal structure of memory, which the modulator error will be a two tab memory of (Vout) the modulator output. From (8) the z domain error given by
E a (z ) [
C C s Ci z 1 i ]Vout (z ) Cs Cs
)9(
If we can create the modeled error at (9) and subtract it from the integrator output, we can remove the error from the modulator and its output is almost ideal. Action can be taken in both digital and analog region to remove modulator error. In analog compensation, it is required to use amplifier, which consumes high power and has nonlinearity. Implementation in digital region is more accurate and it is possible to have lower power. Therefore, digital compensation is preferable. Integrator and modulator outputs relate to each other as:
d (n ) Voutp (n ) eq (n )
)10(
From (9) and (10) the additive error is obtained as:
e a (n )
C C s Ci (d (n ) eq (n )) i (d (n 1) e q (n 1)) Cs Cs
)11(
Assuming that eq (n ) can be neglected compared with d (n ) in (11), it gives:
e d (n )
C C s Ci d (n ) i d (n ) Cs Cs
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)12(
3
where e q ( n ) is the modulator quantization noise that was determined with quantizer resolution which is quite small in modulators. 2.3 Second Order Passive ΔΣ Modulator Second order modulator with passive integrator is shown in Fig. 4(a). Passive integrator in Fig. 4(a) was replaced with ideal integrator with accumulative error signal in Fig. 4(b). Passive integrator with gain and phase error X
Passive integrator with gain and phase errors Eq
++ 𝛼1 + + +
𝑧
+ 𝛼2α ++
−1
+
𝑧
−1
+
D
β2
𝛽1
(a) X
Ea
Ea +
+
+
-
+1 +
𝑧
−1
+
++ -
+ 2 + +
𝑧
−1 q
E +
+
D
(b)
Fig. 4 (a) Conventional and (b) output-referred distortion models of a second-order passive sigma-delta modulator
The ideal modulator output is:
d i (n ) x (n 2) eq (n ) eq (n 2) 2eq (n 1)
)13(
Passive modulator output along with error signal is:
d (n ) x (n 2) ea1 (n 1) ea 2 (n ) ea 2 (n 1) eq (n ) eq (n 2) 2eq (n 1)
)14(
So for second order modulator error yields:
ea (n ) ea1 (n 1) ea 2 (n ) ea 2 (n 1)
)15(
Each stage error is defined as: e aj (n )
j 1 j j Voutj (n ) Voutj (n 1) j j
)16(
Where Vout1 and Vout2 are the first and second integrator outputs respectively. They are as
Vout1 (n 1) d (n ) d (n 1) ea 2 (n ) eq (n ) eq (n 1)
)17(
Vout2 (n ) d (n ) eq (n )
)18(
Therefore, total modulator error at output is:
e a (n )
1 1 1 1 Vout1 ( n 1) 1 Vout1 ( n 2) 2 Vout2 ( n ) 1 1 2
)19(
2 2 1 2 Vout2 (n 1) 2 Vout2 (n 1) 2 Vout2 (n 2) 2 2 2
Giving that V out 1 depends e a 2 on in (17) in calibration, e a 2 is determined first and then its result for determining applied. Substituting (16), (17) and (18) in (19) gives:
e a (n ) 1[d (n ) d (n 1) eq (n ) eq (n 1)] 2 [d (n 1) d (n 2) eq (n 1) e q (n 2)] [d (n ) eq (n )][1 3 3 ] [d (n 1) eq (n 1)][1 4 2 3 3 4 ] [d (n 2) eq (n 2)][ 2 4 4 ]
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)20(
is
where i are as 1
1 1 1 ، 2 1 1 ، 3 2 and 4 2 2 . Neglecting eq (n ) compared with d (n ) gives: 1 2 1 2
ed (n ) d (n )[1 13 3 ] d (n 1)[1 2 3 4 1 4 23 ] d (n 2)[ 2 2 4 4 ]
)21(
The passive modulators error with a digital FIR filter is obtained from its output. 3.
PROPOSE METHOD FOR DIGITAL COMPENSATION
In previous section, error model of passive Σ∆ modulator is introduced. Transfer function of FIR filter is:
HFIR a 0 a1z1 a 2 z2 ... a n z n
)22(
It is obvious from (12), (21) that the calculated error of passive modulators can implemented by FIR filters. In following sub-section, these filters are investigated for first and second order modulators. 3.1 First Order Passive ΔΣ Modulator Fig. 5 illustrates the passive Σ∆ modulator accompanied by compensatory FIR filter. Passive integrator with accumulative error
T X
𝑧 −1
Ea
+ ++
-
++ +
𝑧 −1
+
b
Eq
+
+ D
a
ed(n)
++
Fig. 5. Block diagram of digital calibration scheme for the first-order sigma-delta modulator and FIR filter
First order modulator error, (12), is constructed by FIR filter and the calibrated output is obtained by subtracting the error from the modulator output. According to (5), can be written as
x n 1 d n ea n eq n eq n 1 d c (n )
)23(
If the quantization noise is ignored and modulator error is omitted, the calibrated output Dc represents X. Modulator digital error is:
E d (Z ) aD (z ) bz 1D (z ) Which a
)24)
Ci C Cs and b i . Cs Cs
Therefore the calibrated output written as:
d c (n ) d n ad (n ) bd (n 1)
)25(
3.2 Second Order Passive ΔΣ Modulator Fig. 6 illustrates the second order passive Σ∆ modulator accompanied by compensatory FIR filter. Second order modulator error, (21), is constructed by FIR filter and the calibrated output is obtained by subtracting the error from the modulator output. According to (14), can be written as
x (n 2) d (n ) ea1 (n 1) ea 2 (n ) ea 2 (n 1) eq (n ) eq (n 2) 2eq (n 1)
)26(
If the quantization noise is ignored and modulator error is omitted, the calibrated output Dc represents X.
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Passive-active integrator with accumulative error Ea1
X
-
++ +
+
𝑧 −1
+
Passive-active integrator with accumulative error Ea2
X
-+
++ +
𝑧 −1
+
Eq
+
D
++ -
+
ed1(n)
+ +
a1
𝑧 −1
Dc
𝑧 −1
𝑧 −1 d1(n)
+-
d2(n)
𝑧 −1
b1
a2
ed2(n) -
+ +
b1
Fig. 6. Architecture of proposed digital calibration scheme of the second-order sigma-delta modulator
E a1 and E a 2 errors From (26) are functions of Vout1 and Vout2 respectively. Error model is created based on digital version of integrator outputs of Vout1 and Vout2 named D1 and D 2 respectively. The digital output of second integrator is obtained directly from the quantizer, which is the output of the modulator and that of D1 according to (17) as follows
V out 1 (n 1) d (n ) d (n 1) e a 2 (n )
)27(
eq (n ) eq (n 1)
(1 z 1 )D 2 (z ) E d 2 (z ) z 1 which is implemented in Fig. 7(b). The integrator errors are estimated as: D1 (z )
)28(
ed 1 (n ) a1d1 (n ) b1d1 (n 1)
)29(
ed 2 (n ) a2d 2 (n ) b2d 2 (n 1)
)30(
According to (13) and (14), The calibrated output of the passive modulator (PM) is:
Dc (z ) D 2 (z ) z 1E d 1 (z ) (1 z 1 )E d 2 (z )
)31(
D (z ) E d (z )
Noise shaping of second integrator error E d 2 is done with (1 z 1 ) . From (31) and (21) The calibrated output of the passive modulator (PM) is:
Dc (n ) D (z ) D (z )[1 13 3 ] z 1D (z )[1 2 3 4 1 4 23 ] z 2 D (z )[ 2 2 4 4 ]
)32(
4.
SIMULATION RESULT In this section, the calibration simulation of the first and second order modulator shows the effectiveness of the proposed technique. Sampling rate and oversampling ratio are 32 KHz and 16 respectively. Input signal is 1% of clock frequency of signal. 4.1 First-Order Passive ΔΣ Modulator Fig. 7 shows the power spectral density (PSD) of first order passive modulator output with 2^15 point Fast Fourier Transform (FFT). The amplitude of the input signal is -4dBFS. Fig. 7(a) shows the PSD for an ideal modulator. Fig. 7(b) shows the PSD for a non-calibrated passive modulator. Fig. 7(c) shows the PSD for a calibrated passive modulator, which shows the suitability and effectiveness of the proposed technique.
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Fig. 7. Simulation results of a 5-bit first order ΔΣ modulator: a) with ideal integrator, b) passive integrator, c)
passive integrator after 4.2 First-Order Passive ΔΣ Modulator Fig 8. shows the power spectral density (PSD) of the second order passive modulator output with 2^15 point Fast Fourier Transform (FFT). The amplitude of the input signal is -4dBFS. Fig. 8(a) shows the PSD for an ideal integrator based modulator. Fig. 8(b) shows the PSD for a non-calibrated passive modulator. Fig. 8(c) shows the PSD for a calibrated passive modulator, which shows the suitability and effectiveness of the proposed technique.
Fig. 8. Simulation results of a 5-bit first order ΔΣ modulator: a) with ideal integrator, b) passive integrator, c)
passive integrator after calibration 5.
CONCLUSION In this paper a background digital calibration technique is proposed for phase and gain error compensation in passive modulator. An accumulative error model is proposed for non-ideal modeling of the gain and phase errors at the output of the passive integrator. The simulation results show great improvement in the modulator performance. Therefore, the Ci value becomes so relaxed that it reduces power consumption and chip area. REFERENCES [1] F. Maloberti, Data converters. Springer Science & Business Media, 2007. [2] A. F. Yeknami, F. Qazi, and A. Alvandpour, “Low-power DT ΔΣ modulators using SC passive filters in 65 nm
CMOS,” IEEE Trans. Circuits Syst. I Regul. Pap, vol. 61, no. 2, pp. 358–370, 2014. [3] T. Sai and Y. Sugimoto, “Design of a 1-V operational passive sigma-delta modulator,” in ECCTD 2009 -
European Conference on Circuit Theory and Design Conference Program, 2009, pp. 751–754. [4] A. F. Yeknami and A. Alvandpour, “A 0.5-V 250-nW 65-dB SNDR passive ΔΣ modulator for medical implant
devices,” in Proceedings - IEEE International Symposium on Circuits and Systems, 2013, pp. 2010–2013. [5] B. H. Seyedhosseinzadeh and A. Nabavi, “A MOS Parametric Integrator With Improved Linearity for SC ΣΔ
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for High-Resolution and Low-Power Applications,” IEEE Trans. Very Large Scale Integr. Syst., vol. 25, no. 1, pp. 364–374, 2017.
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[7] A. Hussain, S.-W. Sin, U. Seng-Pan, and R. P. Martins, “NTF zero compensation technique for passive sigma-
[8] [9] [10] [11]
delta modulator,” in Microelectronics and Electronics (PrimeAsia), 2011 Asia Pacific Conference on Postgraduate Research in, 2011, pp. 82–85. F. Qazi and J. J. Dabrowski, “Passive SC Sigma Delta Modulators Revisited: Analysis and Design Study,” IEEE J. Emerg. Sel. Top. Circuits Syst., vol. 5, no. 4, pp. 624–637, 2015. S. C. Lee and Y. Chiu, “Digital calibration of nonlinear memory errors in sigma - Delta modulators,” IEEE Trans. Circuits Syst. I Regul. Pap., vol. 57, no. 9, pp. 2462–2475, 2010. S. C. Lee, B. Elies, and Y. Chiu, “An 85dB SFDR 67dB SNDR 8OSR 240MS/s ΣΔ ADC with nonlinear memory error calibration,” in IEEE Symposium on VLSI Circuits, Digest of Technical Papers, 2012, pp. 164–165. A. Bafandeh and M. Yavari, “Digital Calibration of Amplifier Finite DC Gain and Gain Bandwidth in MASH ΣΔ Modulators,” IEEE Trans. Circuits Syst. II Express Briefs, vol. 63, no. 4, pp. 321–325, 2016.
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