Digital Design Using VHDL

A Training Manual On

Digital Design Using VHDL

Krishna Prasad Gnawali IOE, Thapathali Campus March 2016

1

Introduction

Design Engineer need to translate the system specification into circuit description, this can be achieved using schematic capture tools like Proteus or by describing the design using textual form much like software program. Textual descriptions of digital hardware can be written in programming language such as C, or in a hardware description language (HDL). Hardware description language (HDL) is a specialized computer language used to program the structure, design and operation of electronic circuits, and most commonly, digital logic circuits. Two HDLs are in common use today: Verilog and VHDL (VHSIC Hardware Description Language), where VHSIC stands for Very High Speed Integrated Circuit. HDLs such as VHDL and Verilog were developed to support the underlying characteristics of hardware • Connections of parts • Concurrent operations • Concept of propagation delay and timing These characteristics cannot be captured by traditional programming languages. VHDL is a rich and strongly typed language, deterministic and more verbose than Verilog. As a result, designs written in VHDL are considered self-documenting. Its syntax is non-C-like and engineers working in VHDL need to do extra coding to convert from one data type to another. VHDL often catches errors missed by Verilog. VHDL emphasizes unambiguous semantics and allows portability between tools. Although Verilog is easy to learn, we set our objective to VHDL. Developed by US, Department of Defense (DOD) between 1970 and 80s, it was officially standardized as IEEE 1076 in 1987. VHDL is designed to fill a number of needs in the design process. Firstly, it allows description of the structure of a design that is how it is decomposed into sub-designs, and how those sub-designs are interconnected. Secondly, it allows the specification of the function of designs using familiar programming language forms. Thirdly, as a result, it allows a design to be simulated before being manufactured, so that designers can quickly compare alternatives and test for correctness without the delay and expense of hardware prototyping.

1.1

Levels of Representation and Abstraction

VHDL representation can be seen as text file describing a digital system. The digital system can be represented in different forms such as a behavioral model or a structural model. Most commonly known as levels of abstraction, these levels help the designer to develop complex systems efficiently.

Figure 1-1. Levels of abstraction: Behavioral, Structural and Physical

1.1.1 Behavioral Model Behavioral level describes the system the way it behaves (function of the system) instead of a lower abstraction of its connections. Behavioral model describes the relationship between the input and output signals. The description can be a Register Transfer Level (RTL) or Algorithmic (set of instruction) or simple Boolean equations. Register Transfer Level (RTL) typically represents data flow within the systems like data flow between registers. RTL is mostly used for design of combinational logics. Algorithmic Level In this method, specific instruction set of statements define the sequence of operations in the system. Algorithmic level is mostly used for design of sequential logics.

1.1.2 Structural Model Structural level describes the systems as gates or component block interconnected to perform the desired operations. Structural level is primarily the graphical representation of the digital system and so it is closer to the actual physical representation of the system. It can be compared to schematic of interconnected logic gates. A formal VHDL structural description is done using the concept of ’component’ which is first declared (make known) and then instantiated (used). Figure below shows the example of structural representation of door, belt and ignition monitoring system employed in vehicle.

Figure 1-2 Structural representation of buzzer circuit 1.2

Basic Language Construct of VHDL

VHDL description of a system consists of primary design units and secondary units. The primary design units are Entity and Package. Architecture and Package body represent the secondary design units. Libraries are collections of primary and secondary design units. A typical design usually contains one or more libraries of design units.

1.2.1 Entity Entity can be seen as the black box view of the system. We define the inputs and outputs of the system which we need to interface. For the system below, entity is defined as ENTITY mux IS PORT( ip1, ip2 : IN STD_LOGIC; Sel : IN STD_LOGIC; OUT: STD_LOGIC);

END mux; In the descriptions shown throughout the book, keywords of the language and types provided with the STANDARD package are shown in ALL CAPITAL letters. For instance, in the example, the keywords are ENTITY, IS, PORT, IN, INOUT, and so on. Names of user-created objects such as mux, in the example above is shown in lower case.

An entity always starts with the keyword ENTITY, followed by its name and the keyword IS. Next are the port declarations using the keyword PORT. An entity declaration always ends with the keyword END, optionally [] followed by the name of the entity. 

The NAME_OF_ENTITY is a user-selected identifier



Signal names consists of a comma separated list of one or more user-selected identifiers that specify external interface signals.



IN ,OUT specifies the mode in which pin operate and they may of the form o IN – indicates that the signal is an input o OUT – indicates that the signal is an output of the entity whose value can only be read by other entities that use it. o INOUT – the signal can be an input or an output.



type: a built-in or user-defined signal type. Examples of types are BIT, BIT_VECTOR, BOOLEAN, CHARACTER, STD_LOGIC, and STD_ULOGIC. o BIT– can have the value 0 and 1 o BIT_VECTOR – is a vector of bit values (e.g. BIT_VECTOR (0 to 7) o STD_LOGIC o

STD_ULOGIC

o STD_LOGIC_VECTOR o STD_ULOGIC_VECTOR: can have 9 values to indicate the value and strength of a signal. STD_ULOGIC and STD_LOGIC are preferred over the BIT, BIT_VECTOR types. BOOLEAN – can have the value TRUE and FALSE INTEGER – can have a range of integer values REAL – can have a range of real values CHARACTER – any printing character

TIME – to indicate time 

GENERIC: generic declarations are optional and determine the local constants used for timing and sizing (e.g. bus widths) the entity. A generic can have a default value. The syntax for a generic follows,

GENERIC ( constant_name: TYPE [:=value] ; constant_name: TYPE [:=value] ; :

constant_name: TYPE [:=value] );

Format for declaring entity ENTITY entity_name IS GENERIC(constant_name: TYPE [:=value] ; : : Constant_name: TYPE[:= value] ); PORT(port list); END entity_name;

For the example of Figure 1-2 above, the entity declaration looks as follows.

--ENTITY DECLARATION ENTITY buzzer IS PORT( door, ignition, sbelt: IN STD_LOGIC; Warning: OUT STD_LOGIC); END buzzer;

NOTE: comments in VHDL program starts with -- and VHDL identifier are not case sensitive.

1.2.2 Architecture Body The architecture body specifies how the circuit operates and how it is implemented. As discussed earlier, an entity or circuit can be specified in a variety of ways, such as behavioral, structural (interconnected components), or a combination of the above so there can be multiple form of architecture body of the same entity.

The architecture body looks as follows,

ARCHITECTURE architecture_name OF NAME_OF_ENTITY IS -- Declarations -- components declarations -- signal declarations -- constant declarations -- function declarations -- procedure declarations -- type declarations BEGIN -- Statements --Body statements

END architecture_name;

The following program described how entity and architecture body are combined to build a complete VHDL program.

-- this is comment, comment in VHDL starts with --- this the complete VHDL programme of the circuit shown in figure1-2 -- following two line of code includes the library

LIBRARY IEEE; USE IEEE. STD_LOGIC_1164.ALL;

-- Entity declaration -----------------------------------------------------------------------------------ENTITY buzzer IS PORT(door, ignition, sbelt : IN STD_LOGIC; Warning: OUT STD_LOGIC ); END buzzer; ------------------------------------------------------------------------------------

-- ARCHITECTURE DECLARATION ARCHITECTURE behavioral OF buzzer IS --SIGNAL DECLARATION SIGNAL w1, w2: STD_LOGIC; BEGIN w1 w2, F2=> op);

);

END structure; Inertial Delay and Transport Delay We can delay a signal assignment by, say, 4 ns, using the following construct in VHDL: z A(4), B => B(4), Cin => carry(4), S=> S(4), Cout => carry(5)); F6: Full_adder_1_bit port map(A => A(5), B => B(5), Cin => carry(5), S=> S(5), Cout => carry(6)); F7: Full_adder_1_bit port map(A => A(6), B => B(6), Cin => carry(6),

S=> S(6), COUT =>CARRY(7)); F8: Full_adder_1_bit port map(A => A(7),

B=> B(7), CIN => CARRY(7), S=> S(7), Cout => cout); end Behavioral; Carry Look Ahead Adder(CLA)- Fast Adder library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity CLA_4_bit is Port(A,B :In std_logic_vector(3 downto 0); Cin: in std_logic; carry: out std_logic; sum: out std_logic_vector(3 downto 0)); end CLA_4_bit;

architecture Behavioral of CLA_4_bit is Signal G,P: std_logic_vector(3 downto 0); signal C: std_logic_vector(3 downto 0); begin

G(0)