Digital frequency tripling circuit for third harmonic detection by lock-in ...

Digital frequency tripling circuit for third harmonic detection by lock-in amplifiers Seung-Min

Lee and Sook-ll Kwun

Department of Physics, Seoul National University, Seoul 151-742, Korea

(Received 5 October 1993; accepted for publication

17 December 1993)

A new digital circuit for fast and stable frequency tripling was constructed. The frequency tripler covers the input frequency range from 0.1 Hz up to 5 kHz with a maximum phase shift less than 1 deg at the highest frequency. The tripler generates a stable signal synchronized to the input after just one input period. Since the circuit design is flexible, input frequency range and phase accuracy can be improved using faster integrated circuits.

I. INTRODUCTION

There have been many developments in measurement methods for heat capacity and thermal conductivity by third harmonic modulation techniques, often called the 3w technique.’ Recent progress includes specific heat spectroscopy,2’3 the ac hot wire method,4 and the 3w method.’ Third harmonic response exists also in nonlinear systems and useful information about the systems can be obtained by measuring the response.6 Since the third harmonic signals are measured by lock-in amplifiers, a frequency tripling device is essential in those methods. Usually frequency triplers have been constructed with a phase locked loop (PLL) which consists of a voltage controlled oscillator (VCO), a phase sensitive detector (PSD), and low pass filters.57 However, frequency triplers of this type have at least four major deficiencies. First, circuits for low pass filters and oscillators often do not work well over the designed frequency range. Second, since these circuits are essentially analog devices, poor noise immunity may cause a serious problem. Third, due to the low pass filters in the feedback loop, it takes quite a long time to stabilize the 30 reference at low frequencies after a frequency change. Another crucial deficiency of the circuit is that a wide frequency range cannot be covered with a single frequency tripler and sometimes two or more triplers are used together with command lines to switch them.3 In this work, to remove all the above problems, we have constructed a digital circuit for frequency tripling. The digital tripler works over four decades of input frequency ranging from 0.1 Hz to 5 kHz. We can obtain a stabilized 3w reference signal after just one input period. The phase fluctuation of the output signal is less than 1 deg at the highest frequency of the range and gets smaller for lower frequency.

that it counts Ti/6to pulses during the period Ti. On the other hand, another counter (counter “B”) counts pulses of period to and it takes TJ6toX to= T/6 to count the same number of pulses as counter “A”. Thus by producing a pulse each time the counting of counter B reaches Ti/6to we can generate pulses of period TJ6. Finally these pulses are sent to a flip-flop and we obtain a symmetric square wave of period TJ3 at the output of the flip-flop. Since a reference signal of a symmetric wave form gives better results in most lock-in detection, pulses of period 6ro are used instead of pulses of period 3to. The most important thing is that the output should be synchronized to the reference input. We accomplish it by generating short reset pulses at each rising edge of the input. The pulses reset the flip-flop at the output stage to be high. They also reset counter B in the oscillator circuit to restart the counting cycle. This digital logic has good noise immunity and works as designed. But there is an inevitable imperfection. Since the input period Ti is not an exact multiple of 6to, there can be a truncation time error. The maximum error is 6to and it causes phase lags or leads by 360X 6tdTi deg. Hence the maximum phase fluctuation in degrees is approximately 2000toX f where f is the input frequency. When to= 10u7 s, for example, the phase fluctuation is at most 1 deg for the 5 kHz input and becomes smaller at lower frequencies. The phase error can be reduced if we use a clock with frequency higher than 10 MHz and counters of larger capacity. On the other hand, when one uses a stand-alone lock-in amplifier, the forced synchronization at each input rise reduces the phase error, since the built-in PLL circuit of the lock-in amplifier averages out the phase fluctuation. HI. CIRCUIT

II. PRINCIPLE

OF DIGITAL

FREQUENCY

TRIPLING

Figure 1 is a block diagram of the digital frequency tripler, and the principle of frequency tripling is as follows. Let T, be the period of input signal whose frequency is ,f. A crystal oscillator generates pulses of period to and a divide-by-six circuit produces pulses of period 6to. A digital counter (counter “A”) counts pulses of period 6t, so

DESCRIPTION

Figure 2 shows the circuit diagram of the digital frequency tripler. With this circuit we could obtain a frequency-tripled signal for the input frequency range between 0.1 Hz and 5 kHz. Two 24 bit counters, “A” and “B”, consist of a high-speed complementary metal-oxide semiconductor (CMOS) counter integrated circuit (IC) (74HC4040) and can count up to 224-107. Counter A

Redistribution subject to AIP copyright, seeAmerican http://ojps.aip.org/rsio/rsicpyrts.html. Rev. Sci.Downloaded Instrum. 65 01 (4),Nov April2000 1994to 147.46.25.86. 0034.6?46/94/65(4)/971/3/$6.00 @ 1994 Institute of Physics 971

FIG. 1. Block diagram of digital frequency tripler.

counts pulses from a 10.000 000/6 MHz source and the counts of counter A is sent to a 24 bit register (three 74LS573’s). Counter B counts pulses from a 10.000 000 MHz clock and a 24 bit comparator (three 74LS688’s) flips a flip-flop (74LS74) whenever the counts of counter B reaches that of the register. The reset pulses and latch pulses shown in Fig. 1 are generated by a flip-flop combined with a NAND gate IC( CMOS 40 11) . The pulse width is about 50 ns which is the typical delay time of CMOS IC’S.~ In Fig. 3 the frequency tripling procedure is visualized by the wave form at

the marked test points. The synchronization pulse (TP2) resets the output flip-flop to high at the rising edge of the input signal (TPl ). This procedure provides the synchronization of the output oscillation to the input. The reset pulse at TP4 resets counter A and the latch pulse (TP5) forces the register to duplicate the content of counter A. The time interval T, between these two pulses is equal to the period of the input signal. The pulse at TP6 is from a 24 bit comparator. It flips the output flip-flop and restarts the counting cycle of counter B. The synchronization procedure also requires a restart of counter B so that the

-_-_. . --

??‘IG. 2. Circuit description of digital frequency tripler. A CMOS 4011 produces a time delay of about 50 74HC4040 for counters.

ns.

Note the use of high-speed CMOS

Frequency Rev. Sci. Instrum., Vol. 65, No. 4, April 1994 972 Downloaded 01 Nov 2000 to 147.46.25.86. Redistribution subject to AIP copyright, see http://ojps.aip.org/rsio/rsicpyrts.html.

tripling1

I TPI

1;I I

WAVE FORMS AT THE TEST POINTS 1

I

I

,

I

I I

TP2 I

I

TP3 TP4 TP5

TP6

I I I I I

I I I I

TP8

I I I

TA

I I I

;

-+-+

TB

----A I I I

/innnnnnnnnnnbnnnnnh I I nnnnnnnnnn!nnnnnn I I

TP7

I I I I II+-

I

I

I

I

I

I I I I

I I I I I

I

I

I

BIG. 3. Timing diagram of the signal at each test point. Exaggerated time lags indicate the typical propagation delay of a TTL IC, 10 ns. T,, denotes the time interval for which counter A counts pulses from IO/6 MHz line. Ta is the time spent by counter B to count the 10 MHz clock pulses. Bold lines of the wave form at TP7 indicate the forced synchronization by the reset pulses of TP2.

signals at TP2 and TP6 are superposed to generate the reset signal at TP7. A flip-flop between TP2 and TP3 helps us to use both symmetric and asymmetric input signals. IV. REMARKS

The frequency tripler circuit of Fig. 2 can be optimized further for better performance. First, one can increase the highest input frequency by using faster clocks, with a frequency higher than 10 MHz. However, the maximum frequency will be limited by the speed of all other logic IC’S.~ On the other hand, more counters as well as more comparators and registers are required to cover a lower frequency region. Second, if the input signal is symmetric, symmetrization at the input stage is not required so that we can halve the phase fluctuation by using pulses of period tJ3 with some modifications of the synchronization and latch circuit. Finally, by changing the electric connection of the up/down counter (74LS193), one can use this circuit as a frequency multiplier of a different multiplication factor.

ACKNOWLEDGMENTS

This work was supported by the Basic Science Research Institute Program, Ministry of Education, Republic of Korea and the Korea Science and Engineering Foundation (KOSEF) through the Science Research Center (SRC) of Excellence Program. We thank Professor I. Yu of Seoul National University for reading this manuscript and helpful comments.

‘0. M. Corbino, Physik Z. 11,413 (1910); L. R. Holland, J. Appl. Phys. 34, 2350 (1963); R. C. Smith, i&d. 37, 4528 (1966); Ya. Y. Kraftmakher, Soviet Phys-Solid State 6, 369 [ 1964). ‘N. 0. Birge and S. R. Nagel, Rev. Sci. Instrum. 58, 1464 (1987). 3D. H. Jung, T. W. Kwon, D. J. Bae, I. K. Moon, and Y. H. Jeong, Meas. Sci. Technol. 3, 475 (1992). ‘N. 0. Birge, Phys. Rev. B 34, 1631 (1986). 5D- G. Cahill, Rev. Sci. Instrum. 61, 802 (1990). 6J. H. Classen, M. E. Reeves, and R. J. Soulen, Jr., Rev. Sci. Instrum. 62, 996 (1991). ‘P. Horowitz and W. Hill, The Art of Electronics, 2nd ed. (Cambridge University, Cambridge, 1989), pp. 569 and 647.

Rev. Sci.Downloaded Instrum., Vol. 65, No. 4, April 1994 Frequency tripling 973 01 Nov 2000 to 147.46.25.86. Redistribution subject to AIP copyright, see http://ojps.aip.org/rsio/rsicpyrts.html.