Digital RF Processor Techniques for Single-Chip ... - Semantic Scholar

IEEE 2006 Custom Intergrated Circuits Conference (CICC)

Digital RF Processor Techniques for Single-Chip Radios (Invited) Robert Bogdan Staszewski, Khurram Muhammad and Dirk Leipold Texas Instruments, Dallas, TX 75243, USA Abstract— RF circuits for multi-GHz frequencies have recently migrated to low-cost digital deep-submicron CMOS processes. Unfortunately, this process environment, which is optimized only for digital logic and SRAM memory, is extremely unfriendly for conventional analog and RF designs. We present fundamental techniques recently developed that transform the RF and analog circuit design complexity to digital domain for a wireless RF transceiver, so that it enjoys the benefits of digital approach, such as process node scaling and design automation. All-digital phase locked loop, all-digital control of phase and amplitude of a polar transmitter, and direct RF sampling techniques allow great flexibility in reconfigurable radio design. Digital signal processing concepts are used to help relieve analog design complexity, allowing one to reduce cost and power consumption in a reconfigurable design environment. VHDL hardware description language is universally used throughout this SoC. The ideas presented have been used in Texas Instruments to develop two generations of commercial digital RF processors: a single-chip Bluetooth radio and a single-chip GSM radio.

In the deep-submicron process, with its low supply voltage (at and below 1.5 V), relatively high threshold voltage (0.6 V and often higher due to the MOSFET body effect), the available voltage headroom is quite small for any sophisticated analog functions. Moreover, considerable switching noise of substantial digital circuitry around makes it harder to resolve signals in the voltage domain. On the positive side, the switching characteristics of a MOS transistor, with rise and fall times on the order of tens of picoseconds, offer excellent timing accuracy at high frequencies, and the fine lithography offers precise control of capacitor ratios. Hence, we exploit this new paradigm by leveraging on these advantages while avoiding the weaknesses. Xtal

In a deep-submicron CMOS process, time-domain resolution of a digital signal edge transition is superior to voltage resolution of analog signals.

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SRAM

Amplitude modulation

Σ∆

FREF

Design flow and circuit techniques of contemporary transceivers for multi-GHz mobile RF wireless applications are typically analog intensive and utilize process technologies that are incompatible with a digital baseband (DBB) and application processor (AP). The mobile industry continues to thrive by providing support for Bluetooth personal area networking, positioning technology based on GPS, and wireless LAN for high-speed local-area data access. Sophisticated applications, such as MP3 audio playback, camera functions, MPEG video and digital TV further entice a new wave of handset replacements. Such application support dictates high level of memory integration [1] together with large digital signal processing horse-power and information flow management, all requiring sophisticated DSP and microprocessor cores. Nowadays, the DBB and AP designs constantly migrate to the most advanced deep-submicron digital CMOS process available, which usually does not offer any analog extensions and has very limited voltage headroom [2]. Our primary approach to reduce the cost and power consumption of the complete mobile handset solutions is through integration of the conventional RF functions with the DBB and AP. Given the task of designing highly integrated RF circuits in the digital deep-submicron process environment, we have realized that we are facing a new paradigm [3]:

Digital Baseband Processor

DCXO

I. I NTRODUCTION

Front-end Module

DPA Σ∆ Digital logic

DCO TDC

LO clock

TX RX Digital logic

A/D

Power Management (PM)

Discrete time

LNTA Current sampler

RF in

RF Built-in Self Test (RFBIST)

Battery Management VBAT

Fig. 1. Single-chip radio with an all-digital transmitter and a discrete-time receiver.

In this paper, we describe key ideas used to develop two generations of a Digital RF Processor (DRPTM ): single-chip Bluetooth [4] [5] [6] and GSM/EDGE [7] [8] radios realized in 130-nm and 90-nm digital CMOS process technologies, respectively. Fig. 1 highlights the common radio architecture. The all-digital phase-locked loop (ADPLL)-based transmitter

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employs a polar architecture with all-digital phase/frequency and amplitude modulation paths. The receiver employs a discrete-time architecture in which the RF signal is directly sampled and processed using analog and digital signal processing techniques. A digitally-controlled crystal oscillator (DCXO) generates a high-quality basestation-synchronized frequency reference. The transceiver is integrated with the DBB, SRAM memory, power management and RF builtin self-test (RFBIST) in a complete system-on-chip (SoC) solution.

a time-to-digital converter (TDC). All inputs and outputs are digital even at multi-GHz frequency — the 40-ps rise time makes almost a perfect square wave. The full digital control of the RF frequency allows digital implementation of the phase locked loop. CKV

FREF

II. A LL -D IGITAL PLL

FREF

(fR)

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VCO Loop Filter

UP

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Pseudo-Thermometer-Code Edge Decoder

Charge Pump

Phase/ Frequency Detector

DOWN

(a)

DCO period normalization multiplier

(fV)

Tuning voltage

Fractional part of variable phase

Frequency Divider

(a)

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(b) FREF

FCW

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Reference phase Phase error Loop

(fR)

Filter TDC

(b)

Σ∆

∆tinv

CKV

DCO Tune

∆t r

TV

CKV

(fV)

Fig. 3. Time-to-digital converter (TDC): (a) structure; (b) quantization of the timing difference between the DCO and FREF edges. The integer counter of DCO edges is not shown.

Variable phase

Fig. 2. RF frequency synthesizers: (a) conventional charge-pump PLL; (b) all-digital phase-domain PLL based on TDC and DCO. F CW ≡ N is a fractional frequency division ratio.

RF frequency synthesizer is a key block used for both up-conversion and down-conversion of radio signals. It has been traditionally based on a charge-pump PLL, shown in Fig. 2(a), which is not easily amenable to scaled CMOS integration and suffers from high level of reference spurs generated by the correlative phase detection method. Recently, a digitally-controlled oscillator (DCO), which deliberately avoids any analog tuning voltage controls, was proposed and demonstrated in [9] for RF wireless applications. This allows for its loop control circuitry to be implemented in a fully digital manner as first proposed in [10] and then demonstrated as novel phase-domain all-digital PLL (ADPLL), as shown in Fig. 2(b), in commercial single-chip Bluetooth [4] and GSM [7] radios. The ADPLL architecture is built from the ground up using digital techniques that exploit the high speed and high density of the advanced CMOS, while avoiding problems related to voltage headroom. The ADPLL replaces the conventional RF synthesizer architecture, based on a voltage-controlled oscillator and a phase/frequency detector and charge-pump combination, with a digitally controlled oscillator (DCO) and

Since the conventional phase/frequency detector and charge pump are replaced by the TDC, the phase-domain operation does not fundamentally generate any reference spurs thus allowing for the digital loop filter to be set at an optimal performance point between the reference phase noise and oscillator phase noise. Integer part of the variable phase is determined by counting the number of rising clock transitions of the DCO oscillator clock CKV. The TDC core measures and quantizes the time differences between the FREF and DCO edges (see Fig. 3(b)), i.e., the fractional part of the variable phase. The variable phase is subtracted from the reference phase (accumulated FCW) by the digital phase detector. The phase error samples are then scaled and filtered to be used as the DCO tuning word. The DCO tuning capacitance is split into a large number of tiny capacitors that are selected digitally. The advanced lithography allows creation of extremely fine variable capacitors (varactors) – about 40 attofarads of capacitance per step, which equates to the control of only 250 electrons entering or leaving the resonating LC tank. Despite the small capacitance step, the resulting frequency step at the 2 GHz RF output is 10–20 kHz, which is too coarse for wireless applications. Thus, the fast switching capability of the transistors is utilized by performing high-speed 225–900 MHz Σ∆ dithering of the 250 electrons in the finest varactors. The duty cycle of the high/low capacitive states establishes the time-averaged res-

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onating frequency resolution, now better than 1 kHz. The finest varactors are realized as n-poly/n-well MOSCAP devices. III. A LL -D IGITAL T RANSMITTER data

Complex pulse shaping filter

Amplitude Control Word (ACW)

Data FCW Channel FCW

FREF

FCW

Σ

Reference phase Phase error Loop

A. Receiver Architecture

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(fV)

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IV. D ISCRETE -T IME R ECEIVER

Filter

(fR) TDC

DPA

Variable phase

Fig. 4.

CKV

ADPLL-based polar transmitter.

An RF transmitter that is well-suited for a deep-submicron CMOS implementation is shown in Figure 4. It performs the quadrature modulation in polar domain [4] [7]. The transmitter architecture is fully digital and takes advantage of the wideband frequency modulation capability of the all-digital PLL by adjusting its digital frequency command word. The modulation method is an exact digital two-point scheme, with one feed directly modulating the DCO frequency deviation while the other is compensating for the developed excess phase error. The DCO gain characteristics are constantly calibrated through digital logic to provide the lowest possible distortion of the transmitted waveform [11]. from LDO

Controllable switch array

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Matching network

Fig. 5.

controlled digitally and establishes the instantaneous amplitude of the output RF envelope. Fine amplitude resolution is achieved through high-speed Σ∆ transistor switch dithering. Despite the high speed of digital logic operation, the overall power consumption of the transmitter architecture is lower than that of architectures to date.

Digitally controlled PA.

The digitally controlled power amplifier (DPA) circuit, shown in Fig. 5, which acts as a digital-to-RF-amplitude converter (DRAC) [12] is used for the power ramp as well as amplitude modulation. The DPA operates as a near-class-E RF power amplifier and is driven by the square wave output of the DCO. The large number of core NMOS transistors are used as on/off switches and are followed by a matching network that interfaces with an antenna. The number of active switches is

The receiver architecture shown in Fig. 6 [8] uses direct RF sampling [4] [6] [13] [14] in the receiver front-end path. In the past, only subsampling mixer receiver architectures have been demonstrated: They operate at lower IF frequencies [15], [16] and suffer from noise folding and exhibit susceptibility to clock jitter. A recent reference [17] uses a high sampling frequency of 480 MHz after the mixer but adds an RC filtering stage. In this architecture, discrete-time analog signal processing is used to sample the RF input signal at Nyquist rate of the carrier frequency as it is then down-converted, down-sampled, filtered and converted from analog to digital with a discrete-time Σ∆ ADC. This method achieves great selectivity right at the mixer level. The selectivity is digitally controlled by the local oscillator (LO) clock frequency and capacitance ratios, both of which are extremely well controlled and precise in deep-submicron CMOS processes. The discretetime filtering at each signal processing stage is followed by successive decimation. The main philosophy in architecting the receive path is to provide all the filtering required by the standard as early as possible using a structure that is quite amenable to migration to the more advanced deepsubmicron processes. This approach significantly relaxes the design requirements for the following baseband amplifiers. Following the low noise amplifier (LNA), the signal is converted to current using a transconductance amplifier (TA) stage and down-converted to a programmable low-IF frequency by integrating on a sampling capacitor. After initial decimation through a sinc filter response, a series of IIR filtering follows RF sampling for close-in interferer rejection. These signal processing operations are performed in the multi-tap direct sampling mixer (MTDSM) that receives its clocks from the digital control unit (DCU). A Σ∆ ADC containing a front-end gain stage follows. A feedback control unit (FCU) provides a single-bit feedback to the MTDSM to establish the common mode voltage for the MTDSM while canceling out differential offsets. The output of the I/Q ADCs are passed on to digital receive (DRX) chain. The first rate change filter (RCF1) provides anti-aliasing and decimation filtering to reduce the clock rate by 16. Pre-filtering (PREF) is then performed to assist digital resampling (RES) operation. The residual dc offset that could not be corrected by the FCU is corrected by DIGOC. The resampler follows and converts the sample rate from LO dependent clock rate to a fixed output rate of 8.66 Msps. Next, the sample rate is decimated by a second rate change filter to the following I/Q mismatch block. The IF frequency is then converted from the low-IF to dc by the

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1.0833 Msps CHANNEL SELECT FILTER

RATE CHANGE FILTER 2

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6.72~7.82 Msps

RATE CHANGE FILTER 1

I/Q MISMATCH COMPENS.

ZERO IF

AVSS

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RESAMPLE

CHANNEL SELECT FILTER

RATE CHANGE FILTER 2

MTDSM

Fig. 6.

Block diagram of the receiver.

ZERO IF block. The final filtering is performed using a fully programmable 64-tap channel select FIR filter. One significance of this work is in demonstrating the feasibility of obtaining low noise figure in a receive chain in the presence of more than a million digital gates. Another significance is the development of very low-area, simple and highly programmable analog blocks that are controlled by software to guarantee best achievable performance. A third significance is the architecture of analog structures that are amenable to migration from one process node to the next without significant re-work. The approach used is to use signal processing to reduce analog area and complexity. The radio solution was targeted to meet quad-band GSM specification in addition to supporting several experimental modes of operation. B. Direct Sampling Mixer with IIR Filtering gm

gm

iRF

iRF

N LOA

LO

LOA

LOB

LOB

Cs

(a)

Cs

mechanism to prevent the charge overflow is needed. Both of these operations are accomplished by fixing the integration window length followed by charge readout phase that will also discharge the sampling capacitor such that the next period of integration would start from the same zero condition. The RF sampling and readout operations are cyclically rotated on both Cs capacitors as shown in Fig. 7(b). When LOA rectifies N RF cycles that are being integrated on the first sampling capacitor, LOB is off and the second sampling capacitor charge is being read out. On the following N RF cycles the operation is reversed. This way, the charge integration and readout occur at the same time and no RF cycles are missed. The sampling capacitor integrates the half-rectified RF current over N cycles. The charge accumulated on the sampling capacitor and the resulting voltage (V = Q/Cs ) increases with the integration window, thus giving rise to a discrete signal processing gain of N . The temporal integration of N halfrectified RF samples performs a finite-impulse response (FIR) operation with N all-one coefficients, also knownPas movingN −1 average (MA), according to the equation: wi = l=0 ui−l , where ui is the ith RF sample of the input charge sample, wi is the accumulated charge. Its frequency response is a sinc function.

Cs

i RF

(b)

Fig. 7. Temporal MA operation at RF rate: (a) with a single sampling capacitor; (b) with a cyclic charge readout.

The basic idea of the current-mode direct sampling mixer [6] [13] is illustrated in Fig. 7(a). The low-noise transconductance amplifier (LNTA = LNA + TA) converts the received RF voltage vRF into iRF in current domain through the transconductance gain gm . The current iRF gets switched by the halfcycle of the LO and integrated into the sampling capacitor Cs . If the LO oscillating at f0 frequency is synchronous and in phase with the sinusoidal RF waveform, the voltage gain of a single RF half-cycle is Gv,RF = π1 · f10 · gCms , and the accumulated charge on the sampling capacitor is Gq,RF = 1 1 1 π · f0 · gm . In the above equations, the π factor is contributed by the half-cycle sinusoidal integration. Continuously accumulating the charge as shown in Fig. 7(a) is not very practical if it cannot be read out. In addition, a

N

gm

LO

LO SA

SA

SAZ

SAZ

CH = a1Cs

Fig. 8.

CR = CR = (1-a1)Cs (1-a1)Cs

IIR operation with cyclic charge readout.

Fig. 7(b) is now modified to include recursive operation that gives rise to the IIR filtering capability, which is generally considered stronger than that of FIR. A “history” sampling capacitor CH is added in Fig. 8. The integration operation is

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continually performed on the “history” capacitor CH = a1 Cs and one of the two rotating “charge-and-readout” capacitors CR = (1 − a1 )Cs such that the total RF integrating capacitance, as seen by the LNTA, is always CH + CR = Cs . When one of the CR capacitors is being used for readout, the other is being used for RF integration. The IIR filtering capability comes into play in the following way: The RF current is being integrated over N RF cycles, as described before. This time, the charge is being shared on both CH and CR capacitors proportionately to their capacitance values. At the end of the accumulation cycle, the active CR capacitor, that stores (1 − a1 ) of the total charge, stops further accumulating in preparation for charge readout. The other rotating capacitor joins the CH capacitor in the RF sampling 1−a1 = 1 − a1 of process and, at the same time, obtains a1 +(1−a 1) the total remaining charge in the “history” capacitor, provided it has no initial charge at the time of commutation. Thus the system retains a1 portion of the total system charge of the previous cycle. If the input charge accumulated over the most-recent N RF samples is wj then the charge sj stored in the system at sampling time j, where i = N · j, (as stated earlier, i is the RF cycle index) could be described as a single-pole recursive IIR equation: sj = a1 sj−1 + wj (1) xj = (1 − a1 )sj−1 a1 =

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CH + CR 1 = 1 − a1 CR

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Since there is no sampling time expansion for the IIR operation, the discrete signal processing charge gain Gq,iir1 is one. In other words, due to the charge conservation principle, the input charge per sample interval is on average the same as the output charge. For the voltage gain, however, there is an impedance transformation of Cinput = Cs and Coutput = (1 − a1 )Cs , thus resulting in a gain: Gv,iir1 =

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The output charge xj is (1 − a1 ) of the system charge in the most-recent cycle. This discrete-time IIR filter operates at f0 /N sampling rate and introduces a single pole with the frequency attenuation of 20 dB/dec. The equivalent pole location in the continuous-time domain for fc1 ≪ f0 /N is 1 f0 CR 1 f0 · (1 − a1 ) = · = 2π N 2π N CH + CR

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that is greater than unity. V. S ILICON R EALIZATION Fig. 9 shows two chip micrographs representing the first and second generation of digital RF processor (DRP), respectively: commercial single-chip Bluetooth radio in 130 nm CMOS, and commercial single-chip GSM radio in 90 nm CMOS. The GSM SoC consists of the digital baseband with digital logic and SRAM memory on the left part, and the DRP that

Fig. 9. Die micrographs of the commercial single-chip SoC’s employing two generations of DRP: (top) first generation – Bluetooth; (bottom) second generation – GSM.

integrates memory, digital logic, analog and RF, on the right part. The 90 nm process is characterized by the following parameters: 0.27 µm minimum metal pitch, five levels of copper metal, 1.2 V nominal transistor voltage, 2.6 nm gate oxide thickness, logic gate density of 250 kgates/mm2 , SRAM cell density of 1.0 Mb/mm2 . Closer examination of the devices reveals easily discernable RF inductors and other large analog elements that occupy silicon area equivalent to tens or even hundreds of thousands of digital gates. Consequently, to be cost effective, the number of classical RF components shall be minimized with architectural and circuit design choices. The measured RX sensitivity of -82 dBm for Bluetooth and -110 dBm for GSM, versus the respective specifications of 70 dBm and -102 dBm, is among the best in class. The overall GSM RX noise figure is only 2 dB.

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A. VHDL TX Simulations DCO output clock: f0=915.000076 MHz −80 −90

Upconverted flicker noise

−100 Phase noise [dBc/Hz]

With the first demonstrations of a fully-digital frequency synthesizer and transmitter, and a digitally-intensive receiver for wireless applications, a need has arisen to model and simulate RF circuits using the same simulation engine as that used for the digital back-end, which nowadays is likely to contain over a million gates. This way, complex interactions and performance of the entire SoC could be validated and verified prior to tape-out. Fig. 1 offers some examples of these complex interactions: 1) Effect of the TDC resolution and nonlinearity on the close-in PLL phase noise performance and generated spurs. 2) Effect of the DCO phase noise on the PLL phase noise performance and generated spurs, especially when the PLL contains a higher-order digital loop filter and operates in fractional-N mode. 3) Effect of the DCO frequency resolution on the close-in phase noise of the PLL. 4) Effect of the Σ∆ DCO dithering on the far-out phase noise. 5) Effect of the DCO varactor mismatches on the modulated spectrum. 6) Effect of the DPA resolution and nonlinearity on the RF output spectrum. 7) Effect of the DCO phase noise on the degradation of the signal-to-noise ratio in the direct RF sampling receiver. 8) Effect of the mixer capacitor mismatches on the receiver performance. 9) Operation of the common and differential mode feedback loops [14] in the receiver. While SPICE-based simulation tools are extremely useful for small RF circuits containing several components (such as an RF oscillator or an LNA), their long simulation times prevent from investigating larger circuits (such as an RF oscillator with a PLL loop and a transmitter or a receiver). In fact, using the presented techniques, we were able to determine that the entire transceiver (with 100’s of 1000’s of gates) meets the RF GSM and EDGE specifications prior to tapeout. This level of validation seems to be nowadays a requirement given over a million dollar price tag for the reticle set in the 90 nm CMOS process. The behavioral modeling and simulation environment is based on a standard event-driven single-core simulator, e.g., VHDL. This environment [18] is well suited for digitallyintensive SoC solutions with a fair amount of analog/RF circuitry. The main advantage of the single simulation engine at the top level is that it allows seamless integration of all hardware abstraction levels (such as behavioral, RTL, gate level) in a uniform environment. The single most important feature of the standard VHDL hardware description language, which makes it far superior to Verilog for mixed-signal designs, is its support of real or floating-point type signals. Extensive simulation and synthesis support by the standard VHDL language makes it possible for a complex communication system to

achieve “build what we simulate, and simulate what we build” goal. Simulator performance, stability, multi-vendor support, mature standard and widespread use are all advantages of this environment. The RF/analog circuit behavior is modeled in VHDL using real-valued signals. The rest of the RF transceiver is synthesizable from RTL subset of VHDL, auto-placed and autorouted. A portion of the digital logic operates at the multiGHz clock carrier frequency. The use of VHDL allows for a tight and seamless integration of RF with the digital logic. Simulation of the entire transceiver, including the microcode processor, is carried out to determine the RF performance at the communication packet level.

−110 −120 −130 Upconverted thermal noise −140 GSM spec

−150 −160 −170 −180

5

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10 10 10 Frequency offset [Hz] (FFT: len=5352523, nfft=5352523, nwin=137250) −80 −90

Upconverted flicker noise

−100 Phase noise [dBc/Hz]

VI. B EHAVIORAL M ODELING AND S IMULATION IN VHDL

−110 −120 −130 Upconverted thermal noise −140 GSM spec

−150 −160 −170 −180

5

10

6

10 Frequency offset [Hz]

7

10

Fig. 10. DCO phase noise of the last channel of the GSM900 band: (top) simulated in VHDL; (bottom) measured using Aeroflex PN9000.

Fig. 10 demonstrates capability and usefulness of the eventdriven simulation environment to model the RF phase noise

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B. VHDL RX Simulations The discrete-time mixer operation is modeled and simulated in VHDL directly in the charge-domain according to the equations described in Sec. IV-B and [13] and [14]. For example, the amount of charge being distributed through chargesharing between two capacitors is being tracked based on the relative capacitance ratio. This section demonstrates capability and usefulness of the event-driven simulation environment by specifically showing simulation results of a single-tone frequency input to the first generation DRP receiver while referring to the already published circuit topology examples and signal flow description in [13] and [14]. The input signal is corrupted by the thermal noise and a large interferer. The software-programmable mixer is a 2-pole IIR filtering system with a certain amount of an FIR anti-aliasing filtering. Both poles are programmed at 300 kHz (1.5 times the 200 kHz GSM channel spacing with the 100 kHz IF frequency) by controlling the capacitance ratio of the switched capacitor mixer circuit. Consequently, the filtering capability at the IFA output is 40 dB/dec with the 6-dB cutoff at 300 kHz. The ADC is a 5-level Σ∆ converter [20] operating at 1800 MHz / 64 = 28.125 MHz. 

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The channel of interest lies at 1820 MHz and its power level is at -99 dBm. The data is a continuous wave and is not GMSK modulated, as shown in Fig. 11. A large interferer at 3 MHz away at -23 dB power level is added. Their main purpose is to demonstrate the sensitivity and selectivity capabilities along various points of the receive path. The resolution bandwidth (actually, the FFT bin separation) is related to the number of FFT samples, so the signal power is obtained by integrating it over the windowing bandwidth.

In addition, there is a simple noise model for the 50-ohm RF thermal noise input at -174 dBm and the 10 dB noise figure of the receiver is lumped into the RF input. All the PSD plots use the averaged periodogram method. The power scale is normalized to the highest peak level. 

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behavior of an oscillator. It includes the upconverted flicker and thermal noise. The simulated noise profile of the DCO matches closely with the measured phase noise. DCO modeling in VHDL is described in detail in [19].

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After demodulation to near-zero IF, the channel of interest lies at 100 kHz. Fig. 12 shows the power spectral density for the IF buffer output after the second passive charge-sharing IIR filter, which is the first practical place one could extract the mixer output in a voltage, not charge, domain. The IF output has the sampling rate of 56.25 MHz. The 76 dB of the interferer-to-signal power ratio is now reduced to 37 dB, so the mixer selectivity realized only through passive devices provides almost 40 dB of the 3-MHz interferer reduction. Note the 40 dB/dec noise filtering profile at higher frequency offsets. Fig. 13(top) shows the spectrum of the 5-level second order Σ∆ ADC output operating at the sampling rate of 28.125 MHz. Since the Σ∆ ADC does not provide any closein filtering, the 37 dB of the interferer-to-signal power ratio at the mixer is maintained. The large amount of quantization noise gets shaped and pushed into higher frequencies as the 40 dB/dec profile. The task of the following decimating FIR (DFIR) filter is to remove this high frequency noise, as well as near interferers beyond the channel of interest (not applicable for this particular simulation). Spectrum at the DFIR output on Fig. 13(bottom) shows some filtering capability of the higher frequency quantization noise. This plot clearly shows the filter bandwidth of slightly greater than 200 kHz. At the neighborhood of 100 kHz, the signal-to-noise ratio is better than 20 dB, indicating a satisfactory level for baseband detector operation. The large 3 MHz interferer is now completely eliminated. VII. C ONCLUSION We have presented key digital RF processing techniques behind two generations of single-chip radios realized in a

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Fig. 13. PSD at (top) the second order Σ∆ ADC output; (bottom) the decimating FIR (DFIR) output.

deep-submicron CMOS technology: (1) Bluetooth personal area networking SoC and (2) GSM/EDGE cellular phone SoC. The local oscillator, transmitter and receiver are architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrated with digital baseband and application processors. The receiver operates on direct RF sampling techniques. Its selectivity is digitally controlled by the LO clock frequency and the capacitance ratio, both of which here are extremely precise. The modeling and simulation methodology of the entire radio is based on the standard VHDL hardware description language. R EFERENCES [1] W. Krenik, D. Buss and P. Rickert, “Cellular handset integration – SIP vs. SOC,” Proc. of 2004 IEEE Custom Integrated Circuits Conf., pp. 63– 70, Oct. 2004. [2] A. A. Abidi, “RF CMOS comes of age,” IEEE Journal of Solid-State Circuits, vol. 39, iss. 4, pp. 549–561, April 2004.

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