DIGITAL SIGNAL PROCESSING FOR DEEP SPACE TRANSPONDER L. Simone (1), S. Cocchi (1), M. D’Attilia (1), M. Delfino (1), A. Delfino (1) , G. Boscagli (2) (1)
Alenia Spazio Via Marcellina 11 - 00131 Rome (Italy) Email:
[email protected] (2)
Formerly Alenia Spazio, now ESA Email:
[email protected]
INTRODUCTION The progress of Digital Signal Processing techniques and the improvements of the Very Large Scale Integration (VLSI) technologies allow the implementation of digital modem for Deep Space Transponder (DST). Accordingly, a new class of DST based on digital architecture has been developed by Alenia for the ESA next Deep Space Missions (Rosetta, Mars Express). Besides, the digital-based design makes the proposed architecture suitable for a wide range of space applications other than deep space missions. Traditionally, DST provides up-link carrier tracking, command data demodulation, ranging signal turn-around and down-link carrier generation and modulation. The receiver digital architectures have the following advantages with respect to a fully analog solution: • Receiver reconfigurability (for carrier loop bandwidth) according to the received signal input power • Easy implementation of narrow loop bandwidths • Inclusion of data demodulation capability • Data rate flexibility with matched filtering implementation • Interface optimization based on the extensive use of command and telemetry housekeeping in digital format • Design flexibility with receiver tuning based on software constants • On-board regenerative ranging. Besides the frequency synthesis and the modulation process based on Numerically Controlled Oscillator (NCO) offer a great flexibility in terms of channel selection, data rate, modulation format and spectral shaping. This paper is presented in three sections. The first section provides an architectural overview of a digital DST. The second part offers in-depth description of the implemented algorithms and functions. Finally, the third part deals with the employed technology. DEEP SPACE TRANSPONDER ARCHITECTURE Fig.1 shows the Alenia DST architecture developed for Rosetta and Mars Express missions. It is composed by tree main blocks: the receiver section (with S-band and X-band front-end), the 5 W S-band transmitter and the low power (7 dBm) X-band transmitter [1]. The receiver section is based on a digital architecture as will be detailed in the following. The transmitter sections perform the function of transmitting and modulating the down-link signal in order to provide the ground stations with the telemetry signal and the ranging signal demodulated by the receiver. The DST frequency plan is based on the Sampled Phase Locked Loop (SPLL) approach and on the use of the Direct Digital Frequency Synthesis (DDFS). This architectural solution is very attractive , both in terms of size and output spectral purity, when high multiplication factors are required. Besides the Numerically Controlled Oscillator (NCO), based on the Coordinate Rotation Digital Computer (CORDIC) algorithm, allows great design flexibility with wide range tracking capability. In coherent mode, the down-link frequencies include the up-link Doppler contribution Fd evaluated by the microprocessor and scaled by the relevant turn-around ratio. In non-coherent mode the down-link frequencies are fixed. In general future deep space missions require transponders capable of up-link in X-band and down-link both in X and K band (X/X/K DST). Indeed the selection of X and K bands offer better link performance, in particular when accurate radio science experiment are required [2]. Alenia DST design allows to replace the S-band with the K-band transmitter leaving almost unchanged all the other functions included the digital signal processing.
DIGITAL SIGNAL PROCESSING FUNCTIONS The receiver analog section performs the signal down-conversion, filtering and amplification in order to provide the proper level to the Analog-to-Digital Converter (ADC) input. An analog wide-band Automatic Gain Control (AGC) is required to keep constant the signal-plus-noise power at the ADC input. The carrier loop closure at Intermediate Frequency (IF) allows the application of the coherent sampling: the signal is sampled at the fixed intermediate frequency F1 with a clock frequency 4F1 and the IF-to-baseband conversion is eliminated. The proposed sampling scheme produces alternatively in-phase and quadrature baseband samples, allowing the receiver digital signal processing section to perform the complex carrier demodulation without the use of a multiplier. With this approach, only one ADC is required and the phase and amplitude imbalances are avoided, being the mixing accomplished in the digital domain. The IF digitized samples are passed to the receiver digital section implementing signal tracking and data demodulation functions. The digital receiver section is based on a Receiver Application Specific Integrated Circuit (Rx ASIC), which mainly performs the high speed processing tasks, and on a Microprocessor, which allocates the low rate processing tasks (Fig.2).
Telemetry
221 F 1 + F d
S-Rx Front- End
Telecommand
4 F1
1s t L O G e n e r a t i o n
To Decoder
AGC µP
1 3 F1 + Fd 2 nd IF
ADC
DAC Rx NCO
4 F1 14 F1 + F d
240 F 1 + R sF d
Power Amplifier
nd
DAC
LO Generation
2 F1
Phase Modulator
DAC
2/3 F1 + R xFd /6
2
Ranging
Telemetry
4 F1
X-Tx NCO Ranging Video Filter
DAC
4 F1 1s t L O G e n e r a t i o n
S-Tx NCO
2/3 F1 + RsF d/3
X-Rx Front- End
2/3 F1 + Fd /3
749 F 1 + F d
Memories
ASIC
F1
1 st IF
To X-Tx Phase Modulator
To S-Tx Phase Modulator
Frequency Reference (USO/Internal TCXO)
S-Tx Frequency Generation
2 F1 4 F1 Phase Modulator
Telemetry
X2
÷2
X-Tx Frequency Generation
2 F1
Ranging
880 F 1 + R x F d
Fig. 1 Deep Space Transponder: architectural block diagram Rx ASIC To Ranging DAC
Ranging Channel
I/D
Clock
DTTL & Matched Filter
Recovered Data
∑ Quadrature Channel
F1
14F 1 + F d
1 3F 1 + F d
2 nd I F strip
ADC
4 F1
Even/Odd Decimation
Microprocessor Costas Loop Detector
∑ F1
I n -p h a s e Channel
Sub-Carrier NCO
∑
F1
Sub-carrier Lock Detector
Carrier Loop Filter
∑
2 nd L O Generation
Sub-Carrier Loop Filter
Carrier Lock Detector
2 / 3 F 1 + Fd/ 3
Carrier NCO
2/3 F 1 + R sF d / 3
S-Tx NCO
Rx NCO Base
2 4 0F 1 + R s F d
880 F 1 + R x F d
S-Tx SPLLL
X-Tx SPLL
2 / 3 F 1 + R xF d / 6
S-Tx NCO Base
Ks
X-Tx NCO Base
Kx
X-Tx NCO
Fig. 2 Digital receiver: functional block diagram
The chosen Hardware/Software partitioning allows a great flexibility in terms of functions, algorithms and design parameters. As an example, the tracking loops constants can be easily optimized during the receiver tuning phase to obtain the best performance. The following sections are devoted to Digital Signal Processing functions and management. Digital Receiver Algorithms Signal Model The command signal at the ADC input can be expressed as:
s (t ) = 2C sen[2πF1t + θ ⋅ D (t ) ⋅ sen(2πFsc t + φ sc ) + φ c ]
(1)
where C is the total transmitted power, F1 is the carrier frequency (∼9.5702 MHz), φ c is the carrier phase, Fsc is the sub-carrier frequency, φ sc is the sub-carrier phase, θ is the carrier modulation index and D(t) is the command nonreturn-to-zero (NRZ) data. The digital samples s(k) at the ADC output can be derived from (1) setting t = k 4F1 being k an integer value, i.e.:
k π π = 2C ⋅ sen k ⋅ I c ( k ) + 2C ⋅ cos k ⋅ Qc (k ) s ( k ) = s 2 2 4 F1
(2)
k I c (k ) = J 0 (θ ) ⋅ cos(φ c ) − J 1 (θ ) ⋅ sen(φ c ) ⋅ D (k ) ⋅ sen 2πFsc + φ sc 4 F1
(3)
k Qc (k ) = J 0 (θ ) ⋅ sen (φ c ) + J 1 (θ ) ⋅ cos(φ c ) ⋅ D(k ) ⋅ sen 2πFsc + φ sc 4 F1
(4)
in which:
are the in-phase and quadrature residual carrier baseband components, derived using the Anger-Jacobi expansion and neglecting the higher order terms being filtered out by the decimator stages. Carrier Demodulation As suggested by (2), the in-phase Ic (k ) and quadrature Qc (k ) baseband components can be recovered demultiplexing the sampled signal s(k) into even and odd samples and then multiplying alternatively by +1 and –1. Carrier Tracking Loop Equation (4) shows that the carrier loop error term φ c can be obtained from the quadrature samples, after digital mixing with quadrature reference signal. The carrier quadrature samples are accumulated to reduce the sampling rate, thus enabling the software implementation of the loop filter. The digital loop filter includes a perfect integrator, making the carrier recovery loop capable of tracking a frequency offset without steady state phase error. The filter outputs a frequency error estimate at the loop update rate adjusting the nominal frequency of the NCO that feeds the Digital-to-Analog Converter (DAC). The DAC output is mixed with the SPLL output frequency allowing the analog closure of the carrier loop at IF. The difference between the absolute value of the in-phase and quadrature baseband samples is used to implement the carrier lock detector. Sub-Carrier Tracking Loop In case of perfect carrier tracking φ c = 0 and Qc (k ) becomes proportional to the modulated sub-carrier. Hence, the sub-carrier tracking loop input is given by the quadrature baseband component of the residual carrier. The sub-carrier tracking loop is implemented as a second-order order Costas loop with hard-limited in-phase channel and squarewave reference. This solution has been analyzed in detail in [3]. During the sub-carrier acquisition phase, the Costas loop detector is configured as a frequency detector thus speeding the frequency acquisition process. Once the sub-carrier
frequency has been acquired, the Costas loop detector is configured as a phase detector in order to perform sub-carrier tracking. The in-phase signal of the sub-carrier is proportional to the modulating NRZ sequence . The difference between the absolute value of the in-phase and quadrature sub-carrier samples is used to implement the sub-carrier lock detector. Symbol Synchronization The in-phase signal of the sub-carrier is applied to the Digital Data Transition Tracking Loop (DTTL) performing symbol synchronization and matched filtering. The base-band input signal is passed through two parallel channels: the in-phase channel monitors the polarity of the actual transitions and the quadrature channel measures the timing error accumulating over the estimated symbol transition. The quadrature channel output is delayed by one-half symbol period and then multiplied by the in-phase channel output. The multiplication results is the loop error signal, that is proportional to the estimate of the timing error. Subsequently, the loop error signal is filtered by the loop filter with the resulting output being used to control the timing generator. The DTTL is implemented as a digital first-order loop and it shows a steady-state error in presence of Doppler or frequency instability. However, at low symbol rates, the DTTL NCO is clocked by the estimated sub-carrier frequency and only the phase must be recovered. Transponder Coherence The DST frequency plan must guarantee the coherent turn-around ratio between the transmitted and the received signal in order to enable two-way ranging. The DST architecture is based on DDFS that intrinsically does not allow the coherent turn-around function due to frequency control quantization. To avoid a frequency error due to the NCO control word quantization, the dithering of the base frequency is performed at carrier loop sampling time. Besides, a dedicated signal processing is implemented to compensate the deviation of the down-link signal phase from its desired value. Digital Automatic Gain Control Digital AGC algorithms are used for digital receiver calibration. The digitized samples are collected from the Rx ASIC by the Microprocessor and the loop filter is software implemented. During the signal detection and carrier acquisition phases a non-coherent AGC is performed, using both the in-phase (3) and quadrature (4) baseband components of the residual carrier. During carrier tracking, a coherent AGC based on the in-phase baseband component of the residual carrier is implemented. Turn-Around Ranging The tone demodulation with base-band conversion is implemented inside the digital section; after mixing with the F1 frequency, the samples are processed by an integrate-and-dump filter (I/D) which accumulates the base-band samples and dumps at an output rate equal to F1 2 . After digital-to-analog conversion, the samples are routed to ranging video circuit composed by: high pass filter for DC offset rejection, active low pass filter for rejection of non desired spectral component (spectrum replica and alias), resistive divider to route the signal both at S-band and X-band down-link modulator. To simplify the hardware design, the video AGC (usually applied in the video channel) has been removed. However, at low signal-to-noise ratio, the same performance have been obtained by properly tuning the overall ranging channel, including the down-link modulation index. In Fig.3 the performance of Rosetta ranging channel (RF AGC only) in terms of down-link ranging side-bands power over overall down-link signal power Pr Ptot is compared versus the classical video AGC approach. The transponder digital architecture allows the application of on-board regenerative ranging. This approach becomes important in case of low signal to noise ratio typical of deep space application. Indeed the traditional ranging channel routes to the down-link modulator all the up-link noise power reducing the useful sideband ranging components and affecting the ground station performances. Digital Receiver Management The Microprocessor manages the digital signal processing operations according to the State Diagram sketched in Fig.4. The following operative scenarios are foreseen: • Low input power level: -146 dBm ≤C
