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Digital Signal Processor Controlled PWM Phase Modulator for Two Phase Voltage Source Inverter
Digital Signal Processor Controlled PWM Phase Modulator for Two Phase Voltage Source Inverter
by
Muhibul Haque Bhuyan
MASTER OF SCIENCE IN ELECTRICAL AND ELECTRONIC ENGINEERING
Department of Electrical and Electronic Engineering BANGLADESH UNIVERSITY OF ENGINEERING AND TECHNOLOGY (BUET) 2002
The thesis titled "Digital Signal Processor Controlled PWM Phase Modulator for Two
Phase Voltage Source Inverter" submitted
by Muhibul Haque Bhuyan Roll
\OOOO6243F, Session: October 2000 has been accepted as satisfactory in partial
No:
fulfillment
of the requirement for the degree of Master of Science in Electrical and Electronic Engineering on September 10, 2002.
BOARD OF'EXAMINERS
Dr.KaziMujibur Rahman Associate Professor
Chairman (Supervisor)
Department ofEEE, BUET Dhaka - 1000, Bangladesh
Dr. Mohammad Ali Choudhury Professor Department of EEE, BLIET Dhaka - 1000, Bangladesh
Professor and Head
Member
Member (Ex-offrcio)
Department of EEE, BUET Dhaka - 1000, Bangladesh
4 qrr,"rb
Dr. K. Siddique-E Robbani Professor Department of Physics University of Dhaka Dhaka - 1000, Bangladesh
Member (External)
CANDIDATE’S DECLARATION It is hereby declared that this thesis “Digital Signal Processor Controlled PWM Phase Modulator for Two Phase Voltage Source Inverter” or any part of it has not been submitted elsewhere for the award of any degree or diploma.
Signature of the candidate
____________________________ Muhibul Haque Bhuyan
Dedicated to My Parents
Contents List of Tables List of Figures
ix x
List of Abbreviations
xviii
List of Symbols
xix
Acknowledgments
xx
Abstract
xxi
Chapter 1 Introduction
1
1.1
Introduction
1
1.2
Literature Review
2
1.2.1 Review of PWM Techniques in Static Inverters 1.2.2 Review of Microcomputer Controlled PWM Techniques for Static Inverters
3 5
1.2.3 Review of Digital Signal Processor Controlled PWM Techniques for Inverters and Motor Drives
8
1.3
Problems in State of the Art Control
11
1.4
Objectives of the Work
12
1.5
Methodology
12
1.6
Organization of the thesis
13
Chapter 2 Theory Development and Simulation
15
2.1
15
Introduction
2.2 Inverters 2.2.1 Performance Parameters for Inverters
15 16
2.3
PWM Signal
17
2.4
PWM Pattern Generation
18
2.4.1 Natural Sampled PWM Pattern Generation
18
2.4.2 Regular Sampled PWM Pattern Generation
19
2.4.3 Optimal PWM Pattern Generation
24
2.4.4 Three-Level and Two-Level PWM Pattern Generation
28
2.4.5 Calculation of Pulse Width and Number of pulses
29
2.4.6 Switching Angle and Phase Voltage Calculation
32
vi
2.4.7 Current in the R-L Load with a Step Voltage Input
34
2.5
36
Torque for Induction Motors
2.5.1 Formulation 2.5.2 Methods of Torque Control in Induction Motor
36 37
2.5.3 Rotating Magnetic Field for Two-Phase Induction Motor
38
2.5.4 Torque Equation for Two-Phase Induction Motor Under Balanced Condition
40
2.5.5 Torque Equation for Two-Phase Induction Motor Under Unbalanced Condition
42
2.5.6 Torque-Speed Characteristics of Two-Phase Induction Motor Under Unbalanced Condition 2.6 Simulation of PWM Pattern for Two Phase Induction Motor
44 46
2.7
Simulation of Currents for Phase A of a Two Phase Induction Motor
67
2.8
Summary
81
Chapter 3 Implementation Scheme using DSP
82
3.1
Introduction
82
3.2
Hardware Architecture Using Digital Signal Processor
82
3.2.1 Personal Computer
82
3.2.2 Digital Signal Processor Kit (TMS320C50)
83
3.2.3 RS 232C Serial Interface 3.2.4 Hardware Interfacing Circuit
84 85
3.2.5
89
Inverter Controller Circuit
3.2.6 Power Inverter Circuit Using MOSFETs
92
3.2.7
Switching Matrices for the Variation of Modulation Index
92
3.3
Software Development Using ANSI C Compiler
93
3.3.1 Configuring the 8255 Peripheral Interface 3.3.2 Development of the Program 3.4
Summary
93 94 100
Chapter 4 Data Acquisition and Result Analysis
101
4.1
Introduction
101
4.2
Inverter Operation
101
4.2.1 The Integrated Development Environment
101
4.2.2 MDA-DSP Windows
102 vii
4.2.3 The Main and Sub Menu
102
4.2.4 The Program Window
102
4.2.5 The MMR (Memory Mapped Register) Window 4.2.6 The Block B2 Window
102 102
4.2.7 The Block B0-B1 Window
102
4.2.8 The Basic Operation Procedure
103
4.2.9 Operation of the Inverter
103
4.3
PWM Patterns and Current Waveforms
110
4.4
Summary
126
Chapter 5 Conclusions
127
5.1
Conclusion
127
5.2 5.3
Limitations of the Proposed Systems Recommendations for Future Works
129 129
References
130
Appendix
138
viii
List of Tables Table Number 2.6.1
2.6.2
2.6.3
2.6.4
Title of the Tables
Page Number
Distortion factors in switching patterns of three and two level PWM scheme for phase A and phase B of a two phase voltage source inverter with the variation of fundamental frequency (f) for fc = 1400 and 1600 Hz, M = 1.0 and Z = 1.0
62
Distortion factors in switching patterns of three and two level PWM scheme for phase A and phase B of a two phase voltage source inverter with the variation of modulation index (M) for f = 50 Hz, fc = 1400 and 1600 Hz and Z = 1.0
63
Distortion factors in switching patterns of three and two level PWM scheme for phase A and phase B of a two phase voltage source inverter with the variation of carrier frequency (fc) for f = 50 Hz, M = 1.0 and Z = 1.0
63
Distortion factors in switching patterns of three and two level PWM scheme for phase A and phase B of a two phase voltage source inverter with the variation of phase modulation index (Z) for f = 50 Hz, fc = 1400 Hz and M = 1.0
64
ix
List of Figures Figure Page Captions of the Figure Number Number 2.3.1 Various types of PWM Signals: (a) Symmetric PWM Signals, (b) Asymmetric PWM Signals (Left Justified), (c) Asymmetric PWM Signals (Right Justified) 17 2.4.1 Details of kth pulse in two level regular-sampled asymmetric PWM: (a) Modulating waveform, (b) Regular-sampled waveform, and (c) PWM waveform. 20 2.4.2 Regular-sampled symmetric double edge modulations 21 2.4.3 Generation of Three-Level Regular-Sampled PWM, (a) Regular-Sampled Modulating Wave, (b) Three-Level PWM Inverter Voltage 22 2.4.4 Details of kth Pulse in Three Level Regular-Sampled Symmetric PWM, (a) Reference Modulating Signal, (b) Regular-Sample (or Carrier) Signal, and (c) PWM Signal 23 2.4.5 Details of pulse obtained using Suboptimal Strategy (a) Reference modulating Signal, (b) Regular-Sample (or Carrier) signal, and (c) PWM signal 27 2.4.6 (a) Sinusoidal Reference Signal, (b) Three-Level and (c) Two-Level PWM Pattern 28 2.4.7 Pulse width calculation for Three-Level PWM Pattern (a) Sinusoidal Reference Signal, (b) Sampled Signal, (c) PWM Output Voltage 29 2.4.8 Pulse width calculation for Two-Level PWM Pattern: (a) Sinusoidal Reference Signal, (b) Sampled Signal, (c) PWM Output Voltage 31 2.4.9 Two Phase Half Bridge Voltage Source Inverter for Two Phase Induction Motor 33 2.4.10 A Unit Step Input Voltage applied to an R-L Load 35 2.5.1 The Shaft of a Motor and its cross-sectional view 36 2.5.2 Diagram of a simple Two-Phase Three Wire Induction Motor 38 2.5.3 (a) The assumed positive direction of fluxes (b) The sinusoidal flux distribution due to the flow of current in each phase winding 38 2.5.4 Vector representations of magnetic fluxes for Two-Phase Induction Motor for various instances 39 2.5.5 Schematic representation of Two-Phase Induction Motor 40 2.5.6 Equivalent circuit for Two-Phase Induction Motor under unbalanced condition in terms of phase A 42 2.5.7 Torque-Speed Characteristics of a Two-Phase Induction Motor. (a) voltage in phase A, (b) voltage in phase B, (c) phase angle between phase A and B 45 2.6.1 MATLAB Simulation results of the three level scheme. (a) Harmonic Spectrum of phase A, (b) PWM Pattern of phase A, (c) PWM Pattern of phase B with f = 50 Hz, fc = 1400 Hz, M = 1.0, Z = 1.0 and N = 28 46 x
2.6.2
2.6.3
2.6.4
2.6.5
2.6.6
2.6.7
2.6.8
2.6.9
2.6.10
2.6.11
2.6.12
2.6.13
2.6.14
2.6.15
2.6.16
MATLAB Simulation results of the three level scheme. (a) Harmonic Spectrum of phase A, (b) PWM Pattern of phase A, (c) PWM Pattern of phase B with f = 60 Hz, fc = 1400 Hz, M = 1.0, Z = 1.0 and N = 23 MATLAB Simulation results of the three level scheme. (a) Harmonic Spectrum of phase A, (b) PWM Pattern of phase A, (c) PWM Pattern of phase B with f = 70 Hz, fc = 1400 Hz, M = 1.0, Z = 1.0 and N = 20 MATLAB Simulation results of the three level scheme. (a) Harmonic Spectrum of phase A, (b) PWM Pattern of phase A, (c) PWM Pattern of phase B with f = 50 Hz, fc = 1600 Hz, M = 1.0, Z = 1.0 and N = 32 MATLAB Simulation results of the three level scheme. (a) Harmonic Spectrum of phase A, (b) PWM Pattern of phase A, (c) PWM Pattern of phase B with f = 60 Hz, fc = 1600 Hz, M = 1.0, Z = 1.0 and N = 27 MATLAB Simulation results of the three level scheme. (a) Harmonic Spectrum of phase A, (b) PWM Pattern of phase A, (c) PWM Pattern of phase B with f = 70 Hz, fc = 1600 Hz, M = 1.0, Z = 1.0 and N = 23 MATLAB Simulation results of the three level scheme. (a) Harmonic Spectrum of phase A, (b) PWM Pattern of phase A, (c) PWM Pattern of phase B with f = 50 Hz, fc = 1400 Hz, M = 0.9, Z = 1.0 and N = 28 MATLAB Simulation results of the three level scheme. (a) Harmonic Spectrum of phase A, (b) PWM Pattern of phase A, (c) PWM Pattern of phase B with f = 50 Hz, fc = 1400 Hz, M = 0.8, Z = 1.0 and N = 28 MATLAB Simulation results of the three level scheme. (a) Harmonic Spectrum of phase A, (b) PWM Pattern of phase A, (c) PWM Pattern of phase B with f = 50 Hz, fc = 1600 Hz, M = 0.9, Z = 1.0 and N = 32 MATLAB Simulation results of the three level scheme. (a) Harmonic Spectrum of phase A, (b) PWM Pattern of phase A, (c) PWM Pattern of phase B with f = 50 Hz, fc = 1600 Hz, M = 0.8, Z = 1.0 and N = 32 MATLAB Simulation results of the three level scheme. (a) Harmonic Spectrum of phase A, (b) PWM Pattern of phase A, (c) PWM Pattern of phase B with f = 50 Hz, fc = 1000 Hz, M = 1.0, Z = 1.0 and N = 20 MATLAB Simulation results of the three level scheme. (a) Harmonic Spectrum of phase A, (b) PWM Pattern of phase A, (c) PWM Pattern of phase B with f = 50 Hz, fc = 1200 Hz, M = 1.0, Z = 1.0 and N = 24 MATLAB Simulation results of the three level scheme. (a) Harmonic Spectrum of phase A, (b) PWM Pattern of phase A, (c) PWM Pattern of phase B with f = 50 Hz, fc = 1400 Hz, M = 1.0, Z = 0.5 and N = 28 MATLAB Simulation results of the three level scheme. (a) Harmonic Spectrum of phase A, (b) PWM Pattern of phase A, (c) PWM Pattern of phase B with f = 50 Hz, fc = 1400 Hz, M = 1.0, Z = 0.0 and N = 28 MATLAB Simulation results of the three level scheme. (a) Harmonic Spectrum of phase A, (b) PWM Pattern of phase A, (c) PWM Pattern of phase B with f = 50 Hz, fc = 1400 Hz, M = 1.0, Z = -0.5 and N = 28 MATLAB Simulation results of the three level scheme. (a) Harmonic Spectrum of phase A, (b) PWM Pattern of phase A, (c) PWM Pattern of phase B with f = 50 Hz, fc = 1400 Hz, M = 1.0, Z = -1.0 and N = 28 xi
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2.6.17
2.6.18
2.6.19
2.6.20
2.6.21
2.6.22
2.6.23
2.6.24
2.6.25
2.6.26
2.6.27
2.6.28
2.6.29
2.6.30
2.6.31
MATLAB Simulation results of the two level scheme. (a) Harmonic Spectrum of phase A, (b) PWM Pattern of phase A, (c) PWM Pattern of phase B with f = 50 Hz, fc = 1400 Hz, M = 1.0, Z = 1.0 and N = 28 MATLAB Simulation results of the two level scheme. (a) Harmonic Spectrum of phase A, (b) PWM Pattern of phase A, (c) PWM Pattern of phase B with f = 60 Hz, fc = 1400 Hz, M = 1.0, Z = 1.0 and N = 23 MATLAB Simulation results of the two level scheme. (a) Harmonic Spectrum of phase A, (b) PWM Pattern of phase A, (c) PWM Pattern of phase B with f = 70 Hz, fc = 1400 Hz, M = 1.0, Z = 1.0 and N = 20 MATLAB Simulation results of the two level scheme. (a) Harmonic Spectrum of phase A, (b) PWM Pattern of phase A, (c) PWM Pattern of phase B with f = 50 Hz, fc = 1600 Hz, M = 1.0, Z = 1.0 and N = 32 MATLAB Simulation results of the two level scheme. (a) Harmonic Spectrum of phase A, (b) PWM Pattern of phase A, (c) PWM Pattern of phase B with f = 60 Hz, fc = 1600 Hz, M = 1.0, Z = 1.0 and N = 27 MATLAB Simulation results of the two level scheme. (a) Harmonic Spectrum of phase A, (b) PWM Pattern of phase A, (c) PWM Pattern of phase B with f = 70 Hz, fc = 1600 Hz, M = 1.0, Z = 1.0 and N = 23 MATLAB Simulation results of the two level scheme. (a) Harmonic Spectrum of phase A, (b) PWM Pattern of phase A, (c) PWM Pattern of phase B with f = 50 Hz, fc = 1400 Hz, M = 0.9, Z = 1.0 and N = 28 MATLAB Simulation results of the two level scheme. (a) Harmonic Spectrum of phase A, (b) PWM Pattern of phase A, (c) PWM Pattern of phase B with f = 50 Hz, fc = 1400 Hz, M = 0.8, Z = 1.0 and N = 28 MATLAB Simulation results of the two level scheme. (a) Harmonic Spectrum of phase A, (b) PWM Pattern of phase A, (c) PWM Pattern of phase B with f = 50 Hz, fc = 1600 Hz, M = 0.9, Z = 1.0 and N = 32 MATLAB Simulation results of the two level scheme. (a) Harmonic Spectrum of phase A, (b) PWM Pattern of phase A, (c) PWM Pattern of phase B with f = 50 Hz, fc = 1600 Hz, M = 0.8, Z = 1.0 and N = 32 MATLAB Simulation results of the two level scheme. (a) Harmonic Spectrum of phase A, (b) PWM Pattern of phase A, (c) PWM Pattern of phase B with f = 50 Hz, fc = 1000 Hz, M = 1.0, Z = 1.0 and N = 20 MATLAB Simulation results of the two level scheme. (a) Harmonic Spectrum of phase A, (b) PWM Pattern of phase A, (c) PWM Pattern of phase B with f = 50 Hz, fc = 1200 Hz, M = 1.0, Z = 1.0 and N = 24 MATLAB Simulation results of the two level scheme. (a) Harmonic Spectrum of phase A, (b) PWM Pattern of phase A, (c) PWM Pattern of phase B with f = 50 Hz, fc = 1400 Hz, M = 1.0, Z = 0.5 and N = 28 MATLAB Simulation results of the two level scheme. (a) Harmonic Spectrum of phase A, (b) PWM Pattern of phase A, (c) PWM Pattern of phase B with f = 50 Hz, fc = 1400 Hz, M = 1.0, Z = 0.0 and N = 28 MATLAB Simulation results of the two level scheme. (a) Harmonic Spectrum of phase A, (b) PWM Pattern of phase A, (c) PWM Pattern of phase B with f = 50 Hz, fc = 1400 Hz, M = 1.0, Z = -0.5 and N = 28 xii
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2.6.32
2.6.33
2.6.34
2.6.35
2.6.36
2.7.1
2.7.2
2.7.3
2.7.4
2.7.5
2.7.6
2.7.7
2.7.8
2.7.9
MATLAB Simulation results of the two level scheme. (a) Harmonic Spectrum of phase A, (b) PWM Pattern of phase A, (c) PWM Pattern of phase B with f = 50 Hz, fc = 1400 Hz, M = 1.0, Z = -1.0 and N = 28 Plot of Distortion Factors (DF) vs Fundamental Frequency (f) for different Level of PWM Schemes: (a) 3-level fc = 1400 Hz, (b) 3-level for fc = 1600 Hz, (c) 2-level for fc = 1400 Hz, (d) 2-level for fc = 1400 Hz for phase A of a 2-phase VSI with M = 1.0 and Z = 1.0 Plot of Distortion Factors (DF) vs Modulation Index (M) for different level of PWM Schemes: (a) 3-level for fc = 1400 Hz, (b) 3-level for fc = 1600 Hz, (c) 2-level for fc = 1400 Hz, (d) 2-level for fc = 1400 Hz for phase A of a 2-phase VSI with f = 50 Hz and Z = 1.0 Plot of Distortion Factors (DF) vs Carrier Frequency (fc). (a) Three Level PWM Scheme, (b) Two Level PWM scheme for Phase A of a 2-Phase Voltage Source Inverter with f = 50 Hz, M = 1.0 and Z = 1.0 Plot of Distortion Factors (DF) vs Phase Modulation Index (Z). (a) Three Level PWM Scheme, (b) Two Level PWM Scheme for Phase A of a 2-Phase Voltage Source Inverter with f = 50 Hz, fc = 1400 Hz and M = 1.0 Current waveform of a two phase induction motor for three level PWM scheme obtained using MATLAB Simulation for phase A with f = 50 Hz, fc = 1400 Hz, M = 1.0 and Z = 1.0 and N = 28 Current waveform of a two phase induction motor for three level PWM scheme obtained using MATLAB Simulation for phase A with f = 60 Hz, fc = 1400 Hz, M = 1.0 and Z = 1.0 and N = 23 Current waveform of a two phase induction motor for three level PWM scheme obtained using MATLAB Simulation for phase A with f = 70 Hz, fc = 1400 Hz, M = 1.0 and Z = 1.0 and N = 20 Current waveform of a two phase induction motor for three level PWM scheme obtained using MATLAB Simulation for phase A with f = 50 Hz, fc = 1600 Hz, M = 1.0 and Z = 1.0 and N = 32 Current waveform of a two phase induction motor for three level PWM scheme obtained using MATLAB Simulation for phase A with f = 60 Hz, fc = 1600 Hz, M = 1.0 and Z = 1.0 and N = 27 Current waveform of a two phase induction motor for three level PWM scheme obtained using MATLAB Simulation for phase A with f = 70 Hz, fc = 1600 Hz, M = 1.0 and Z = 1.0 and N = 23 Current waveform of a two phase induction motor for three level PWM scheme obtained using MATLAB Simulation for phase A with f = 50 Hz, fc = 1400 Hz, M = 0.9 and Z = 1.0 and N = 28 Current waveform of a two phase induction motor for three level PWM scheme obtained using MATLAB Simulation for phase A with f = 50 Hz, fc = 1400 Hz, M = 0.8 and Z = 1.0 and N = 28 Current waveform of a two phase induction motor for three level PWM scheme obtained using MATLAB Simulation for phase A with f = 50 Hz, fc = 1600 Hz, M = 0.9 and Z = 1.0 and N = 32 xiii
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2.7.10
2.7.11
2.7.12
2.7.13
2.7.14
2.7.15
2.7.16
2.7.17
2.7.18
2.7.19
2.7.20
2.7.21
2.7.22
2.7.23
2.7.24
Current waveform of a two phase induction motor for three level PWM scheme obtained using MATLAB Simulation for phase A with f = 50 Hz, fc = 1600 Hz, M = 0.8 and Z = 1.0 and N = 32 Current waveform of a two phase induction motor for three level PWM scheme obtained using MATLAB Simulation for phase A with f = 50 Hz, fc = 1000 Hz, M = 1.0 and Z = 1.0 and N = 20 Current waveform of a two phase induction motor for three level PWM scheme obtained using MATLAB Simulation for phase A with f = 50 Hz, fc = 1200 Hz, M = 1.0 and Z = 1.0 and N = 24 Current waveform of a two phase induction motor for two level PWM scheme obtained using MATLAB Simulation for phase A with f = 50 Hz, fc = 1400 Hz, M = 1.0 and Z = 1.0 and N = 28 Current waveform of a two phase induction motor for two level PWM scheme obtained using MATLAB Simulation for phase A with f = 60 Hz, fc = 1400 Hz, M = 1.0 and Z = 1.0 and N = 23 Current waveform of a two phase induction motor for two level PWM scheme obtained using MATLAB Simulation for phase A with f = 70 Hz, fc = 1400 Hz, M = 1.0 and Z = 1.0 and N = 20 Current waveform of a two phase induction motor for two level PWM scheme obtained using MATLAB Simulation for phase A with f = 50 Hz, fc = 1600 Hz, M = 1.0 and Z = 1.0 and N = 32 Current waveform of a two phase induction motor for two level PWM scheme obtained using MATLAB Simulation for phase A with f = 60 Hz, fc = 1600 Hz, M = 1.0 and Z = 1.0 and N = 27 Current waveform of a two phase induction motor for two level PWM scheme obtained using MATLAB Simulation for phase A with f = 70 Hz, fc = 1600 Hz, M = 1.0 and Z = 1.0 and N = 23 Current waveform of a two phase induction motor for two level PWM scheme obtained using MATLAB Simulation for phase A with f = 50 Hz, fc = 1400 Hz, M = 0.9 and Z = 1.0 and N = 28 Current waveform of a two phase induction motor for two level PWM scheme obtained using MATLAB Simulation for phase A with f = 50 Hz, fc = 1400 Hz, M = 0.8 and Z = 1.0 and N = 28 Current waveform of a two phase induction motor for two level PWM scheme obtained using MATLAB Simulation for phase A with f = 50 Hz, fc = 1600 Hz, M = 0.9 and Z = 1.0 and N = 32 Current waveform of a two phase induction motor for two level PWM scheme obtained using MATLAB Simulation for phase A with f = 50 Hz, fc = 1600 Hz, M = 0.8 and Z = 1.0 and N = 32 Current waveform of a two phase induction motor for two level PWM scheme obtained using MATLAB Simulation for phase A with f = 50 Hz, fc = 1000 Hz, M = 1.0 and Z = 1.0 and N = 20 Current waveform of a two phase induction motor for two level PWM scheme obtained using MATLAB Simulation for phase A with f = 50 Hz, fc = 1200 Hz, M = 1.0 and Z = 1.0 and N = 24 xiv
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3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 3.2.6 3.2.7 3.2.8 3.3.1 3.3.2 3.3.3 4.2.1
4.2.2
4.2.3
4.2.4
4.2.5 4.2.6 4.2.7 4.2.8
4.3.1
4.3.2
Block Diagram of the Digital Signal Processor Controlled PWM Phase Modulator for 2-Phase Voltage Source Inverter for 2-Phase Induction Motor 83 Connection Diagram of MDA-DSP Kit with PC: (a) PC 25 Pin, MDA-DSP 9 Pin Connection, (b) PC 9 Pin, MDA-DSP 9 Pin Connection 85 Clock, Counter and Pulse Stretcher Circuit 85 Data Storage Devices using EPROM 27C256 87 Decoding of Signals for the two transistor of the same leg of the power inverter: (a) in Three Level PWM Scheme, (b) in Two Level PWM Scheme 88 Buffer and Opto-isolation Circuit 89 Buffers, Current Amplifiers and Gate Isolation Circuits 90 Switching matrices for the variation of the modulation index 92 Control word for 8255 to configure port A and B as output and port C as input port 94 Flow Chart for developing the software in ANSI C to generate PWM patterns in Three Level PWM Scheme 96-98 Flow Chart for developing the software in ANSI C to generate PWM patterns in Two Level PWM Scheme 99-100 Hardware Interfacing Circuit for the digital signal processor controlled PWM phase modulator for two phase voltage source inverter (for three level PWM scheme) 104 Photograph of the Real-time Hardware Interfacing Circuit, implemented on the PCB, for the digital signal processor controlled PWM phase modulator for two-phase voltage source inverter (for three-level PWM scheme) 105 Hardware Interfacing Circuit for the digital signal processor controlled PWM phase modulator for two phase voltage source inverter (for two-level PWM scheme) 106 Photograph of the Real-time Hardware Interfacing Circuit, implemented on the PCB, for the digital signal processor controlled PWM phase modulator for two-phase voltage source inverter (for two-level PWM scheme) 107 Circuit diagram of a two-phase half-bridge inverter and its controller circuit (for both two and three level PWM scheme) 108 Photograph of the real-time two-phase half-bridge inverter and its controller circuit implemented on a PCB (for both two and three level PWM schemes) 109 Photograph of the MDA-DSP kit (TMS320C50) 109 Photograph of the complete system of digital signal processor controlled PWM phase modulator for two phase induction motor using two level PWM scheme 110 PWM patterns obtained at the output of the EPROM for Q1 MOSFET and the phase current waveform of phase A for three level PWM scheme with f = 50 Hz, fc = 1400 Hz, M = 1.0, Z = 1.0 and N = 28 111 PWM patterns obtained at the output of the EPROM for Q1 MOSFET and the phase current waveform of phase A for three level PWM scheme with f = 60 Hz, fc = 1400 Hz, M = 1.0, Z = 1.0 and N = 23 111 xv
4.3.3
4.3.4
4.3.5
4.3.6
4.3.7
4.3.8
4.3.9
4.3.10 4.3.11 4.3.12 4.3.13 4.3.14 4.3.15
4.3.16
4.3.17
4.3.18
PWM patterns obtained at the output of the EPROM for Q1 MOSFET and the phase current waveform of phase A for three level PWM scheme with f = 70 Hz, fc = 1400 Hz, M = 1.0, Z = 1.0 and N = 20 PWM patterns obtained at the output of the EPROM for Q1 MOSFET and the phase current waveform of phase A for three level PWM scheme with f = 50 Hz, fc = 1400 Hz, M = 0.9, Z = 1.0 and N = 28 PWM patterns obtained at the output of the EPROM for Q1 MOSFET and the phase current waveform of phase A for three level PWM scheme with f = 50 Hz, fc = 1400 Hz, M = 0.8, Z = 1.0 and N = 28 PWM patterns obtained at the output of the EPROM for Q1 MOSFET and the phase current waveform of phase A for three level PWM scheme with f = 50 Hz, fc = 1600 Hz, M = 1.0, Z = 1.0 and N = 32 PWM patterns obtained at the output of the EPROM for Q1 MOSFET and the phase current waveform of phase A for three level PWM scheme with f = 50 Hz, fc = 1600 Hz, M = 0.9, Z = 1.0 and N = 32 PWM patterns obtained at the output of the EPROM for Q1 MOSFET and the phase current waveform of phase A for three level PWM scheme with f = 50 Hz, fc = 1600 Hz, M = 0.8, Z = 1.0 and N = 32 PWM patterns obtained at the output of the EPROM for Q1 MOSFET and the phase current waveform of phase A for three level PWM scheme with f = 50 Hz, fc = 1200 Hz, M = 1.0, Z = 1.0 and N = 24 Phase current waveforms for phase A and phase B for three level PWM scheme with f = 50 Hz, fc = 1400 Hz, M = 1.0, Z = 1.0 and N = 28 Phase current waveforms for phase A and phase B for three level PWM scheme with f = 50 Hz, fc = 1400 Hz, M =1.0, Z = 0.5 and N = 28 Phase current waveforms for phase A and phase B for three level PWM scheme with f = 50 Hz, fc = 1400 Hz, M = 1.0, Z = 0.0 and N = 28 Phase current waveforms for phase A and phase B for three level PWM scheme with f = 50 Hz, fc = 1400 Hz, M = 1.0, Z = -0.5 and N = 28 Phase current waveforms for phase A and phase B for three level PWM scheme with f = 50 Hz, fc = 1400 Hz, M = 1.0, Z = -1.0 and N = 28 PWM patterns obtained at the output of the EPROM for Q1 MOSFET and the phase current waveform of phase A for two level PWM scheme with f = 50 Hz, fc = 1400 Hz, M = 1.0, Z = 1.0 and N = 28 PWM patterns obtained at the output of the EPROM for Q1 MOSFET and the phase current waveform of phase A for two level PWM scheme with f = 60 Hz, fc = 1400 Hz, M = 1.0, Z = 1.0 and N = 23 PWM patterns obtained at the output of the EPROM for Q1 MOSFET and the phase current waveform of phase A for two level PWM scheme with f = 70 Hz, fc = 1400 Hz, M = 1.0, Z = 1.0 and N = 20 PWM patterns obtained at the output of the EPROM for Q1 MOSFET and the phase current waveform of phase A for two level PWM scheme with f = 50 Hz, fc = 1400 Hz, M = 0.9, Z = 1.0 and N = 28
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112
112
113
113
114
114
115 115 116 116 117 117
118
118
119
119
4.3.19
4.3.20
4.3.21
4.3.22
4.3.23
4.3.24 4.3.25 4.3.26 4.3.27 4.3.28
PWM patterns obtained at the output of the EPROM for Q1 MOSFET and the phase current waveform of phase A for two level PWM scheme with f = 50 Hz, fc = 1400 Hz, M = 0.8, Z = 1.0 and N = 28 PWM patterns obtained at the output of the EPROM for Q1 MOSFET and the phase current waveform of phase A for two level PWM scheme with f = 50 Hz, fc = 1600 Hz, M = 1.0, Z = 1.0 and N = 32 PWM patterns obtained at the output of the EPROM for Q1 MOSFET and the phase current waveform of phase A for two level PWM scheme with f = 50 Hz, fc = 1600 Hz, M = 0.9, Z = 1.0 and N = 32 PWM patterns obtained at the output of the EPROM for Q1 MOSFET and the phase current waveform of phase A for two level PWM scheme with f = 50 Hz, fc = 1600 Hz, M = 0.8, Z = 1.0 and N = 32 PWM patterns obtained at the output of the EPROM for Q1 MOSFET and the phase current waveform of phase A for two level PWM scheme with f = 50 Hz, fc = 1200 Hz, M = 1.0, Z = 1.0 and N = 24 Phase current waveforms for phase A and phase B for two level PWM scheme with f = 50 Hz, fc = 1400 Hz, M = 1.0, Z = 1.0 and N = 28 Phase current waveforms for phase A and phase B for two level PWM scheme with f = 50 Hz, fc = 1400 Hz, M = 1.0, Z = 0.5 and N = 28 Phase current waveforms for phase A and phase B for two level PWM scheme with f = 50 Hz, fc = 1400 Hz, M = 1.0, Z = 0.0 and N = 28 Phase current waveforms for phase A and phase B for two level PWM scheme with f = 50 Hz, fc = 1400 Hz, M = 1.0, Z = -0.5 and N = 28 Phase current waveforms for phase A and phase B for two level PWM scheme with f = 50 Hz, fc = 1400 Hz, M = 1.0, Z = -1.0 and N = 28
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120
120
121
121
122 122 123 123 124 124
List of Abbreviations ADC BIOS BJT CMOS CPU DAS DF DSP EPROM HEPWM HF LED LOH MOSFET p.u. PWM ROM RSPWM SPWM THD TI TTL VSI VVVF
Analog to Digital Converter Basic Input Output System Bipolar Junction Transistor Complimentary Metal Oxide Semiconductor Central Processing Unit Data Acquisition System Distortion Factor Digital Signal Processing/Processor Erasable Programmable Read Only Memory Harmonic Elimination PWM Harmonic Factor Light Emitting Diode Lowest Order Harmonic Metal Oxide Semiconductor Field Effect Transistor per unit Pulse Width Modulator/Modulation Read Only Memory Regular Sampled PWM Sine Pulse Width Modulation Total Harmonic Distortion Texas Instruments Transistor Transistor Logic Voltage Source Inverter Variable Voltage Variable Frequency
xviii
List of Symbols
Pulse Width of a Sample
D1 - D4
Free-wheeling Diodes of the Inverter
DF_A, DF_B
Distortion factors in PWM Pattern or in motor Currents of Phase A & B
f
Fundamental Frequency
fc
Carrier or Sampling Frequency
M
Modulation Index
N
Number of Samples in a Fundamental Period
n
Sample Number
p
Number of Poles per Phase of the Motor
PDA
Phase Difference Angle
Q1 - Q4
MOSFETs of the Inverter or Inverter Switches
r1 – r2
Resistance of the Motor Winding
T
Fundamental Time Period
Tc
Carrier Time Period
Van, Vbn
Phase voltages of Phase A and Phase B
Vs
DC Supply Voltage to the Inverter
x1 – x2
Reactance of the Motor Winding
xm
Mutual Reactance of the Motor Windings
Z
Phase Modulation Index
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Acknowledgements First of all, the author expresses his heartiest gratitude to the Almighty Allah, the most beneficent, the most merciful to give him “toufique” to complete this work successfully.
Then the author expresses his profound gratitude and respect to his supervisor Dr. Kazi Mujibur Rahman, Associate Professor of the Department of Electrical and Electronic Engineering, Bangladesh University of Engineering and Technology (BUET), for his erudite suggestions, helpful discussions, invaluable assistance and great encouragement in the process of completing this work. Without his able guidance, constructive suggestions, supply of research materials and above all wholehearted supervision it would have been impossible to realize the work in proper time.
The author also expresses his thanks and gratefulness to the Committee of Advanced Studies and Research (CASR) of BUET for the financial support in this research.
The author would also like to express his thanks and respects to all the members of the Board of Post Graduate Studies (BPGS) for their unanimous decisions for which this research has come into reality. Their invaluable suggestions and corrections are also gratefully acknowledged.
Sincerest thanks are also due to my friend Mr. Mohammed Imamul Hassan Bhuiyan, Assistant Professor of the Department of EEE, BUET for his encouragement and co-operation for the course of this thesis work.
Finally, the author expresses his profound gratitude to his parents and sincerest thanks to other family members for their inspiration and extension of their hands during the progress of this work.
xx
ABSTRACT The work is aimed at proposing a phase modulated PWM scheme for two-phase voltage source inverter optimizing the pattern for minimum third harmonic content. The proposed two phase PWM controller is implemented with a Digital Signal Processor (DSP, TMS320C50). The experimental waveforms is compared with the simulated ones for different characteristic parameters like distortion factors. This work results in an improved controller for two phase motor drives and position controllers employing DSP. Both three level and two level PWM schemes are adopted for the generation of PWM signals for the inverter. For implementation of the scheme two different programs are written in C by using ANSI C compiler supplied with the TI’s TMS320C50. For compiling and running the program an INTEL Pentium IV microcomputer is used. After running the program the code is uploaded to the TMS320C50 DSP kit. After that the DSP kit supplies the calculated switching points through its I/O ports to the external hardware interfacing circuit using EPROMs. The byte patterns for PWM signals generated using MATLAB are stored in two EPROMs (27C256) as data. The DSP kit sends calculated duty cycles to the EPROMs and then according to the calculated duty cycles required patterns are obtained at the output of the EPROMs. For controlling the whole process a 12-bit counter, a high frequency clock circuit, a monostable timer and buffers are used. To test the performance of the scheme these signals are then applied to a two phase half bridge inverter using MOSFETs. To drive the inverter properly an electronic controller circuit is also developed. The supplied DC voltage to the inverter is 90V. The output of the inverter is fed to a prototype 0.5 hp two phase induction motor. Phase currents of the motor are obtained using two current transformers and resistors. Finally the system performance is evaluated from the MATLAB simulation results and experimental waveforms. Upon completion of the work it is found that the two level scheme gives the better system performance especially the distortion factors of output current is much lower in this scheme than that in the three level scheme. The experimental result shows good agreement with the simulated one.
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1
Chapter 1 Introduction 1.1
Introduction
Small electric motors are produced by many manufacturers in many varieties and sizes. These have penetrated into our almost servant less domestic society and highly automatic world of commerce and industry. Of all the various types of AC motors, the fractional horsepower induction motor is the most popular for use in single-phase and poly-phase circuits. The enormous popularity of the induction motor is due to its simplicity of construction, reliability and constant-speed characteristics. A single-phase induction motor has no revolving field when stationary and no inherent lockedrotor torque. It is, therefore, necessary to employ a starting device of some sort for any singlephase induction motor. There are many varieties of these, for example, the split-phase, capacitor-start, repulsion-start and reactor-start motors. A single-phase induction motor will continue to run in the direction in which it is started. The split phase motor is one of the oldest types of single-phase motor ever built for commercial use. Even today it is one of the most widely used of all the types of single-phase motors. It is used in washing machines, oil burners, blowers, centrifugal pumps, woodworking tools, business machines, bottle washers, churns, automatic musical instruments, grinders, machine tools and a host of other applications. It is most widely used in the ratings from 1/20 to 1/2 hp. Great interest is shown nowadays in the fractional horsepower variable speed drive systems. DC motors supplied from the controlled rectifiers or choppers are mainly used for this purpose. Small two-phase induction motor had been very popular in servomechanisms since the 1940’s. In general, the speed control for two-phase induction motors is carried out by adjusting the control winding voltage by the quadrature control signal of an AC amplifier while exciting the reference winding with supply of constant frequency and amplitude. This typical control method had been widely used because an AC source is usually available and an AC amplifier is drift free. However, the drift ability of an AC amplifier is not satisfactory. The advent of low-cost
2 power semiconductor devices in the early 1960’s solved the drift problem of DC source, so in servomechanisms, the two-phase induction motors were replaced with DC motors, which are easy to control and have a high efficiency. But DC motors have some disadvantages, such as the friction between the commutator and brush, which causes high maintenance cost and shortens work life. Besides, the DC motor is more expensive than a single-phase induction motor of the same power [1]. Therefore, AC motors are being studied again to reduce maintenance cost and increase motor’s work life. Today, inverters are used for ac motor drive. The function of an inverter is to change a dc input voltage to a symmetrical ac output voltage of desired magnitude and frequency. For variable speed and energy efficient operation of ac motors there is no other alternative than using an inverter. The ratings of two-phase induction motors are usually low; so simple inverters are needed. Although the two-step inverters reported earlier are simple and cheap [2], [3], the harmonic contents of output voltage are relatively high, and with a fixed DC voltage source, the amplitude of output voltage cannot be controlled. Hence, the motor speed control capability is weak, and the motor efficiency at slow speed is low because of magnetic saturation. If the dc input voltage is fixed and it is not controllable, a variable output voltage can be obtained by varying the gain of the inverter. The inverter gain may be defined as the ratio of the ac output voltage to dc input voltage. Variation of the gain is normally accomplished by pulsewidth-modulation (PWM) technique within the inverter. The conventional pulse width modulated (PWM) inverters represent the best solution for the reduction of the harmonic content of the output voltage. In this research, digital signal processor (DSP) controlled PWM phase modulator for two phase voltage source inverter to drive low power two phase induction motor will be investigated. Before that an extensive review of the literature is done to find out the specific problems that are to be solved in this work.
1.2
Literature Review
A review of the historical development of the PWM techniques is presented in this section to emphasize the need for the development of the digital signal processor (DSP) based pulse width modulation (PWM) technique. The review of the literature for this work will be discussed under three subtitles. The first one will expound the chronological development of pulse width
3 modulation (PWM) techniques for static power converter operation, the second one will take a look over the microcomputer-based generation of PWM switching pulse reported in literature so far and the third one will discuss about the development of the digital signal processor (DSP) controlled PWM inverter.
1.2.1 Review of PWM Techniques in Static Inverters Static converters that convert dc power to ac are known as inverters. According to their source in general there are two types of inverters: voltage-fed inverter and current-fed inverter. The output of normal square-wave voltage-fed and current-fed inverters are non-sinusoidal and contain low frequency harmonics. Beside, the utility line power factor deteriorates due to the low phase shifts and the system may suffer instability at low frequencies due to the low-pass filter in the dc link. Problems stated above have led to the developments of pulse width modulated (PWM) inverters where the switches of the power converter are operated at higher frequency following particular modulation pattern to enjoy the following advantages: a) achieve simultaneous voltage, frequency and harmonic content control of inverter output in a single power stage [6]-[14] b) perform harmonic reduction and ripple elimination using small size filters at the input/output of the converters resulting low loss c) enhance performance and conversion efficiency of converter d) improve operating power factor [15]. There are several types of modulation schemes to switch inverters, these are, i) Single pulse-width modulation ii) Multiple pulse-width modulation iii) Sine pulse-width modulation (PWM) [16] - Asynchronous - Synchronous - Regular Sampled
4 iv) Optimal PWM v) Delta PWM (DPWM) The earliest modulation techniques applied to inverter operation were single pulse-width modulation and multiple pulse-width modulation [17]-[21], [10], [14]. In single pulse width modulation technique, there is only one pulse per half cycle and the width of the pulse is varied to control the output voltage of the inverter. Here comparing rectangular reference signal with a triangular carrier wave generates the switching signals. The frequency of the reference signal determines the fundamental frequency of the output voltage. In this technique the dominant harmonic is third harmonic, and the distortion factor is significantly large at low output voltage [22]-[24], [9]. In multiple pulse-width modulation technique the harmonic content and the distortion factor of single pulse-width modulation is reduced by producing several pulses in each half-cycle of output voltage. However, due to large number of switching per half-cycle, the switching loss and the amplitude of higher order harmonics would increase although the amplitude of lower order harmonics would decrease. Among several PWM techniques in industrial applications, sine pulse-width modulation (SPWM) is common [24]-[34], [11], [13]. Based on the carrier generation, there are different types of carrier waves [35]-[40]. In sine pulse-width modulation technique, a high frequency isosceles triangle carrier wave is compared with a fundamental-frequency sine modulating wave, and the natural points of interaction determine the switching points of power drives. As a result, in SPWM, instead of maintaining same width of each pulse as in multiple pulse-width modulation the width of each pulse is varied in proportion to the amplitude of the sine wave evaluated at the center of the same pulse. Eventually the distortion factor and low order harmonics are reduced significantly [41]-[47], [10]-[11], [22]. As for drive applications, the fixed frequency modulation has been proved to be problematic at different operating frequencies and the ordinary SPWM was replaced by variable frequency ratio PWM scheme. At present, three distinct SPWM schemes are in use for inverters [48-50], [34]. These are natural sampling method, regular sampling method and optimal switching strategy. Traditionally pulse width modulation control was accomplished using an analog technique known as natural sampling [89]-[91]. This method resembles the multiple pulse modulations
5 where a triangular carrier wave is compared with sine wave to generate PWM pulses. The equations describing the natural sampled switching angles are transcendental and therefore not suitable for microprocessor software implementation. This led to the development of a regular sampling technique in the early 1970’s [89]. Regular sampling is a digital process of sampling a sinusoidal modulating wave, at regularly spaced intervals to produce sinusoidally weighted digital samples of the modulating wave. This method is very common in microcomputer implementation [51], [52]. However, schemes are available in the literature for implementation of naturally sampled SPWM with a microcomputer using advance computational algorithm [92]. The third scheme uses optimized switching strategies based on certain performance criteria [53]. Evolution of microprocessor technology supports the implementation of optimized pulsewidth modulation for switching inverters [54]-[56]. A recent modulation method for switching inverter is the Adaptive PWM technique utilizing hysteresis control, which is referred to as Delta pulse-width modulation (DPWM) [57]. So far for various power converter operations, use of several types of DPWM have been investigated [58], [59]. In delta modulation, a triangular wave is allowed to oscillate within a defined window above and below the reference sine modulating wave. This simple and idealized PWM scheme offers the advantages of continuous converter voltage control and a direct control on the line harmonics. Tuning the feedback filter can control its performance. The DM schemes have the disadvantages of non-uniform switching and suffer from sub-harmonic problems in case of wide bands.
1.2.2 Review of Microcomputer Controlled PWM Techniques for Static Inverters Analog implementation of PWM switching circuit suffers from the problems associated with thermal drift, component tolerance, dc offset and imperfections in the amplitude and phase of three-phase analog sine-wave generation, which produces harmonic effect in the inverter systems. Regular switching action of analog PWM circuit also generates conducted and radiated electromagnetic interference (EMI), and may also generate acoustical disturbance [60]. The above problems are solved by microcomputer-based digital control technique of switching pulses which have profoundly influenced power electronics and static drive system for industrial automation [6]-[10], [22].
6 In contrast to the rapid development of single-chip microcomputers in the early 1970’s, works on microprocessor base power electronics can be traced back to early 1977 at the furthest. The first computer revolution began with Von Neumann’s work in 1945 [61], and second computer revolution began with the commercialization of the microprocessor in 1971, when INTEL introduced the 4004, 4-bit single-chip central processing unit (CPU). Form the first generation of microprocessor using 4-bit architecture; 32/64-bit microprocessors are now available having tremendous speed above 1.7GHz [44]. Microprocessor has largely contributed the control system to provide them with powerful RAS (Reliability, Availability, and Serviceability), together with improved flexibility and performance control system. The trend is found not only in the rising robotics control, factory automation and so forth but also in the replacement of plant in the established industries. The control of static converters and drives by microprocessor can easily be recognized for complex drive control system. The digital control has inherently improved noise immunity, which is particularly important for power electronics because of large power switching transients in the converters. The works on microprocessor-based firing schemes for three-phase full-wave dual converter [62]-[63], for phase controlled rectifier connected to a weak ac system [64] for thyristor choppers [65]-[66], have proved the authentic implementation of microprocessors in this field to optimize drive system performance to improve power factor and effective diagnostics of the relevant system. These are achieved using I/O interfaces and peripheral equipment as programmable counters, programmable memory, interrupt controller, VCO, multipliers, D/A and A/D converters etc. together with the CPU microprocessor use which utilizes look-up tables for firing control. As a result, these techniques cannot prove smooth control and high resolution over wide range of variation of the control variable. Microprocessor-based control of dc motor drives [67]-[69], electronic vehicle [70], and ac drive like induction motor [71]-[73], synchronous motor [74], commutatorless motor drives [75], and reluctance motor [76] etc. is being implemented for automatic and efficient control using dedicated hardware and software. To write about microprocessor controlled inverter, an expound review of microprocessor-based PWM waveform generation necessarily precedes since PWM is by far the best available technique for the production of switching pulses of an inverter. The microprocessor-based technique is advantageous not only for PWM waveform but also for high-resolution real-time sine wave generation by programmable logic cell array. Real-time implementation [77] of
7 SPWM switching strategies for inverters by Optimal, Regular and Natural sampling method using microprocessor has been constant effort of the researchers [78], [79]. The implementation techniques reported are based on transcendental equation relating PWM switching angles and lack generality when implemented by microcomputer [80]. The computation of switching points has so far been complex and time consuming in the absence of substantially developed algebraic equation requiring solution of transcendental formulas. As a result the switching points are stored in EPROM based look-up tables computed on off-line basis. This implies that a very large number of tables must be stored in memory in order to keep the frequency and voltage resolution within the acceptable limits; otherwise a step variation of fundamental voltage during frequency control would lead to undesirable operations of inverters [79].
A possible solution to this drawback of implementing optimal PWM waveform is to store the PWM pattern corresponding to selective frequencies and to use interpolation to compute the intermediate patterns [81], having direct multiplication and division capability with coprocessors. This approach poses similar implementation difficulty because of off-line calculations [82]. Sampling techniques posses’ well-defined modulation procedures, which reveal the possibilities of developing real-time algorithms capable of generating PWM control in the frequency range of the inverter having minimal storage requirements [83]. The ratios of carrier to fundamental frequency tends to be very high at low frequencies, which needs huge table of switching angles for optimized or harmonic elimination strategies. Moreover, optimized waveforms have no significant advantages over sampling waveforms as far as harmonic performance is concerned at low fundamental voltage. The number of notch-angles for a switching pattern tends to increase at lower fundamental frequency, demanding large look-up table memory. As a result, the lower frequency and the number of switching patterns stored tend to be limited. Even if we think of a very large memory, the present microprocessor-based modulators suffers from inadequate and poor angle resolution response in real-time with change in voltage and frequency commands. Techniques to reduce the computational requirements for SPWM switching has been studied [78], [79], [84] and to save CPU time, the DMA technique is used as reported in reference [85] for transferring the switching pattern from memory to the pulse amplifier. The DMA transfer methods have deficiencies as mentioned above. Attempt has also been made to implement three-phase PWM waves by hybrid implementation with computation intensive uniform sampling method in the low-frequency region and look-up tables in the higher frequency region [86].
8 A programmable SPWM scheme to generate switching pulses with display provision associated with converter output voltage-current waveforms and their respective frequency spectra has been reported in reference [87] which uses peripheral digital ICs like PDMA-16 card and mass storage medium for implementation. This implementation method takes a total calculation and preparation time of approximately 120 seconds, of which 110 seconds were spent to compute the required gating signals for using non-linear equations and 10 seconds were used to prepare and deliver the gating signals to the converter. In the work reported in [60] programmed optimal SPWM techniques have been applied using methods to control amplitude of harmonic peaks by the EMI generated by the switched power circuits. It has been implemented by 64 bytes of EPROM and 16MHz oscillator and presettable down counters as peripheral circuitry. Here the relatively large sensitivity of the spectrum to random perturbation (such as round-off) in the switching instants can cause difficulties. The above type of implementation needs microcomputer along with peripherals of digital ICs of on-chip 8-or 10-b A/D converters, 28 interrupt sources, programmable high speed input (HSI) and programmable high speed output (HSO) [87], PDMA-16 card and mass storage medium [86], DMA chips and 2564 RAMs [84], 8259 interrupt controller, 2.5 Kb EPROM, oscillator etc. [85]. They are basically more off-line microprocessor-based switching pulse generator and may be considered as modification to unified approach to the real time implementation [78] and harmonic minimization [88] for various types of SPWM techniques only. Technical trends are to implement sophisticate control algorithm of the system in the software, thereby reducing peripheral hardware chips to provide higher performance. To alleviate the problems related to frequency limited poor switching angle resolution in the discussed off-line schemes, an on-line microcomputer based Delta-PWM technique has also been devised using INTEL 80386 DX-2 microcomputer to solve simple algebraic equation to find switching points of sign delta modulated wave and output the generated pulses through the parallel port [93].
1.2.3 Review of Digital Signal Processor Controlled PWM Techniques for Inverters and Motor Drives The era of analog control systems for electric motor drives is definitely over, and a wide array of digital devices is available for drive designers. All modern PWM techniques are discrete time in nature and hence needs to be implemented digitally. Digital controllers allow implementation
9 of sophisticated operating algorithms, offering significant technical advantages thanks to their ability of fast processing of vast data, high operational flexibility, and ease of integration into automated industrial systems. If the digital processors involved are so efficient that reserves of computing power remain after the basic control algorithms have been realized, additional enhancing features can be implemented, such as the self commissioning and auto tuning, efficiency optimization, or automated fault diagnostics of the drives. Traditionally, general-purpose micro controllers have been the devices of choice when analog controllers were being replaced with digital ones. Embedded PWM schemes normally use a microprocessor or a micro controller along with peripherals for real time computation and implementation. These schemes normally require special hardware architecture for efficient control in real time. The control of adjustable speed drives and static power converters in the 1980’s and 1990’s was increasingly based on the real-time digital generation of pulse-width modulated (PWM) waveforms using either microprocessors or application-specific integrated circuits (ASICs). Microprocessors-based PWM generation techniques offer significant advantages, particularly for optimizing the PWM waveform. However, the maximum switching frequency of the inverter can be severely limited by the computation time needed to generate the PWM switching times in the microprocessors, particularly when advanced PWM strategies are used; for example, the harmonic minimization [53] or harmonic elimination [94] PWM strategies, which involve considerable on-line, real-time computing. Past development of these more advanced PWM strategies has involved considerable off-line computation, using a mainframe computer to determine the PWM switching angle characteristics. This has been necessary because the equations relating PWM switching angles to voltage are transcendental and cannot be solved online by a microprocessor-based controller. Significant off-line computation is therefore involved in developing these strategies [95], [96], and this has delayed their use by industry in many applications. In contrast, the conventional natural sampled [89]-[91] and regular sampled [91], [97] PWM techniques are based on well established and definable modulation processes, which can be readily implemented using standard hardware or microprocessor software implementations [97]-[102]. Recently developed novel harmonic elimination and harmonic minimized PWM control strategies, based on regularsampling techniques [90], can be used to reduce significantly the computational requirements and provide more efficient real-time microprocessor-based PWM implementations [102].
10 General-purpose microprocessors are not considered in newer designs for economic and operational constraints. Digital signal processors (DSP) are investigated as alternatives among the embedded processor family for such applications. In recent years, the digital signal processors (DSPs) have been enjoying increased interest and implementation in control of electric motors. The DSPs still suffer from certain misconceptions among design engineers who tend to associate them with classic data processing tasks such as image analysis or speech recognition. However, the newly emerging class of DSP controllers (DSPCs) is likely to dispel such notions and to dominate the motion control market in the years to come. Digital Signal Processors (DSP processor) have different architecture than general purpose Microprocessors. DSP processors have powerful arithmetic unit that can do multiplication and division operations very fast. A DSP is much faster (ten times or even more) than a microprocessor [103]. They can do fast data transfer, can perform complicated control algorithm with fast speed and can execute most instructions in a single clock cycle. Some DSPs have builtin hardware floating point unit, programmable timers, control area network, fast PWM ports, DMA, interrupt controller, multi-channel A/D converters and many more other facilities suitable for most control system. Besides, simplification of control hardware and a corresponding reduction of cost in comparison with analog control is the principal advantage of DSP control. For this reason, DSP processors are preferred for real time applications. DSP based schemes can handle and implement complex mathematical models and hence are most suitable for drive controls [104]-[107]. Recently many DSP based drive schemes have been reported in the literature. Apart from control of PWM schemes, DSP have found a wide application in motion control [108]-[110]. A motion controller needs multiple feedback signals with high precision computation. The major application of DSP is in the field oriented space vector drives that need huge arithmetic computations [111], [112]. Flexible ac transmission systems (FACTS), static var compensators (SVC) also need huge computations and feedback that can be easily implemented with a DSP [113], [114]. In the DSP based current control for brushless motor system, DSP performs not only the current control but a necessary control processing such as rotor position sensing, speed calculation and a calculation of the torque command through the speed control loop [115]. Not only speed and current controls but also a real-time identification of the motor parameters can be implemented by software using the digital signal processor (DSP) TMS320C25.
11 For on-line parameter estimation in a highly precise control system the self-tuning control technique [116] is used. It has already been implemented for reference tracking of a DC drive using a single-chip digital signal processor (DSP). It results in reduction of system hardware, cost and calculation time [117]. To implement self-tuned integral-proportional (IP) speed controller for a rolling mill dc drive system, 32 bit floating point digital signal processor (DSP) - TMS320C30, has been used. It showed excellent adaptation capability under parameter change and a better transient recovery characteristic than a conventional PI controller under load change. Both speed measurement and a load torque observer were carried out on line at about 1 ms sampling time [118]. Pillay et al. [119] proposed a DSP-based vector and current control scheme for a PMSM drive. The design is centered on the TI TMS320E17 and TMS302E15 DSPs. The TMS320E17 is used to implement the vector control algorithm while the TMS320E15 is used to implement the current controller. The relatively slow speed of the DSPs affects the performance of the current controllers due to the high bandwidth and high sampling requirement. For constant power operation field oriented induction machine drive is a desirable candidate because the field of the induction machine can be easily weakened by reducing the flux component current as the rotor speed increases. The maximum output torque developed by the machine is dependent on the allowable current rating and the maximum voltage limit of the machine. To yield the maximum torque per ampere over the entire high speed range a novel field weakening approach is developed. The whole control algorithm is fully implemented in a digital control system based on a TMS320C30 DSP [120].
1.3
Problems in State of the Art Control
It is evident from the literature review that the two-phase induction motor control using PWM technique is necessary for some applications. However, the application of PWM techniques to the two-phase induction motors has been restricted, because the drives are too complicated for small two-phase induction motors [2]. But for position control and reversible speed drive applications inverter driven two-phase induction motor is a good choice. Reluctance type permanent magnet hybrid motors may be used for medium power applications [4]. Torque and speed of two-phase induction motors can be controlled by direct-coupled equations having many independent parameters, such as voltage magnitude, fundamental and carrier frequency
12 and phase angle difference between the two phases. Inverter driven two phase motor drives are controlled by varying voltage and frequency [5]. Researchers exclude phase angle because of computational burden on the processor. However, inclusion of phase angle control would make the controller more versatile. In addition to speed control, phase angle control would result smooth speed reversal and reduce torsion stress on the drive shaft. A hybrid type implementation can reduce the computation burden on the processor drastically. Hence using the hybrid implementation, the phase angle can be incorporated in the control process that would widen the application area of inverter driven two-phase motors. To control voltage, frequency and phase angle by using inverter digital signal processor (DSP) would be the best choice so that faster computation of the switching points is possible. Since there is no triplen harmonic eliminator in two-phase drives, the PWM patterns of twophase inverters needs to be more refined than three-phase inverters. In this regard, the PWM process will involve high precision arithmetic for precise PWM waveform.
1.4
Objectives of the Work
The work is aimed at proposing a phase modulated PWM scheme for two-phase voltage source inverter to drive two phase induction motor optimizing the pattern for minimum third harmonic content. The proposed two-phase PWM controller will be implemented with a Texas Instrument’s digital signal processor (TMS320C50). Moreover special care will be taken so that real time PWM waveform does not deteriorate from the theoretical ones. The proposed scheme is expected to give better control on two-phase inverter. The experimental waveforms will be compared with the simulated ones for different characteristic parameters like total harmonic distortion and harmonic contents. Successful completion of the work will result in an improved controller for two-phase motor drives and position controllers employing DSP.
1.5
Methodology
A theoretical model of phase modulated PWM scheme would be developed. The amplitude of the voltages of the two phases, frequency, carrier and phase angle would be the controlling parameters of the new PWM scheme. One phase would be angle (phase) modulated to facilitate variable phase shift between the phases. The modulating function for the phase angle would
13 vary from +1 to –1 and multiplied by a constant of /2 radians. The model would be optimized for minimum third harmonic contents since there is no inherent cancellation process of the triplen harmonics like three phase applications. Both three-level and two-level PWM strategy (employing any one switch of a phase leg in active state) would be adopted for the proposed model. Three-level PWM scheme would facilitate accurate freewheeling of load currents in inductive loads. The model of the proposed PWM controller would involve trigonometric functions. A processor having floating-point support or high precision arithmetic unit with hardware multiplier would be needed for computing the Taylor series of the trigonometric functions. A high-speed generalpurpose microprocessor with floating point unit is needed for real time implementation that would make the scheme uneconomic. A DSP processor is extremely suited for implementing the scheme since it has high-resolution arithmetic unit with hardware multiplier and parallel internal architecture. The implementation of the proposed scheme would be done using a TMS320C50 (40MHz) trainer having essential interface hardware. The TMS320C50 (40MHz) processor takes about 200 microseconds for computing a sine function. Hence the DSP alone would not be able to generate high-resolution PWM patterns at higher operating frequencies. For this reason a ROM Look Up Table based external hardware would be used for generating the real time PWM patterns. The instruction formats of DSP processor are different from a microprocessor. The equations involved in the scheme would be transformed in DSP format. An ANSI C compiler supplied by Texas Instrument would be used to program and generate the machine codes for the DSP processor. The DSP would be involved for computing the duty cycle of the PWM pulses for two phases. It would then send the PWM codes to 8255 ports where an external ROM based circuit would generate the real time waveforms. Provisions would be made to take frequency, phase voltages and phase angle as input to the controller. Finally the scheme would be tested on a two-phase MOSFET inverter.
1.6
Organization of the thesis
This thesis is organized as follows: Chapter 2 analyzes the development of PWM techniques for the proposed two-phase induction motors. It also discusses the modeling of two-phase induction motors and its torque-speed characteristics. Simulated waveforms and data for distortion factors
14 found using MATLAB are presented in this chapter for the proposed model. Chapter 3 describes the hardware architecture based on the digital signal processor (DSP) with its functional block diagram. It also describes the development of program using ANSI C with flow charts. Chapter 4 provides the detailed circuit diagram of the proposed scheme and the operation of the inverter. Then it analyzes various real-time waveforms obtained from the oscilloscope screen using a camera for both PWM patterns and phase currents of the motor and compares with the simulated results obtained in chapter 2. Finally, Chapter 5 concludes the thesis with recommendations for future research on DSP based PWM techniques and motor drives.
15
Chapter 2 Theory Development and Simulation 2.1
Introduction
This chapter explains the digital pulse width modulation technique and its advantages, calculation of the pulse width for the proposed scheme, modeling of two-phase induction motor, derivation of torque equation for two phase induction motor for variable and reversible speed operation. Various parameters related to pulse width-modulated inverters are also explained. In addition to this, digital signal processor controlled half bridge inverter is given. The simulation results of PWM pattern and current waveform for the proposed scheme using MATLAB are presented in this chapter. From here the expected performance of the proposed real time scheme is analyzed.
2.2
Inverters
DC-to-AC converter is known as inverters. The function of an inverter is to change a dc input voltage to a symmetrical ac output voltage of desired magnitude and frequency. The output voltage could be fixed or variable at a fixed or variable frequency. Varying the input dc voltage and maintaining the gain of the inverter constant a variable output voltage can be obtained. On the other hand, if the dc input voltage is fixed and it is not controllable, a variable output voltage can be obtained by varying the gain of the inverter, which is normally accomplished by pulsewidth-modulation (PWM) control within the inverter. The inverter gain may be defined as the ratio of the ac output voltage to dc input voltage. The output voltage waveforms of ideal inverters should be sinusoidal. However, the waveforms of practical inverters are non-sinusoidal and contain certain harmonics. For low- and mediumpower applications, square-wave or quasi-square-wave voltages may be acceptable; and for high-power applications, low distorted sinusoidal waveforms are required. With the availability of high-speed power semiconductor devices, the harmonic contents of output voltage can be minimized or reduced significantly by switching techniques.
16
2.2.1 Performance parameters for Inverter The quality of an inverter is normally evaluated in terms of the following performance parameters: Harmonic factor of nth harmonic, HFn: The harmonic factor (of the nth harmonic), which is a measure of individual harmonic contribution, is defined as H Fn
Vn
2 .2 .1
V1
where V1 is the rms value of the fundamental component and Vn is the rms value of the nth harmonic component.
Total Harmonic Distortion THD: The total harmonic distortion, which is a measure of closeness in shape between a waveform and its fundamental component, is defined as 1 THD V1
n 2 , 3 ...
2
Vn
1/2
2 .2 .2
Distortion Factor DF: THD gives the total harmonic content, but it does not indicate the level of each harmonic component. If a filter were used at the output of inverters, the higher-order harmonic would be attenuated more effectively. Therefore, knowledge of both the frequency and magnitude of each harmonic is important. The distortion factor indicates the amount of harmonic distortion that remains in a particular waveform after the harmonics of that waveform have been subjected to a second-order attenuation (i.e. divided by n2). Thus DF is a measure of effectiveness in reducing unwanted harmonics without having to specify the values of a secondorder load filter and is defined as 1 Vn DF 2 V 1 n 2 , 3 ... n 2
1/2
2 .2 .3
The distortion factor of an individual (or nth) harmonic component is defined as D Fn
Vn V1 n
2
2 .2 .4
Lowest-order harmonic LOH: The lowest-order harmonic is that harmonic component whose frequency is closest to the fundamental one, and its amplitude is greater than or equal to 3% of the fundamental component.
17
2.3
PWM Signal
PWM signals are pulse trains with fixed frequency and magnitude and variable pulse width. There is one pulse of fixed magnitude in every PWM period. However, the width of the pulses changes from period to period according to a modulating signal. When a PWM signal is applied to the gate of a power transistor, it causes the turn on or turn off intervals of the transistor to change from one PWM period to another PWM period, according to the same modulating signal. The frequency of a PWM signal is usually much higher than that of the modulating signal, or the fundamental frequency, such that the energy delivered to the motor and its load depends mainly on the modulating signal. There are two types of PWM signals: symmetric and asymmetric. The pulses of a symmetric PWM signal are always symmetric with respect to the center of each PWM period as shown in Fig. 2.3.1 (a). Hence they do not contain any sub-harmonics in the load current. It is also called center justified PWM. On the other hand, the pulses of an asymmetric PWM signal always have the same side aligned with one end of each PWM period. It is of two types: left justified [Fig. 2.3.1 (b)] and right justified [Fig. 2.3.1 (c)].
PWM Period
PWM Period
PWM Period
PWM Period
(a)
(b)
(c)
Fig. 2.3.1 Various types of PWM Signals: (a) Symmetric PWM Signals, (b) Asymmetric PWM Signals (Left Justified), (c) Asymmetric PWM Signals (Right Justified)
18 It is found in the literature that for the same computation complexity, the symmetric PWM technique gives better performance than the left justified technique, such as, the center justified PWM scheme is seen to have low total harmonic distortion (THD) compared to the left justified scheme [121]. For some of the conventional modulation processes like regular symmetric sampled PWM, regular asymmetric sampled PWM the resulting switching angles for a single phase due to the modulation process can be found out using simple equations involving the modulation parameters like modulation index, modulating frequency, and modulating frequency to carrier frequency ratio. These equations can be easily implemented digitally such as using microprocessor or digital signal processor. In this work, Texas Instrument‟s inexpensive TMS320C20 DSP controller has been used. But this controller has no floating-point support, but these equations produce floating-point results. So, for direct implementation using fixed-point arithmetic, the parameters of the modulation process will have to be scaled properly to reduce the truncation errors that arise during the calculation of switching angles. For the given modulating frequency and parameters of the modulation process the switching angles are represented in time scale in units of microseconds. For the generation of PWM pattern for two phase induction motor, the number of pulses in one carrier period will be calculated using fixedpoint arithmetic.
2.4
PWM Pattern Generation
Among several Pulse Width Modulation (PWM) techniques in industrial applications, sine pulse-width modulation (SPWM) is the most common one. At present, three distinct SPWM schemes are in use for inverters. These are natural sampling method, regular sampling method and optimal switching strategy. These three methods are described in the following three subsections.
2.4.1 Natural Sampled PWM Pattern Generation Natural-sampled PWM is based on a well define modulation process, involving a direct comparison of a sinusoidal modulating wave and a triangular carrier (sampling) wave. In this process the sampling points and pulse positions are not regularly spaced. The switching edge of the width-modulated pulse is determined by the instantaneous intersection of the two waves, and
19 the resultant pulse width is proportional to the amplitude of the modulation wave at the instant that switching occurs, defined by the transcendental equation: t2
t1
T M 1 2 2
s in t 1
s in t 2
2 .4 .1
This transcendental pulse-width equation can only be solved only by using Bessel function series or numerical techniques [122], and therefore cannot be used directly as a basis for microprocessor software-based generation of PWM. It is, of course, possible to simulate the analogue process of natural sampling in the microprocessor software using the logic/counter capabilities of the microprocessor to determine the pulse widths [7]. However this may require a large number of samples of the sinusoidal modulating wave to be stored in ROM (read only memory) to achieve resemble accuracy, and if software generating loops are used for the real-time sampling comparison, this „ties-up‟ the microprocessor and prevents other sampling being performed. The real-time sampling comparison is, therefore, performed appropriately using external hardware or counters, thus freeing the microprocessor to perform other tasks, while the PWM pulse periods are being „timed-out‟. The
detailed
microprocessor
hardware/software
trade-off
based
on
cost/size
and
accuracy/timings for this period of PWM generation have been investigated earlier for 8 bit microprocessors. Thus, although the natural-sampling process is simple and can be easily implemented using analogous techniques, the inherent real-time comparisons involved make it suitable for efficient microprocessor implementation.
2.4.2 Regular Sampled PWM Pattern Generation Regular-sampled PWM is based on a well-defined modulation process. This technique involves updating the sine reference at regular intervals during the triangular carrier cycle; either once or twice per cycle. The basic principles of regular-sampled PWM techniques are shown in Fig. 2.4.1 for asymmetric regular-sampled PWM. Regular-sampling is a digital process of sampling a sinusoidal modulating wave “a,” at regularly spaced intervals to produce sinusoidally weighted digital samples of the modulating wave, represented by “b” in Fig. 2.4.1. As shown in Fig. 2.4.1, two samples of “b” per carrier cycle are generated. The first sample in the carrier cycle is used to sinusoidally modulate the “leading-edge “ of the PWM pulse “c,” and
20 the second sample is used to sinusoidally modulate the “trailing-edge” of the PWM pulse. Thus each edge of the PWM pulse is modulated by a different amount with respect to the regularly spaced pulse centers, hence the terminology “asymmetric” regular-sampled PWM.
(a) M s i n ( w t) M s i n ( ( k + 1 ) T /2 )
M s i n ( k T /2 )
(b)
wt
T /2
T /2
k
Tk
k +1
k
T k +1
(c)
k +1
T k T /2
Fig. 2.4.1 Details of kth pulse in two level regular-sampled asymmetric PWM: (a) Modulating waveform, (b) Regular-sampled waveform, and (c) PWM waveform.
In regular-sampled PWM, pulse-positions are regularly spaced and the pulse-widths precisely defined, such that a simple equation is used to calculate the PWM pulse-widths, which for a sinusoidal modulating wave is of the form [48], [91], k
where,
kT 2
and
k
1T
T 2
MT kT s in s in 4 2
k
1T 2
2 .4 .2
etc. are the sampling time instants, T is the sampling or carrier period,
2
and M is the modulation index. Equation (2.4.2) can be used directly to generate regularsampled PWM in “real-time” using an efficient microprocessor-based software algorithm [97], [98]. The derivation of the switching equations describing symmetric regular-sampled PWM has been given earlier [48], [91], and the main results are given in (2.4.3).
21
k
T
MT
4
k 1
4 T
kT s in 2
MT
4
4
k 1T s in 2
2 .4 .3
These equations are executed in a software algorithm, which simulates the modulation process shown in Fig. 2.4.1, using switching angles k and k+1 defined in (2.4.3). Phase A uses a modulating function
F Tk
kT s in 2
and phase B uses F T k
kT s in 2 2
.
m(tk+1)
Sampled modulating wave m(tk)
m(t) Modulating waveform
m(tk-1)
Regular-sampled waveform
tk-1
tk
k-1
tk+1
k
k+1 PWM waveform
(k-1)Tc
Tc
kTc
Tc
(k+1)Tc
Fig. 2.4.2 Regular-sampled symmetric double edge modulations.
The general features of symmetric regular sampling are illustrated in Fig. 2.4.2. As shown, the process consists of taking samples m(tk) of a modulating wave at regularly spaced time intervals tk = kTc, where Tc corresponds to the sampling (or carrier) time period. These samples of the modulating wave m(tk) are subsequently used to modulate the widths, k, of the PWM waveform. There are, in general, three ways in which the width of the pulse may be modulated by the samples m(tk) as defined in [48]. These can be categorized as either using “single-edge” or “double-edge” modulation. In double-edge modulation, both edges of the pulse are modulated according to m(tk), either “symmetrically” [48] or “asymmetrically” [7], [48], [91], [99], [100], [123]-[126] about the same positions tk = kTc.
22 In the modulation process shown in Fig. 2.4.2 the sampled modulating values m(tk) are used to modulate the PWM pulses symmetrically, with respect to the sampling instants tk = kTc, such that the pulse width k is proportional to sine (for sinusoidal modulation), resulting in each edge of the pulse being modulated equally; hence the term “symmetric-edge” PWM. Asymmetric sampled PWM has been discussed earlier, and therefore in the following paragraphs we will concentrate on symmetric PWM technique. From observation of Fig. 2.4.2 it can be seen that, as the result of this regular-sampling process, the width of the pulse is proportional to the amplitude of each sample m(tk), therefore the area of the pulse is proportional to the area of the modulating wave m(t) over a sampling (or carrier) interval Tc [48]. Moreover, as a consequence of the regular-sampling process, the PWM pulse positions are regularly spaced and the pulse widths are precisely defined such that it is possible to derive a simple trigonometric equation to calculate the PWM pulse width [48]. Using this simple pulse width equation it is possible to generate regular-sampled PWM signal directly in real-time using a microprocessor-based software algorithm [7], [91], [99], [124]-[125]. Alternatively, the simple pulse width equation can be used to model the regular-sampled PWM process for computeraided (CAD) purpose [91], [99], [124].
(a) 0 2/N
2
w t
2
w t
+1
(b) 0 2/N
-1
Fig. 2.4.3 Generation of Three-Level Regular-Sampled PWM, (a) Regular-Sampled Modulating Wave, (b) Three-Level PWM Inverter Voltage.
23 These advantages result directly from the regular-sampling process and are not available in other PWM techniques. The PWM operation of both single-phase and three-phase inverter, using natural and regular-sampled PWM techniques together with their harmonic spectra, has been presented in the literature [7], [48], [91], [122], [123] earlier. The generation of regular sampled PWM using the single-phase bridge inverter is illustrated in Fig. 2.4.3. In this figure, the “three-level” PWM waveform appearing across the single-phase load switches between +1, 0, -1 (for example), with the pulses changing polarity by half-cycle, noting that in practice the amplitude of the PWM waveform is scaled by the inverter dc link voltage. Thus widths of the pulses in each half-cycle need to be related according to the positive half-cycle of the modulating wave [48], [91], [122], [123] as illustrated in Fig. 2.4.3. The details of the generation of the kth pulse in the three-level PWM modulating cycle, shown in Fig. 2.4.3, for a given frequency ratio N is illustrated in Fig. 2.4.4.
(a) M s i n ( w t) M s i n ( (k 2 )/N )
(b)
k -1
k
wt
2 /N
(c)
k Tc ( k 2 ) /N tk
Fig. 2.4.4 Details of kth Pulse in Three Level Regular-Sampled Symmetric PWM, (a) Reference Modulating Signal, (b) Regular-Sample (or Carrier) Signal, and (c) PWM Signal. The equation for the width of the kth pulse, k , can be derived directly form Fig. 2.4.4 simply by converting the kth sampled value of the modulating wave,
M s in t k
, into an appropriate
24 pulse width angle (or equivalent time period) by multiplying (scaling) by the carrier (or sample) period Tc. Thus k T c M sin t k
2 .4 .4
or equivalently k
2
2 M s in k N N
2 .4 .5
where tk represents the sampling time instant, Tc is the carrier (or sampling) period, M is the modulation depth, and N is the frequency ratio. Equation (2.4.4) can be used to generate regular-sampled PWM in real-time using a microprocessor-based software algorithm [7], [125]. As illustrated in (2.4.5), it can be noted that only one sample of the modulating wave m(tk) is needed to calculate a given pulse width k, and these modulating samples s in t k are easily calculated off-line and stored in microprocessor memory (ROM) prior to inverter startup. This is an important feature of regular-sampled PWM, which considerably simplifies the microprocessor implementation [7], [125]. In general only N modulating samples, or N/4 quarter-wave symmetric PWM waveforms, need be stored in memory, and these samples are easily determined off-line for a given PWM frequency ratio (pulse number) N. The “on-line real-time” software generation of both “symmetric” and “asymmetric” regularsampled PWM inverter drive control strategies, using simple pulse width equation of the form of (2.4.4), has been used since 1975, and was first presented in 1981 [7] for 8-bit microprocessor and in 1983 [125] for 16-bit microprocessors. These regular-sampling techniques have been used for many years for both research and industrial PWM controller designs, using both microprocessor software and various LSI implementations.
2.4.3 Optimal PWM Pattern Generation The advantages of using optimized PWM switching strategies are to minimize harmonic distortion, particularly at low frequency ratios [53], [91], [99]. In contrast to natural- and regular-sampled PWM generation, which use practical circuit implementations based on welldefined modulation processes, optimized PWM has to date no identifiable modulation process. It has been usual in the past to generate optimized PWM by first defining a general PWM waveform in terms of a set of switching angles and then to determine these switching angles
25 using numerical methods. As a consequence of this approach, knowledge of the optimized modulation processes involved does not automatically emerge. This has presented practical implementation difficulties in the past, which have now been largely overcome using microprocessor technology, although a number of problems still remain as outlined in the following text. Optimized PWM microprocessor-based generation is essentially memory based, requiring the optimized switching angles to be programmed into ROM prior to generation. A performance criterion, for example, the elimination of low frequency harmonics, or the minimization of harmonic current distortion, peak current etc., results in a set of nonlinear equations in terms of the unknown switching angles. These equations are generally solved using minimization techniques to determine the optimized switching angles. These angles are subsequently programmed into the microprocessor memory in the form of look-up tables, and used to generate PWM waveforms in real-time. Since, in general, the relationship between the switching angles and the fundamental of the modulating voltage is nonlinear, a large number of look-up tables are usually required, each corresponding to a discrete fundamental voltage level. Alternatively some form of interpolation between tables can be used to produce a quasicontinuous fundamental voltage variation. Ideally, one would wish to be able to generate these optimized PWM switching strategies online and in real-time using the computational ability of the microprocessor. However, the lack of an identifiable modulation process, for example, like regular sampling, precludes this possibility. Alternatively, the implementation of the optimization technique currently used offline on the mainframe computer to determine the switching angles in real-time is unlikely to be feasible in the future; even with the more powerful future generation microprocessor. It is this situation, which has led to the new design philosophy outlined in the following paragraph. The philosophy underlying the development of suboptimal PWM is based on the desire to maintain a well-defined modulation process, which can be simply and efficiently implemented in microprocessor software, and yet still produces the desirable characteristics of optimized PWM. Detailed research investigations involving various attempts to construct a modulation process to achieve this effectively have been made. It is clear from these investigations that to reproduce the optimized PWM waveforms by the process of sampling a sinusoidal modulating wave requires a nonlinear sampling process. Although it may be possible to identify and define this nonlinear sampling process, the complexities involved in implementing it in microprocessor would be considerable, and therefore, inconsistent with the proposed deign philosophy. In
26 recognition to these difficulties, it was considered more appropriate to use the well-established asymmetric regular sampling process, and attempt to determine the form of the modulating wave needed to produce the optimized PWM waveform. It was generally felt that asymmetric regular sampling provided a sufficient number of degrees of freedom to ensure that the optimized or very nearly optimized (suboptimal) PWM waveforms could be generated. Although it was recognized early on that using this rarely simple method of sampling to generate optimized PWM would involve a much more complicated nonsinusoidal modulating wave, it was thought this could be accommodated relatively simply in the microprocessor implementation, for example, by a suitable modification of the modulating wave sample values stored in ROM. More importantly, it was hoped that, by using asymmetric regular sampling, a linear relationship between the modulation depth and the fundamental of the optimized PWM waveform would emerge, thus ensuring a simple equation-based software method of generation. The switching angles for each of the various optimal PWM sampled strategies are calculated by the microprocessor using software algorithms based on the appropriate pulse width equation. It has been shown [100] that the nonsinusoidal modulating signal that produces the optimized PWM switching edges for minimized THD, can be closely approximated by modulating signal m(t) consisting of sine wave plus third harmonic, of the form: m t M
1 s in t s in 3 t 4
2 .4 .6
Noting, as shown earlier [100], that the inclusion of additional higher harmonics into equation (2.4.6) does not significantly change the optimized THDs, and therefore does not justify the additional microprocessor implementation complexity. Equation (2.4.6) shows that m(t) is independent of frequency ratio N and varies linearly with modulation depth M. In addition, it has been shown [100] that a linear relationship exists between the fundamental of the PWM voltage and the modulation depth M, up to approximately M = 1.2 p.u., thereby extending the PWM voltage range by approximately 20% before over modulation and pulse-dropping occurs. Based on the sampled version of the modulating wave m(t), defined in equation (2.4.6), the suboptimal PWM pulse-width can be defined as: k
Tc 1 1 m tk 2 2
m t k 1
2 .4 .7
27 where, m(tk) represents the sampled value of m(t) (equation 2.4.6) at time instants tk. Equation (2.4.7) can therefore be used as the basis for a simple microprocessor software algorithm for real-time generation of suboptimal PWM. For the suboptimal PWM strategy each edge of a pulse is modulated by a different amount, as illustrated in Fig. 2.4.5, where the pulse relationships shown in the figure can be defined as: k
Tc
M Tc
4
k 1
4 Tc
4
.F T k
M Tc 4
2 .4 .8
.F T k 1
2 .4 .9
where, the sampled modulating wave F(Tk), representing a sine wave plus third harmonic, is defined by: F tk
s in T k
Using equations (2.4.8) and (2.4.9), the product
1 4
s in 3T k
M Tc
2 .4 .1 0
is determined once only, and used to
4
calculate all the switching instants. The pulse width computation time can further be reduced using the symmetry of the suboptimal PWM waveform.
b
c
k
a
k +1
T k +1
Tk
T k +2
T c /2 Tc
Fig. 2.4.5 Details of Pulse Obtained using Suboptimal Strategy (a) Reference Modulating Signal, (b) Regular-Sample (or Carrier) Signal, and (c) PWM Signal.
28
2.4.4 Three-Level and Two-Level PWM Pattern Generation In a three-level scheme shown in Fig. 2.4.6(b), three values +E, -E and 0 are produced. To derive a discrete time model, the PWM pulse pattern is shown in Fig. 2.4.6(b) is considered, which is the waveform of vin within a sample interval T. One cycle of the 50 Hz reference sine waveform is divided into N equal intervals of duration T as shown in Fig. 2.4.6(a). As shown in Fig. 2.4.6(b), the switching devices are turned on and off during each sampling interval T.
T
k = 0 1 2 3 4 5
N -1 N
t
......
(a ) + E T 0
0 T
-E P o s i ti v e h a l f- c y c l e
N e g a ti v e h a l f- c y c l e
(b )
+E
+E
0
0
-E
-E T
T P o s i ti v e h a l f- c y c l e
N e g a ti v e h a l f- c y c l e
(c)
Fig. 2.4.6 (a) Sinusoidal Reference Signal, (b) Three-Level and (c) Two-Level PWM Pattern.
29 For a two-level switching pattern, only two switching devices are required to produce two values +E and -E. To derive a discrete time model, the PWM pulse pattern shown in Fig. 2.4.6 (c) is considered, which is the waveform of vin within a sample interval T. One cycle of the 50 Hz reference sine waveform is divided into N equal intervals of duration T as shown in Fig. 2.4.6 (a). In this work, both three-level and two-level PWM pulse patterns have been studied. Two-level scheme provides more computation time for the same number of switching per fundamental cycle. This scheme allows the use of higher switching frequency for a given computation time delay, which results in lower total harmonic distortion at the output [127].
2.4.5 Calculation of Pulse Width and Number of pulses A. Three-level PWM Scheme (a )
v = V m s i n ( w t)
(b )
n Vs t 2 /2
t 2 /2 t1 (c)
0 Tc
Fig. 2.4.7 Pulse Width Calculation for Three-Level PWM Pattern (a) Sinusoidal Reference Signal, (b) Sampled Signal, (c) PWM Output Voltage.
The modulation process involved in the generation of symmetric three-level regular sampled PWM waveform is shown in Fig. 2.4.7. A reference fundamental waveform v = Vmsin(t) is considered for sinusoidal pulse width modulation, where, Vm and are the amplitude and modulating frequency of the modulating wave. The voltage waveform is sampled with a sampling time of Tc. The pulse width during each carrier period is determined by making the area under the PWM signal equal to the area under the input-modulating signal, i.e. both the
30 width and the equivalent area under the sinusoidal modulating signal over the carrier (or sampling) period [128]. Thus the sampled voltage V(n) at the nth sampling instant can be obtained by adding the areas A1(n) and A2(n) of the two level PWM as shown in Fig. 2.4.7. A1 n A 2 n V
n Tc
2 .4 .1 1
The fundamental voltage waveform can be represented in discrete time domain as V
n V m s in n T c . Hence equation (2.4.11) can be written as V s t 1 0 .t 2 V m T c sin n T c
2 .4 .1 2
The duration of the positive pulse and zero voltage of the three-level pulses are t1 and t2 respectively. From Fig. 2.4.7
t1 t 2 Tc
. Equation (2.4.12) can be simplified as
V s t 1 V m T c s in n T c o r, t1
Vm Vs
T c s in n T c
o r , t 1 M T c s in n T c w h e re , M
Vm
2 .4 .1 3
is c a lle d m o d u la tio n in d e x .
Vs
Equation (2.4.13) would be used for the positive pulse width calculation in a sampling period of Tc. But for PWM pattern generation using software it needs to calculate the number of pulses present for the duration of pulse width t1. If 256 numbers of samples are considered in a carrier period Tc then the width of a single pulse is given by
Tc 256
2 .4 .1 4
o r, T c 2 5 6
If x is the number of pulses during the time t1 then from equation (2.4.13) and (2.4.14) it can be written as x 2 5 6 . M s in n T c o r , x 2 5 6 M s in n T c
2 .4 .1 5
B. Two-level PWM Scheme The modulation process involved in the generation of symmetric two-level regular sampled PWM waveform is shown in Fig. 2.4.8. A reference fundamental waveform v = Vmsin(t) is considered for sinusoidal pulse width modulation, where, Vm and are the amplitude and modulating frequency of the modulating wave. The voltage waveform is sampled with a
31 sampling time of Tc. The pulse width during each carrier period is determined by making the area under the PWM signal equal to the area under the input-modulating signal, i.e. both the width and the equivalent area under the sinusoidal modulating signal over the carrier (or sampling) period [128]. Thus the sampled voltage V(n) at the nth sampling instant can be obtained by adding the areas A1(n) and A2(n) of the two level PWM as shown in Fig. 2.4.8. A1 n A 2 n V
n Tc
2 .4 .1 6
The fundamental voltage waveform can be represented in discrete time domain as V n V m sin n T c . Hence equation (2.4.16) can be written as V s t 1 V s .t 2 V m T c sin n T c
v = V m s in (w t) (a)
2 .4 .1 7
V (n+ 3 ) V (n+ 2 )
V o l ta g e
V (n+ 1 )
(b) V (n)
n
n+1
n+2 (c)
A 1(n)
n+3 T im e S a m p le s
A 2(n)
+Vs
0 T im e -V s t1
t2 Tc
Fig. 2.4.8 Pulse Width calculation for Two-Level PWM Pattern: (a) Sinusoidal Reference Signal, (b) Sampled Signal, (c) PWM Output Voltage.
The duration of the positive and negative pulses of the two-level PWM schemes are t1 and t2 respectively. From Fig. 2.4.8
t1 t 2 Tc
. Equation (2.4.17) can be simplified as
32 V s t 1 V s T c t 1 V m T c s in n T c o r , 2V s t 1 - V s T c V m T c s in n T c
o r , 2V s t 1 V s T c V m T c s in n T c
Vm o r , 2V s t 1 V s T c 1 s in n T c Vs o r, t1
o r, t1
Tc Vm s in n T c 1 2 Vs Tc 2
w h e re , M
1
M s in n T c Vm
2 .4 .1 8
is c a lle d m o d u la tio n in d e x .
Vs
Equation (2.4.18) would be used for the positive pulse width calculation in a sampling period of Tc. But for PWM pattern generation using software it needs to calculate the number of pulses present for the duration of pulse width t1. If 256 number of samples are considered in a carrier period Tc then the width of a single pulse is given by
Tc 256
2 .4 .1 9
o r, T c 2 5 6
If x is the number of pulses during the time period t1 then from equation (2.4.18) and (2.4.19) it can be written as x
256 2
1 M
s in n T c
o r, x 1 2 8 1 M s in n T c
2 .4 .2 0
2.4.6 Switching Angle and Phase Voltage Calculation A. Three-level PWM Scheme For a two-phase voltage source inverter with the configuration as shown in Fig. 2.4.9, equation (2.4.13) can be used directly for phase A. For phase B, the reference voltage is to be shifted by 900. The ultimate pulse widths for two phases would be t 1 T c M s in n T c A
B t 1 T c M s in n T c 2
2 .4 .2 1 a 2 .4 .2 1 b
where, t1A and t2B are the duration of the positive pulses of phases A and B respectively for the nth sampling instant. For the two-phase voltage source inverter as shown in Fig. 2.4.9, equation
33 (2.4.21a) and (2.4.21b) represents the conduction times of Q1 and Q3 respectively. Transistors Q2 and Q4 conduct in a complementary fashion with Q1 and Q3 respectively. In practice lockout time is incorporated at the switching edges to overcome the probability of dc bus short circuit because of the turn ON of the two switching transistors of one leg simultaneously.
I1 PHASE A
O N
V1
TI
D3
S3
TA
S1
O
C1
Q3
D1
R
Q1
Vs PH ASE B
I2 Q2 C2
Q4
D2
S2
D4
V2
S4
Fig. 2.4.9 Two Phase Half Bridge Voltage Source Inverter for Two Phase Induction Motor.
The actual load voltage applied across a phase of the load is different from the switching pattern of the individual phase transistors. For one carrier period Tc, the output voltage for the above half-bridge inverter will be Vs/2 for duration of t1 and -Vs/2 for duration of t2. The equation for the voltage at phase A can be calculated using the following formulas: Vs
v a 0 .T c
2
o r , v a 0 .T c o r, v a 0
1 2
t 1 0 .t 2 Vs 2
.T c M s in n T c
.V m s in n T c
2 .4 .2 2 a
Similarly, for phase B, the expression of output voltage can be written as follows: vb0
.V m s in n T c 2 2 1
2 .4 .2 2 b
34 B. Two-level PWM Scheme For two-level PWM Scheme all of the above equations hold good, but in a slightly different format. Following the pulse duration equation of two-level PWM Scheme (equation 2.4.18) the equation of switching pulse can be written directly as follows: t1 A
t1 B
Tc 2
1 M
s in n T c
2 .4 .2 3 a
Tc 1 M s in n T c 2 2
2 .4 .2 3 b
The phase voltage for phase A can be calculated as follows: v a 0 .T c
Vs 2
t1 Vs
o r , v a 0 .T c
2
Vs 2 t1
.t 2 Vs 2
. Tc t1
2 .4 .2 4
Using equation (2.4.18) in equation (2.4.24) it can be written as follows: v a 0 .T c V s .
Tc 2
1 M
o r , v a 0 .T c V s . o r, v a 0 V s o r, v a 0
1 2
Tc 2
s in n T c
M s in n T c
Tc V m . s in n T c 2 Vs .V m s in n T c
Vs 2
Tc
2 .4 .2 5 a
Similarly, for phase B, the expression of output voltage can be written as follows: vb0
.V m s in n T c 2 2 1
2 .4 .2 5 b
From the equations (2.4.22a and 2.4.22b) and (2.4.25a and 2.4.25b) it is seen that for both three and two level PWM Schemes the expressions for the output voltages are the same. That is, the output voltages are independent of the level of the PWM schemes. That is why, the current will also remain same for the same applied DC input voltage for both level of PWM schemes.
2.4.7 Current in the R-L Load with a Step Voltage Input Since the output of a voltage-fed inverter is stepped in nature, the general form of current through a series R-L network with a step input voltage is used for computation of the switching points (duty cycles) of the new controller. An R-L network with a step excitation is described in this section.
35 An R-L load is connected in series to a voltage source (with supply voltage Vs) through a switch (Sw) as shown in Fig. 2.4.10.The switch Sw is closed at t = 0. Applying Kirchoff‟s voltage law one can write, Ri L
di
2 .4 .2 6
Vs
dt
t = 0 Sw
R
Vs
i( t)
L
Fig. 2.4.10 A Unit Step Input Voltage applied to an R-L Load. With initial condition: i(t = 0) = I0. In Laplace‟s domain, equation (2.4.26) becomes, R I s L sI s L I 0
Vs
2 .4 .2 7
s
Solving (2.4.27) for I(s) gives, I s
Vs R Ls s L
I0 R
s
L
Vs 1 I0 1 R R R s s s L L
2 .4 .2 8
Inverse transform of equation (2.4.28) yields, i t I0 e
Rt L
1 e R
Vs
Rt
2 .4 .2 9
L
Equation (2.4.29) can be applied to a sampled R-L network. If the sampling time is T and the network current at the nth sample is I(n), then the current at the (n+1)th sample would be, I n 1 I n e
RT L
1 e R
Vs
RT L
2 .4 .3 0
36 Equation (2.4.30) is useful to all sampled R-L networks, where, the supply voltage term Vs would be replaced by the system excitation function.
2.5
Torque for Induction Motors
2.5.1 Formulation By the term torque is meant the turning or twisting moment of a force about an axis. The product of the force and the radius at which this force acts measures the torque. For finding torque equation let us consider a motor shaft of radius r meter acted upon by a circumferential force F Newton (as shown in Fig. 2.5.1), which causes it to rotate at N rps. Then the torque is given by
2 .5 .1
T F r N e w to n -m e te r
Work done by this force in one revolution is given by W
2 .5 .2
F 2 r Jo u le
F r N rps Fig. 2.5.1 The Shaft of a Motor and its cross-sectional view. If the number of revolution in one second is N (i.e. if the speed of rotation of the motor‟s shaft is N rps) then the work done in one second (i.e., the power developed at the shaft) is given by P F 2 p r N J o u le /s e c o n d o r W a tt
F
r 2 N W a tt
T
2 .5 .3
where, = 2N = angular velocity of the motor‟s shaft. Since the electrical power converted into mechanical power in the rotor is due to the presence of back emf, Eb, then if I2 is the rotor current then electrical power is given by Pe
Eb I2
2 .5 .4
Again, the back emf is given by Eb k
where, k is a constant and is the flux per stator pole.
2 .5 .5
37 Equating the above equations the expression of shaft torque is obtained as follows T
k I 2
2 .5 .6
If motor speed remains constant then the torque expression will be as follows T k I 2 /
2 .5 .7
However, there is one more factor that has to be taken into account i.e. the power factor of the rotor. Let, 2 be the angle between rotor emf and rotor current. Then cos2 will be the power factor of the rotor. T k I 2cos 2
2 .5 .8
T I 2 cos 2
2 .5 .9
/
Since k/ is a constant therefore,
2.5.2 Methods of Torque Control in Induction Motor From the discussions in the earlier section it can be inferred that changing flux, or current, or both can control the torque. The theoretical methods to control the torque two-phase induction motors are as follows [129]: 1. Voltage control: This method can be divided into two types. First, the voltage Vb supplied to the winding of phase B may vary from 100 to 0 %, while the voltage Va supplied to the winding of phase A remains constant, and the phase difference angle (PDA) is fixed at 900. Second, the voltages supplied to the windings may vary together, whereas, the amplitudes of the two winding voltages are equal to each other, and the PDA is fixed at 900. Frequency control should be taken into account as the voltages vary in the second method. 2. Phase Difference Angle Control: The PDA between two winding voltages may vary from +900 to -900, whereas, the amplitudes of two voltages are fixed and identical to each other.
The first method of (1) has been used in conventional torque control of two-phase induction motors, and the second method of (1) has rarely been applied to two-phase induction motors by means of already developed inverters [130]. However, the PDA control method of (2) has not been applied until now.
38
2.5.3 Rotating Magnetic Field for Two-Phase Induction Motor The principle of a 2-pole 2-phase stator having two identical windings 90 space degree apart is illustrated in Fig. 2.5.2. N B A
S1
F2
S2 F1
Fig. 2.5.2 Diagram of a simple Two-Phase Three Wire Induction Motor
m
450
900
1350
1800
(b )
(a )
Fig. 2.5.3 (a) The assumed positive direction of fluxes, (b) The assumed sinusoidal flux distribution due to the flow of current in each phase winding. Let 1 and 2 be the instantaneous values of the fluxes set up by the two windings. The resultant flux r at any time is the vector sum of these two fluxes (1 and 2) at that time. Here it is considered the conditions at intervals of 1/8th of a time period i.e. at intervals corresponding to angles of 00, 450, 900, 1350 and 1800. It will be shown that resultant flux r is constant in
39 magnitude i.e. equal to m - the maximum flux due to either phase and is making one revolution/cycle. In other words, it means that the resultant flux rotates synchronously. Case a: When = 00. At this point 1 = 0 but 2 = - m. Hence the resultant flux r = - m. This is shown by a vector pointing downwards in Fig. 2.5.4 (a). Case b: When = 450. At this point 1 = m/2 but 2 = - m/2. Hence the resultant flux r = [(m/2)2 + (m/2)2] = m although this resultant flux is shifted 450 clockwise as shown in Fig. 2.5.4 (b). Case c: When = 900. At this point 1 = m but 2 = 0. Hence the resultant flux r = m, and is further shifted by an angle of 450 clockwise from its position in b as shown by a vector pointing left direction in Fig. 2.5.4 (c).
r = m
(a) = 00
r = m
(b) = 450
r = m
(d) = 1350
r = m
(c) = 900
r = m
(e) = 1800
Fig. 2.5.4 Vector representations of magnetic fluxes for Two-Phase Induction Motor for various instances. Case d: When = 1350. At this point 1 = m/2 but 2 = m/2. Hence the resultant flux r = [(m/2)2 + (m/2)2] = m, and is shifted by another 450 clockwise as in Fig. 2.5.4 (d). Case e: When = 1800. At this point 1 = 0 but 2 = m. Hence the resultant flux r = m, and is further shifted by an angle of 450 clockwise from its position in d or has rotated through an
40 angle of 1800 from its position at the beginning as shown by a vector pointing upward direction in Fig. 2.5.4 (e). Hence it is concluded that 1. the magnitude of the resultant flux is constant and is equal to m - the maximum value of flux due to either phase. 2. the resultant flux rotates at synchronous speed given by NS = 120f/P rpm. However, it should be clearly understood that in this revolving field, there is no actual revolution of the flux. The flux due to each phase changes periodically according to the changes in the phase current but the magnetic flux itself does not move around the stator. It is only the seat of the resultant flux, which keeps on shifting synchronously around the stator. Let us consider the fluxes of two windings be
1 m s in t a n d 2 m c o s t
.
Since the windings are spatially 900 apart from each other, so it can be written as r 1 2 2
2
2
m s in t m c o s t 2
2
m s in t c o s t m 2
2
2
2
2 .5 .1 0
r m
It shows that flux is of constant value and does not change with time.
2.5.4 Torque Equation for Two-Phase Induction Motor Under Balanced Condition It is shown in previous section that the flux in a two-phase induction motor rotates synchronously with a constant magnitude of m if the motor is in balanced condition.
I1
V1
PH ASE A
R
O
TA
TI
O
N
PH ASE B I2 V2
Fig. 2.5.5 Schematic representation of Two-Phase Induction Motor.
41 Figure 2.5.5 shows the schematic representation of two-phase induction motor, where, the windings of phase A are located 900 apart from that of phase B in space. Let the impedances of the two windings are identical. If two voltages, electrically degree apart, are applied to the two windings then current flow through these windings will set up a magnetic flux, which is directly proportional to the rotor emf. The magnetic flux of one winding will interact with the current of the other winding and will produce two oppositely directed torque and hence a net torque, which will ultimately determine the direction of rotation of the motor. Now if we assume that the fundamental voltages applied to the winding of phase A is v1 V1m c o s t
and that to phase B is
v2 V2 m cos t
, where, is the phase angle difference
between the two winding voltages, then the current flowing through the two windings are i1 I 1 m s in t
and
i 2 I 2 m sin t
. Since it is assumed that the two windings are
identical their impedances are also identical. So if voltages V1m and V2m are identical i.e. V 1 m
V2m
Vm
, then current will also be identical in magnitude i.e. I 1 m
I2m
Im
. If
is fixed at 900, these voltage expressions represent the two balanced winding voltages in the voltage control wherein the motor torque is controlled by the voltage amplitude and frequency. This method of operation is regarded as a balanced operation. If V1m is constant and is fixed at 900, these expressions represent the two winding voltages in a typical servo system of two-phase induction motors wherein the motor torque is controlled by the voltage V2m. On the other hand, if V1m and V2m are constant and identical, these expressions represent the two winding voltages in the PDA control wherein the motor torque is controlled by the PDA between two winding voltages. Incorporating the phase modulation index Z with the PDA will do this. This will be discussed later in this chapter. These two methods of operation are regarded as an unbalanced operation. Now, the net torque developed is T 1 i 2 2 i1 V 1 m c o s t I 2 m s in t V 2 m c o s t I 1 m s in t V m I m c o s t s in t c o s t s in t
Vm Im 2
Vm Im 2
s in 2 t s in s in 2 t s in s in s in
Vm Im 2
s in s in
42
Vm Im 2
2 c o s s in 2 .5 .1 1
V m I m c o s s in
Therefore, torque depends on the phase angle between the two windings, and it varies sinusoidally with the phase angle, . If is positive then torque is negative i.e. the motor rotates in the reverse direction, and if is negative then torque is positive i.e. the motor rotates in the forward direction. If = 900 then torque becomes maximum and is given by T
2 .5 .1 2
- Vm I m cos
Since flux is directly proportional to the applied voltages, it is obvious that the torque will be directly proportional to the flux, current and power factor of any winding.
2.5.5 Torque Equation for Two-Phase Induction Motor Under Unbalanced Condition The torque of the two-phase induction motors under unbalanced operation can be analyzed by a symmetrical coordinate method invented by Fortesque [5].
r1
Iaf
x1
x2
V af
V af1
xm
V ab
V ab1
xm
r 2 /s
Va
r1
Iab
x1
r 2 /( 2 -s)
x2
Fig. 2.5.6 Equivalent circuit for Two-Phase Induction Motor under unbalanced condition in terms of Phase A
Figure 2.5.6 shows the equivalent circuit of phase A winding of the two-phase induction motor under unbalanced conditions. The phase voltage is composed of the forward voltage V1f and backward voltage V1b, which correspond to the forward and backward revolving field respectively. Similarly, the equivalent circuit of phase B has the forward and backward voltages
43 V2f and V2b. As shown in Fig. 2.5.6, the relationship between the forward voltages V1f and V2f of two phases are balanced as V2f = jV1f. The same is true for the backward voltages, that is, V2b = jV1b. The two revolving fields rotate in opposite directions with respect to each other. Thus, the two winding voltages V1 and V2 are expressed in terms of V1f and V1b as follows: V1
V1 f
V2
jV 1 f
2 .5 .1 3 a
V 1b
2 .5 .1 3 b
- jV 1 b
Therefore, if V1 and V2 are known, V1f and V1b can be expressed as follows:
V1 f
V1b
V 1 - jV 2
V 1 1 - jK e
j
2
2
V 1 jV 2
V 1 1 jK e
2
j
2 .5 .1 4 a
2 .5 .1 4 b
2
The torque generated by each component can be easily evaluated. Their algebraic sum becomes the net internal torque, and is expressed as follows: r2 r2 2 2 s 2 s V 2 T0 V af 1 ab 1 2 2 r r2 2 2 2 x2 x2 s 2 s
2 .5 .1 5
where, Vaf1 and Vab1 are the amplitude of the voltage induced by the forward and backward revolving field, respectively, and their squares are expressed as follows: K , C s x mV a
2
2 .5 .1 6 a
V a b 1 Ab K , D s x m V a
2
2 .5 .1 6 b
V af 1 A f 2
2
2
2
w h e re , 2
C
s
r2 2 x2 s
r1 r2 x1 x 2 x m s
x2 xm r1 x 2 x m 2
r x1 x m 2 s 2
2 .1 7 a
2
2
r2 2 x2 2 s
D s r1 r2 x1 x 2 x m 2 s
x2 xm r1 x 2 x m 2
r2 x1 x m 2 s 2
2
2 .1 7 b
44
Af
K ,
1 K
2
2 K s in
2 .5 .1 8 a
4
Ab K ,
and K
1 K
2
2 K s in
2 .5 .1 8 b
4 Vb
2 .5 .1 9
Va
Substitution of (2.5.16 a) and (2.5.16 b) into (2.5.15) yields the following equations:
T0
2
x mV a
2
A f
r2
K ,C s
s 2
r2 2 x2 s
2 s Ab K , D s 2 r2 2 x2 2 s r2
2 .5 .2 0
The first term in (2.5.20) shows the positive component of the torque generated in two-phase induction motors, and the second term shows the negative component.
2.5.6 Torque-Speed Characteristics of Two-Phase Induction Motor Under Unbalanced condition Using (2.5.20), the torque generated in two-phase induction motors under several control methods is analyzed on a test motor (p = 2, r1 = 117, x1 = 125, xm = 828, r2 = 517, x2 = 15.6, f = 60Hz, Va = Vb = 100V). Figure 2.5.7 shows the speed-torque curves of the test motor under several control methods. Torque characteristic under the balanced voltage control is shown in Fig. 2.5.7(a), in which the two winding voltages and frequency vary under the constant volt/hertz ratio (V/f = 5/3), and is fixed at 900. Torque characteristic under the unbalanced voltage control is shown in Fig. 2.5.7(b), in which the voltage of phase B is varied and the voltage and frequency of phase A is fixed. Torque characteristic under the phase difference angle control is shown in Fig. 2.5.7(c), in which is varied and the two winding voltages are fixed. The phase difference angle control of Fig. 2.5.7(c) shows several features in its torque characteristic. First, for a negative phase angle, the motor can be made to operate in quadrant III to where the other methods cannot reach. This feature of the PDA control enables a two-phase induction motor to easily reverse the rotating direction by changing the PDA. An excellent braking capability is another feature of the PDA control. The inherent capability of the plugging operation can be exploited to shorten the braking time to a standstill.
45
8
6
V a= 10 0V
T o rq u e in N -c m
80V
4
60V 40V 20V
2
0
-2 -1
-0 . 5
0
(a )
0.5
1
S p e e d in p .u .
8 K=1
6
T o rq u e in N -c m
0 .8
4
0 .6 0 .4
2
0 .2 0
0
-2 -1
(b )
-0 .5
0
0 .5
1
S p e e d in p .u .
8 =90
6
=72 =54
T o rq u e in N -c m
4
=36
2 =18
0
=0 = -1 8
-2
= -3 6
-4 = -9 0
= -5 4
-6 = -7 2
-8 -1
-0 . 5 (c)
0
0.5
1
S p e e d in p .u .
Fig. 2.5.7 Torque-Speed Characteristics of a Two-Phase Induction Motor. (a) voltage in phase A, (b) voltage in phase B, (c) phase angle between phase A and B.
46
2.6
Simulation of PWM Pattern for Two-Phase Induction Motor
The proposed system is first simulated using MATLAB. Two different programs are written in MATLAB for two different level of PWM schemes: three level and two level PWM schemes. Both of these programs generate the PWM patterns for phase A and phase B as well as harmonic spectrum for phase A. The program also calculates distortion factors for both phases. The harmonic spectrum and PWM patterns are given in Figs. 2.6.1-2.6.32 and the calculated distortion factors are given in tables 2.6.1-2.6.4. Finally the plots of distortion factors versus
Amplitude (p.u.)
various parameters are given in Figs. 2.6.33-2.6.36.
1 0.5 0 0
500
1000
Amplitude (p.u.)
Amplitude (p.u.)
(a)
1500 Frequency (Hz)
2000
2500
1 0 -1 0 (b)
0.005
0.01 Time (sec)
0.015
0.02
0.005
0.01 Time (sec)
0.015
0.02
1 0 -1 0 (c)
Fig. 2.6.1 MATLAB Simulation results of the three level scheme. (a) Harmonic Spectrum of phase A, (b) PWM Pattern of phase A, (c) PWM Pattern of phase B with f = 50 Hz, fc = 1400 Hz, M = 1.0, Z = 1.0 and N = 28.
Amplitude (p.u.)
Amplitude (p.u.)
Amplitude (p.u.)
47 1 0.5 0 0
(a)
500
1000
1500 Frequency (Hz)
2000
2500
1 0 -1 0 (b)
0.002
0.004
0.006
0.008 0.01 Time (sec)
0.012
0.014
0.016
0.002
0.004
0.006
0.008 0.01 Time (sec)
0.012
0.014
0.016
1 0 -1 0
(c)
Fig. 2.6.2 MATLAB Simulation results of the three level scheme. (a) Harmonic Spectrum of phase A, (b) PWM Pattern of phase A, (c) PWM Pattern of phase B with f = 60 Hz, fc = 1400
Amplitude (p.u.)
Amplitude (p.u.)
Amplitude (p.u.)
Hz, M = 1.0, Z = 1.0 and N = 23.
1 0.5 0 0
(a)
500
1000
1500 Frequency (Hz)
2000
2500
1 0 -1 0 (b)
0.002
0.004
0.006 0.008 Time (sec)
0.01
0.012
0.014
0.002
0.004
0.006 0.008 Time (sec)
0.01
0.012
0.014
1 0 -1 0
(c)
Fig. 2.6.3 MATLAB Simulation results of the three level scheme. (a) Harmonic Spectrum of phase A, (b) PWM Pattern of phase A, (c) PWM Pattern of phase B with f = 70 Hz, fc = 1400 Hz, M = 1.0, Z = 1.0 and N = 20.
Amplitude (p.u.)
Amplitude (p.u.)
Amplitude (p.u.)
48 1 0.5 0 0 (a)
500
1000
1500 2000 Frequency (Hz)
2500
3000
1 0 -1 0 (b)
0.005
0.01 Time (sec)
0.015
0.02
0.005
0.01 Time (sec)
0.015
0.02
1 0 -1 0 (c)
Fig. 2.6.4 MATLAB Simulation results of the three level scheme. (a) Harmonic Spectrum of phase A, (b) PWM Pattern of phase A, (c) PWM Pattern of phase B with f = 50 Hz, fc = 1600
Amplitude (p.u.)
Amplitude (p.u.)
Amplitude (p.u.)
Hz, M = 1.0, Z = 1.0 and N = 32.
1 0.5 0 0
(a)
500
1000
1500 2000 Frequency (Hz)
2500
3000
1 0 -1 0 (b)
0.002
0.004
0.006
0.008 0.01 Time (sec)
0.012
0.014
0.016
0.002
0.004
0.006
0.008 0.01 Time (sec)
0.012
0.014
0.016
1 0 -1 0 (c)
Fig. 2.6.5 MATLAB Simulation results of the three level scheme. (a) Harmonic Spectrum of phase A, (b) PWM Pattern of phase A, (c) PWM Pattern of phase B with f = 60 Hz, fc = 1600 Hz, M = 1.0, Z = 1.0 and N = 27.
Amplitude (p.u.)
Amplitude (p.u.)
Amplitude (p.u.)
49 1 0.5 0 0 (a)
500
1000
1500 2000 Frequency (Hz)
2500
3000
1 0 -1 0 (b)
0.002
0.004
0.006 0.008 Time (sec)
0.01
0.012
0.014
0.002
0.004
0.006 0.008 Time (sec)
0.01
0.012
0.014
1 0 -1 0
(c)
Fig. 2.6.6 MATLAB Simulation results of the three level scheme. (a) Harmonic Spectrum of phase A, (b) PWM Pattern of phase A, (c) PWM Pattern of phase B with f = 70 Hz, fc = 1600
Amplitude (p.u.)
Amplitude (p.u.)
Amplitude (p.u.)
Hz, M = 1.0, Z = 1.0 and N = 23.
1 0.5 0 0
(a)
500
1000
1500 Frequency (Hz)
2000
2500
1 0 -1 0 (b)
0.005
0.01 Time (sec)
0.015
0.02
0.005
0.01 Time (sec)
0.015
0.02
1 0 -1 0 (c)
Fig. 2.6.7 MATLAB Simulation results of the three level scheme. (a) Harmonic Spectrum of phase A, (b) PWM Pattern of phase A, (c) PWM Pattern of phase B with f = 50 Hz, fc = 1400 Hz, M = 0.9, Z = 1.0 and N = 28.
Amplitude (p.u.)
Amplitude (p.u.)
Amplitude (p.u.)
50 1 0.5 0 0
(a)
500
1000
1500 Frequency (Hz)
2000
2500
1 0 -1 0
(b)
0.005
0.01 Time (sec)
0.015
0.02
0.005
0.01 Time (sec)
0.015
0.02
1 0 -1 0 (c)
Fig. 2.6.8 MATLAB Simulation results of the three level scheme. (a) Harmonic Spectrum of phase A, (b) PWM Pattern of phase A, (c) PWM Pattern of phase B with f = 50 Hz, fc = 1400
Amplitude (p.u.)
Amplitude (p.u.)
Amplitude (p.u.)
Hz, M = 0.8, Z = 1.0 and N = 28.
1 0.5 0 0
(a)
500
1000
1500 2000 Frequency (Hz)
2500
3000
1 0 -1 0
(b)
0.005
0.01 Time (sec)
0.015
0.02
0.005
0.01 Time (sec)
0.015
0.02
1 0 -1 0 (c)
Fig. 2.6.9 MATLAB Simulation results of the three level scheme. (a) Harmonic Spectrum of phase A, (b) PWM Pattern of phase A, (c) PWM Pattern of phase B with f = 50 Hz, fc = 1600 Hz, M = 0.9, Z = 1.0 and N = 32.
Amplitude (p.u.)
Amplitude (p.u.)
Amplitude (p.u.)
51 1 0.5 0 0
(a)
500
1000
1500 2000 Frequency (Hz)
2500
3000
1 0 -1 0
(b)
0.005
0.01 Time (sec)
0.015
0.02
0.005
0.01 Time (sec)
0.015
0.02
1 0 -1 0
(c)
Fig. 2.6.10 MATLAB Simulation results of the three level scheme. (a) Harmonic Spectrum of phase A, (b) PWM Pattern of phase A, (c) PWM Pattern of phase B with f = 50 Hz, fc = 1600
Amplitude (p.u.)
Amplitude (p.u.) Amplitude (p.u.)
Hz, M = 0.8, Z = 1.0 and N = 32.
1 0.5 0 0
(a)
500
1000 Frequency (Hz)
1500
2000
0.005
0.01 Time (sec)
0.015
0.02
0.005
0.01 Time (sec)
0.015
0.02
1 0 -1 0
(b)
1 0 -1 0
(c)
Fig. 2.6.11 MATLAB Simulation results of the three level scheme. (a) Harmonic Spectrum of phase A, (b) PWM Pattern of phase A, (c) PWM Pattern of phase B with f = 50 Hz, fc = 1000 Hz, M = 1.0, Z = 1.0 and N = 20.
Amplitude (p.u.)
Amplitude (p.u.)
Amplitude (p.u.)
52 1 0.5 0 0
(a)
500
1000 1500 Frequency (Hz)
2000
1 0 -1 0
(b)
0.005
0.01 Time (sec)
0.015
0.02
0.005
0.01 Time (sec)
0.015
0.02
1 0 -1 0 (c)
Fig. 2.6.12 MATLAB Simulation results of the three level scheme. (a) Harmonic Spectrum of phase A, (b) PWM Pattern of phase A, (c) PWM Pattern of phase B with f = 50 Hz, fc = 1200
Amplitude (p.u.)
Amplitude (p.u.) Amplitude (p.u.)
Hz, M = 1.0, Z = 1.0 and N = 24.
1 0.5 0 0
(a)
500
1000
1500 Frequency (Hz)
2000
2500
1 0 -1 0
(b)
0.005
0.01 Time (sec)
0.015
0.02
0.015
0.02
1 0 -1 0
(c)
0.005
0.01 Time (sec)
Fig. 2.6.13 MATLAB Simulation results of the three level scheme. (a) Harmonic Spectrum of phase A, (b) PWM Pattern of phase A, (c) PWM Pattern of phase B with f = 50 Hz, fc = 1400 Hz, M = 1.0, Z = 0.5 and N = 28.
Amplitude (p.u.)
Amplitude (p.u.)
Amplitude (p.u.)
53 1 0.5 0 0
(a)
500
1000
1500 Frequency (Hz)
2000
2500
1 0 -1 0
(b)
0.005
0.01 Time (sec)
0.015
0.02
0.005
0.01 Time (sec)
0.015
0.02
1 0 -1 0
(c)
Fig. 2.6.14 MATLAB Simulation results of the three level scheme. (a) Harmonic Spectrum of phase A, (b) PWM Pattern of phase A, (c) PWM Pattern of phase B with f = 50 Hz, fc = 1400
Amplitude (p.u.)
Amplitude (p.u.)
Amplitude (p.u.)
Hz, M = 1.0, Z = 0.0 and N = 28.
1 0.5 0 0
(a)
500
1000
1500 Frequency (Hz)
2000
2500
1 0 -1 0
(b)
0.005
0.01 Time (sec)
0.015
0.02
0.005
0.01 Time (sec)
0.015
0.02
1 0 -1 0 (c)
Fig. 2.6.15 MATLAB Simulation results of the three level scheme. (a) Harmonic Spectrum of phase A, (b) PWM Pattern of phase A, (c) PWM Pattern of phase B with f = 50 Hz, fc = 1400 Hz, M = 1.0, Z = -0.5 and N = 28
Amplitude (p.u.)
Amplitude (p.u.)
Amplitude (p.u.)
54 1 0.5 0 0 (a)
500
1000
1500 Frequency (Hz)
2000
2500
1 0 -1 0
(b)
0.005
0.01 Time (sec)
0.015
0.02
0.005
0.01 Time (sec)
0.015
0.02
1 0 -1 0
(c)
Fig. 2.6.16 MATLAB Simulation results of the three level scheme. (a) Harmonic Spectrum of phase A, (b) PWM Pattern of phase A, (c) PWM Pattern of phase B with f = 50 Hz, fc = 1400
Amplitude (p.u.)
Amplitude (p.u.) Amplitude (p.u.)
Hz, M = 1.0, Z = -1.0 and N = 28.
1 0.5 0 0 (a)
500
1000
1500 Frequency (Hz)
2000
2500
1 0 -1 0
(b)
0.005
0.01 Time (sec)
0.015
0.02
0.005
0.01 Time (sec)
0.015
0.02
1 0 -1 0
(c)
Fig. 2.6.17 MATLAB Simulation results of the two level scheme. (a) Harmonic Spectrum of phase A, (b) PWM Pattern of phase A, (c) PWM Pattern of phase B with f = 50 Hz, fc = 1400 Hz, M = 1.0, Z = 1.0 and N = 28.
Amplitude (p.u.)
Amplitude (p.u.)
Amplitude (p.u.)
55 1 0.5 0 0 (a)
500
1000 1500 Frequency (Hz)
2000
2500
1 0 -1 0
(b)
0.002
0.004
0.006
0.008 0.01 Time (sec)
0.012
0.014
0.016
0.002
0.004
0.006
0.008 0.01 Time (sec)
0.012
0.014
0.016
1 0 -1 0 (c)
Fig. 2.6.18 MATLAB Simulation results of the two level scheme. (a) Harmonic Spectrum of phase A, (b) PWM Pattern of phase A, (c) PWM Pattern of phase B with f = 60 Hz, fc = 1400
Amplitude (p.u.)
Amplitude (p.u.)
Amplitude (p.u.)
Hz, M = 1.0, Z = 1.0 and N = 23.
1 0.5 0 0
(a)
500
1000
1500 Frequency (Hz)
2000
2500
1 0 -1 0
(b)
0.002
0.004
0.006 0.008 Time (sec)
0.01
0.012
0.014
0.002
0.004
0.006 0.008 Time (sec)
0.01
0.012
0.014
1 0 -1 0
(c)
Fig. 2.6.19 MATLAB Simulation results of the two level scheme. (a) Harmonic Spectrum of phase A, (b) PWM Pattern of phase A, (c) PWM Pattern of phase B with f = 70 Hz, fc = 1400 Hz, M = 1.0, Z = 1.0 and N = 20.
Amplitude (p.u.)
Amplitude (p.u.)
Amplitude (p.u.)
56 1 0.5 0 0
(a)
500
1000
1500 2000 Frequency (Hz)
2500
3000
1 0 -1 0
(b)
0.005
0.01 Time (sec)
0.015
0.02
0.005
0.01 Time (sec)
0.015
0.02
1 0 -1 0
(c)
Fig. 2.6.20 MATLAB Simulation results of the two level scheme. (a) Harmonic Spectrum of phase A, (b) PWM Pattern of phase A, (c) PWM Pattern of phase B with f = 50 Hz, fc = 1600
Amplitude (p.u.)
Amplitude (p.u.)
Amplitude (p.u.)
Hz, M = 1.0, Z = 1.0 and N = 32.
1 0.5 0 0
(a)
500
1000
1500 2000 Frequency (Hz)
2500
3000
1 0 -1 0
(b)
0.002
0.004
0.006
0.008 0.01 Time (sec)
0.012
0.014
0.016
0.002
0.004
0.006
0.008 0.01 Time (sec)
0.012
0.014
0.016
1 0 -1 0
(c)
Fig. 2.6.21 MATLAB Simulation results of the two level scheme. (a) Harmonic Spectrum of phase A, (b) PWM Pattern of phase A, (c) PWM Pattern of phase B with f = 60 Hz, fc = 1600 Hz, M = 1.0, Z = 1.0 and N = 27.
Amplitude (p.u.)
Amplitude (p.u.)
Amplitude (p.u.)
57 1 0.5 0 0 (a)
500
1000
1500 2000 Frequency (Hz)
2500
3000
1 0 -1 0
(b)
0.002
0.004
0.006 0.008 Time (sec)
0.01
0.012
0.014
0.002
0.004
0.006 0.008 Time (sec)
0.01
0.012
0.014
1 0 -1 0
(c)
Fig. 2.6.22 MATLAB Simulation results of the two level scheme. (a) Harmonic Spectrum of phase A, (b) PWM Pattern of phase A, (c) PWM Pattern of phase B with f = 70 Hz, fc = 1600
Amplitude (p.u.)
Amplitude (p.u.)
Amplitude (p.u.)
Hz, M = 1.0, Z = 1.0 and N = 23.
1 0.5 0 0
(a)
500
1000
1500 Frequency (Hz)
2000
2500
1 0 -1 0
(b)
0.005
0.01 Time (sec)
0.015
0.02
0.005
0.01 Time (sec)
0.015
0.02
1 0 -1 0
(c)
Fig. 2.6.23 MATLAB Simulation results of the two level scheme. (a) Harmonic Spectrum of phase A, (b) PWM Pattern of phase A, (c) PWM Pattern of phase B with f = 50 Hz, fc = 1400 Hz, M = 0.9, Z = 1.0 and N = 28.
Amplitude (p.u.)
Amplitude (p.u.)
Amplitude (p.u.)
58 1 0.5 0 0 (a)
500
1000
1500 Frequency (Hz)
2000
2500
1 0 -1 0
(b)
0.005
0.01 Time (sec)
0.015
0.02
0.005
0.01 Time (sec)
0.015
0.02
1 0 -1 0
(c)
Fig. 2.6.24 MATLAB Simulation results of the two level scheme. (a) Harmonic Spectrum of phase A, (b) PWM Pattern of phase A, (c) PWM Pattern of phase B with f = 50 Hz, fc = 1400
Amplitude (p.u.)
Amplitude (p.u.)
Amplitude (p.u.)
Hz, M = 0.8, Z = 1.0 and N = 28.
1 0.5 0 0
(a)
500
1000
1500 2000 Frequency (Hz)
2500
3000
1 0 -1 0
(b)
0.005
0.01 Time (sec)
0.015
0.02
0.005
0.01 Time (sec)
0.015
0.02
1 0 -1 0
(c)
Fig. 2.6.25 MATLAB Simulation results of the two level scheme. (a) Harmonic Spectrum of phase A, (b) PWM Pattern of phase A, (c) PWM Pattern of phase B with f = 50 Hz, fc = 1600 Hz, M = 0.9, Z = 1.0 and N = 32.
Amplitude (p.u.)
Amplitude (p.u.)
Amplitude (p.u.)
59 1 0.5 0 0
(a)
500
1000
1500 2000 Frequency (Hz)
2500
3000
1 0 -1 0
(b)
0.005
0.01 Time (sec)
0.015
0.02
0.005
0.01 Time (sec)
0.015
0.02
1 0 -1 0
(c)
Fig. 2.6.26 MATLAB Simulation results of the two level scheme. (a) Harmonic Spectrum of phase A, (b) PWM Pattern of phase A, (c) PWM Pattern of phase B with f = 50 Hz, fc = 1600
Amplitude (p.u.)
Amplitude (p.u.)
Amplitude (p.u.)
Hz, M = 0.8, Z = 1.0 and N = 32.
1 0.5 0 0
(a)
500
1000 Frequency (Hz)
1500
2000
0.005
0.01 Time (sec)
0.015
0.02
0.005
0.01 Time (sec)
0.015
0.02
1 0 -1 0
(b)
1 0 -1 0
(c)
Fig. 2.6.27 MATLAB Simulation results of the two level scheme. (a) Harmonic Spectrum of phase A, (b) PWM Pattern of phase A, (c) PWM Pattern of phase B with f = 50 Hz, fc = 1000 Hz, M = 1.0, Z = 1.0 and N = 20.
Amplitude (p.u.)
Amplitude (p.u.)
Amplitude (p.u.)
60 1 0.5 0 0
(a)
500
1000 1500 Frequency (Hz)
2000
1 0 -1 0
(b)
0.005
0.01 Time (sec)
0.015
0.02
0.005
0.01 Time (sec)
0.015
0.02
1 0 -1 0
(c)
Fig. 2.6.28 MATLAB Simulation results of the two level scheme. (a) Harmonic Spectrum of phase A, (b) PWM Pattern of phase A, (c) PWM Pattern of phase B with f = 50 Hz, fc = 1200
Amplitude (p.u.)
Amplitude (p.u.)
Amplitude (p.u.)
Hz, M = 1.0, Z = 1.0 and N = 24.
1 0.5 0 0
(a)
500
1000
1500 Frequency (Hz)
2000
2500
1 0 -1 0
(b)
0.005
0.01 Time (sec)
0.015
0.02
0.005
0.01 Time (sec)
0.015
0.02
1 0 -1 0
(c)
Fig. 2.6.29 MATLAB Simulation results of the two level scheme. (a) Harmonic Spectrum of phase A, (b) PWM Pattern of phase A, (c) PWM Pattern of phase B with f = 50 Hz, fc = 1400 Hz, M = 1.0, Z = 0.5 and N = 28.
Amplitude (p.u.)
Amplitude (p.u.)
Amplitude (p.u.)
61 1 0.5 0 0
(a)
500
1000
1500 Frequency (Hz)
2000
2500
1 0 -1 0 (b)
0.005
0.01 Time (sec)
0.015
0.02
0.005
0.01 Time (sec)
0.015
0.02
1 0 -1 0
(c)
Fig. 2.6.30 MATLAB Simulation results of the two level scheme. (a) Harmonic Spectrum of phase A, (b) PWM Pattern of phase A, (c) PWM Pattern of phase B with f = 50 Hz, fc = 1400
Amplitude (p.u.)
Amplitude (p.u.)
Amplitude (p.u.)
Hz, M = 1.0, Z = 0.0 and N = 28.
1 0.5 0 0
(a)
500
1000
1500 Frequency (Hz)
2000
2500
1 0 -1 0
(b)
0.005
0.01 Time (sec)
0.015
0.02
0.005
0.01 Time (sec)
0.015
0.02
1 0 -1 0
(c)
Fig. 2.6.31 MATLAB Simulation results of the two level scheme. (a) Harmonic Spectrum of phase A, (b) PWM Pattern of phase A, (c) PWM Pattern of phase B with f = 50 Hz, fc = 1400 Hz, M = 1.0, Z = -0.5 and N = 28.
Amplitude (p.u.)
Amplitude (p.u.)
Amplitude (p.u.)
62 1 0.5 0 0
(a)
500
1000
1500 Frequency (Hz)
2000
2500
1 0 -1 0 (b)
0.005
0.01 Time (sec)
0.015
0.02
0.005
0.01 Time (sec)
0.015
0.02
1 0 -1 0
(c)
Fig. 2.6.32 MATLAB Simulation results of the two level scheme. (a) Harmonic Spectrum of phase A, (b) PWM Pattern of phase A, (c) PWM Pattern of phase B with f = 50 Hz, fc = 1400 Hz, M = 1.0, Z = -1.0 and N = 28.
Table 2.6.1 Distortion factors in switching patterns of three and two level PWM scheme for phase A and phase B of a two phase voltage source inverter with the variation of fundamental frequency (f) for fc = 1400 and 1600 Hz, M = 1.0 and Z = 1.0. For three level PWM scheme fc = 1400 Hz f
DF_A
DF_B
fc = 1600 Hz DF_A
DF_B
For two level PWM scheme fc = 1400 Hz DF_A
DF_B
fc = 1600 Hz DF_A
DF_B
10 Hz
0.0007 0.0007 0.0006 0.0006 0.0004 0.0004 0.0001 0.0001
20Hz
0.0007 0.0007 0.0007 0.0007 0.0004 0.0005 0.0002 0.0002
30 Hz
0.0009 0.0008 0.0008 0.0008 0.0007 0.0006 0.0004 0.0005
40 Hz
0.0010 0.0011 0.0010 0.0010 0.0009 0.0008 0.0006 0.0006
50 Hz
0.0014 0.0014 0.0011 0.0011 0.0013 0.0013 0.0009 0.0009
60 Hz
0.0016 0.0017 0.0012 0.0012 0.0020 0.0016 0.0014 0.0015
70 Hz
0.0022 0.0022 0.0016 0.0017 0.0024 0.0024 0.0020 0.0016
80 Hz
0.0023 0.0022 0.0022 0.0022 0.0031 0.0030 0.0024 0.0024
90 Hz
0.0028 0.0028 0.0023 0.0022 0.0038 0.0038 0.0031 0.0030
100 Hz 0.0035 0.0033 0.0028 0.0028 0.0052 0.0050 0.0038 0.0038
63
Table 2.6.2 Distortion factors in switching patterns of three and two level PWM scheme for phase A and phase B of a two phase voltage source inverter with the variation of modulation index (M) for f = 50 Hz, fc = 1400 and 1600 Hz and Z = 1.0. For three level PWM scheme fc = 1400 Hz M
DF_A
DF_B
fc = 1600 Hz DF_A
DF_B
For two level PWM scheme fc = 1400 Hz DF_A
DF_B
fc = 1600 Hz DF_A
DF_B
0.1 0.0045 0.0045 0.0053 0.0053 0.0165 0.0165 0.0129 0.0129 0.2 0.0037 0.0037 0.0020 0.0020 0.0077 0.0077 0.0060 0.0060 0.3 0.0027 0.0027 0.0020 0.0020 0.0053 0.0053 0.0039 0.0039 0.4 0.0019 0.0019 0.0020 0.0020 0.0037 0.0037 0.0029 0.0029 0.5 0.0019 0.0019 0.0014 0.0014 0.0029 0.0029 0.0022 0.0022 0.6 0.0017 0.0017 0.0012 0.0012 0.0025 0.0025 0.0018 0.0018 0.7 0.0014 0.0014 0.0014 0.0014 0.0019 0.0019 0.0014 0.0014 0.8 0.0012 0.0012 0.0011 0.0011 0.0016 0.0016 0.0012 0.0012 0.9 0.0012 0.0012 0.0008 0.0008 0.0014 0.0014 0.0011 0.0011
Table 2.6.3 Distortion factors in switching patterns of three and two level PWM scheme for phase A and phase B of a two phase voltage source inverter with the variation of carrier frequency (fc) for f = 50 Hz, M = 1.0 and Z = 1.0. For three level PWM scheme For two level PWM scheme fc
DF_A
DF_B
DF_A
DF_B
800 Hz
0.0028
0.0028
0.0038
0.0038
1000 Hz
0.0022
0.0022
0.0024
0.0024
1200 Hz
0.0016
0.0016
0.0017
0.0017
1400 Hz
0.0014
0.0014
0.0013
0.0013
1600 Hz
0.0011
0.0011
0.0009
0.0009
1800 Hz
0.0010
0.0010
0.0007
0.0007
64 Table 2.6.4 Distortion factors in switching patterns of three and two level PWM scheme for phase A and phase B of a two phase voltage source inverter with the variation of phase modulation index (Z) for f = 50 Hz, fc = 1400 Hz and M = 1.0. For three level PWM scheme For two level PWM scheme Z
DF_A
DF_B
DF_A
DF_B
-1.0
0.0014
0.0014
0.0013
0.0013
-0.75
0.0014
0.0012
0.0013
0.0013
-0.50
0.0014
0.0011
0.0013
0.0013
-0.25
0.0014
0.0012
0.0013
0.0013
0.0
0.0014
0.0014
0.0013
0.0013
0.25
0.0014
0.0012
0.0013
0.0013
0.50
0.0014
0.0011
0.0013
0.0013
0.75
0.0014
0.0012
0.0013
0.0013
1.0
0.0014
0.0014
0.0013
0.0013
0 .0 0 6
D i s to rti o n F a c t o rs
0 .0 0 5
0 .0 0 4
0 .0 0 3
0 .0 0 2
0 .0 0 1
0 0
10
20
30
40
50
60
70
80
90
100
F u n d a m e n ta l F r e q u e n c y ( H z )
(a )
(b )
(c )
(d )
Fig. 2.6.33 Plot of Distortion Factors (DF) vs Fundamental Frequency (f) for different level of PWM schemes: (a) 3-level fc = 1400 Hz, (b) 3-level for fc = 1600 Hz, (c) 2-level for fc = 1400 Hz, (d) 2-level for fc = 1400 Hz for phase A of a 2-phase VSI with M = 1.0 and Z = 1.0.
65 0 .0 1 8
0 .0 1 6
D i s to rti o n F a c t o rs
0 .0 1 4
0 .0 1 2
0 .0 1
0 .0 0 8
0 .0 0 6
0 .0 0 4
0 .0 0 2
0 0
0 .1
0 .2
0 .3
0 .4
0 .5
0 .6
0 .7
0 .8
0 .9
1
M o d u la tio n In d e x
(a )
(b )
(c )
(d )
Fig. 2.6.34 Plot of Distortion Factors (DF) vs Modulation Index (M) for different level of PWM schemes: (a) 3-level fc = 1400 Hz, (b) 3-level for fc = 1600 Hz, (c) 2-level for fc = 1400 Hz, (d) 2-level for fc = 1400 Hz for phase A of a 2-phase VSI with f = 50 Hz and Z = 1.0. 0 .0 0 4 0 .0 0 3 5
D i s to rti o n F a c to rs
0 .0 0 3 0 .0 0 2 5 0 .0 0 2 0 .0 0 1 5 0 .0 0 1 0 .0 0 0 5 0 800
900
1000
1100
1200
1300
1400
1500
1600
1700
1800
C a r r ie r F r e q u e n c y ( H z )
(a )
(b )
Fig. 2.6.35 Plot of Distortion Factors (DF) vs Carrier Frequency (fc). (a) three level PWM scheme (b) two level PWM scheme for phase A of a 2-phase voltage source inverter with f = 50 Hz, M = 1.0 and Z = 1.0.
66 0 .0 0 1 4 5
D i s to rti o n F a c to rs
0 .0 0 1 4
0 .0 0 1 3 5
0 .0 0 1 3
0 .0 0 1 2 5
0 .0 0 1 2 -1 .2
-1
-0 .8
-0 .6
-0 .4
-0 .2
0
0 .2
0 .4
0 .6
0 .8
1
1 .2
P h a s e M o d u la tio n In d e x
(a )
(b )
Fig. 2.6.36 Plot of Distortion Factors (DF) vs Phase Modulation Index (Z). (a) three level PWM scheme (b) two level PWM scheme for phase A of a 2-phase voltage source inverter with f = 50 Hz, fc = 1400 Hz and M = 1.0. Figures 2.6.1-2.6.16 provide the PWM pattern and harmonic spectrum for three level PWM scheme and Figs. 2.6.17-2.6.32 give the PWM pattern and harmonic spectrum for two level PWM scheme. Tables 2.6.1-2.6.4 present the data of calculated distortion factors for both level of schemes. Here the variable parameters are the fundamental frequency (f), carrier frequency (fc), modulation index (M) and phase modulation index (Z). At first, the fundamental frequency is varied keeping other parameters constant. As the fundamental frequency is increased it is observed that the distortion factors increase for both level of PWM schemes. From f = 10 Hz to 50 Hz, distortion factors are smaller in two level PWM scheme than that of the three level, but for f = 60 Hz to 100 Hz, it is opposite. Also the increase in distortion factor is higher above the 50 Hz of fundamental frequency. If the carrier frequency is increased from 1400 Hz to 1600 Hz then it is seen that distortion factor decreases or remain same in some cases for a particular fundamental frequency. This is due to the fact that the ratio of carrier frequency to fundamental frequency i.e. number of pulses in one carrier period determines the switching instants of the PWM pattern. That is as the number of pulses increases the distortion factor decreases. Because then switching increases. In the second case, the modulation index is increased keeping other parameters at constant. It is observed that as modulation index increases the distortion factor decreases. Because then the
67 duty cycle of the samples increases and the transistors remain in ON state for longer time. It is also seen in the PWM patterns that the width of the pulses have been increased. Besides, in the harmonic spectrum it is observed that as the modulation index is increased per unit amplitude of the fundamental component (the left most spectrum) is also increased. It is also observed that the distortion factor is higher in two level PWM scheme than in three level for the set of data. As the carrier frequency is changed from 1400 Hz to 1600 Hz then for the same value of other parameters distortion factor comes down slightly for both level of PWM scheme. Since the number of pulses increases with the carrier frequency. Still the distortion factor in two level PWM scheme is higher. It is also seen in the harmonic spectrum of two level scheme that per unit amplitude of the harmonics component increases as the modulation index goes down. But in three level it remains almost constant. In the third case the carrier frequency is changed from 800 Hz to 1800 Hz keeping the other parameters constant. As this parameter is increased again the number of switching instant increases and distortion factors go down. But distortion factor is higher in two level scheme compared to three level scheme. So, higher operating frequency is preferable. In the fourth case the phase modulation index is varied from -1.0 to +1.0. Here the distortion factors remain constant for both level of scheme. So, the speed reversal is possible without any change in fundamental or harmonic component. Not only that the distortion factor is very low for various values of other parameters. Besides, for this case the distortion factors are slightly lower in two level PWM scheme than that in the three level scheme. When Z = -1.0 the motor will rotate in clockwise direction and when Z = +1.0 it will rotate in counterclockwise direction. When Z = 0.0, the PWM patterns for both phases are completely in phase with each other as seen from the figures. Thus voltages of two phases of the motor will also be in phase with respect to each other. Therefore, the motor will not be able to produce any torque and hence it will remain at standstill.
2.7
Simulation of Current Waveform for Phase A of Two-Phase Induction Motor
The proposed system is simulated for both two-level and three-level PWM scheme to get the expected current waveforms of phase A for the two-phase induction motor with the variation of various modulation parameters. In this case a prototype 0.5 hp two phase induction motor is used having the motor resistance of 80 and the motor inductance of 50mH in each phase. Actual DC resistance of the motor is lower than the value of 80. Since for AC, at higher
68 frequency the DC resistance increases due to skin effect. So, taking this effect into account DC resistance has been increased to 80. The inverter is operated from a 90V, 3A DC power supply. Two high value capacitors are used to split this supply voltage equally into 45V for each phase of the motor since the inverter used in this experiment is a half-bridge type inverter. The proposed two-phase half-bridge power inverter using power MOSFET is given in Fig. 2.4.9.
0.6
Current (amps)
0.4
0.2
0
-0.2
-0.4
-0.6 0
0.01
0.02
0.03 Time (sec)
0.04
0.05
0.06
Fig. 2.7.1 Current waveform of a two phase induction motor for three level PWM scheme obtained using MATLAB Simulation for phase A with f = 50 Hz, fc = 1400 Hz, M = 1.0 and Z = 1.0 and N = 28.
69 0.6
Current (amps)
0.4
0.2
0
-0.2
-0.4
-0.6 0
0.01
0.02 0.03 Time (sec)
0.04
0.05
Fig. 2.7.2 Current waveform of a two phase induction motor for three level PWM scheme obtained using MATLAB Simulation for phase A with f = 60 Hz, fc = 1400 Hz, M = 1.0 and Z = 1.0 and N = 23.
0.6
Current (amps)
0.4
0.2
0
-0.2
-0.4
-0.6 0
0.005
0.01
0.015
0.02 0.025 Time (sec)
0.03
0.035
0.04
0.045
Fig. 2.7.3 Current waveform of a two phase induction motor for three level PWM scheme obtained using MATLAB Simulation for phase A with f = 70 Hz, fc = 1400 Hz, M = 1.0 and Z = 1.0 and N = 20.
70 0.6
Current (amps)
0.4
0.2
0
-0.2
-0.4
-0.6 0
0.01
0.02
0.03 Time (sec)
0.04
0.05
0.06
Fig. 2.7.4 Current waveform of a two phase induction motor for three level PWM scheme obtained using MATLAB Simulation for phase A with f = 50 Hz, fc = 1600 Hz, M = 1.0 and Z = 1.0 and N = 32.
0.6
Current (amps)
0.4
0.2
0
-0.2
-0.4
-0.6 0
0.01
0.02 0.03 Time (sec)
0.04
0.05
Fig. 2.7.5 Current waveform of a two phase induction motor for three level PWM scheme obtained using MATLAB Simulation for phase A with f = 60 Hz, fc = 1600 Hz, M = 1.0 and Z = 1.0 and N = 27.
71 0.6
Current (amps)
0.4
0.2
0
-0.2
-0.4
-0.6 0
0.005
0.01
0.015
0.02 0.025 Time (sec)
0.03
0.035
0.04
0.045
Fig. 2.7.6 Current waveform of a two phase induction motor for three level PWM scheme obtained using MATLAB Simulation for phase A with f = 70 Hz, fc = 1600 Hz, M = 1.0 and Z = 1.0 and N = 23.
0.5 0.4 0.3
Current (amps)
0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0
0.01
0.02
0.03 Time (sec)
0.04
0.05
0.06
Fig. 2.7.7 Current waveform of a two phase induction motor for three level PWM scheme obtained using MATLAB Simulation for phase A with f = 50 Hz, fc = 1400 Hz, M = 0.9 and Z = 1.0 and N = 28.
72 0.5 0.4 0.3
Current (amps)
0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0
0.01
0.02
0.03 Time (sec)
0.04
0.05
0.06
Fig. 2.7.8 Current waveform of a two phase induction motor for three level PWM scheme obtained using MATLAB Simulation for phase A with f = 50 Hz, fc = 1400 Hz, M = 0.8 and Z = 1.0 and N = 28.
0.5 0.4 0.3
Current (amps)
0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0
0.01
0.02
0.03 Time (sec)
0.04
0.05
0.06
Fig. 2.7.9 Current waveform of a two phase induction motor for three level PWM scheme obtained using MATLAB Simulation for phase A with f = 50 Hz, fc = 1600 Hz, M = 0.9 and Z = 1.0 and N = 32.
73 0.5 0.4 0.3
Current (amps)
0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0
0.01
0.02
0.03 Time (sec)
0.04
0.05
0.06
Fig. 2.7.10 Current waveform of a two phase induction motor for three level PWM scheme obtained using MATLAB Simulation for phase A with f = 50 Hz, fc = 1600 Hz, M = 0.8 and Z = 1.0 and N = 32.
0.6
Current (amps)
0.4
0.2
0
-0.2
-0.4
-0.6 0
0.01
0.02
0.03 Time (sec)
0.04
0.05
0.06
Fig. 2.7.11 Current waveform of a two phase induction motor for three level PWM scheme obtained using MATLAB Simulation for phase A with f = 50 Hz, fc = 1000 Hz, M = 1.0 and Z = 1.0 and N = 20.
74 0.6
Current (amps)
0.4
0.2
0
-0.2
-0.4
-0.6 0
0.01
0.02
0.03 Time (sec)
0.04
0.05
0.06
Fig. 2.7.12 Current waveform of a two phase induction motor for three level PWM scheme obtained using MATLAB Simulation for phase A with f = 50 Hz, fc = 1200 Hz, M = 1.0 and Z = 1.0 and N = 24.
0.6
Current (amps)
0.4
0.2
0
-0.2
-0.4
-0.6 0
0.01
0.02
0.03 Time (sec)
0.04
0.05
0.06
Fig. 2.7.13 Current waveform of a two phase induction motor for two level PWM scheme obtained using MATLAB Simulation for phase A with f = 50 Hz, fc = 1400 Hz, M = 1.0 and Z = 1.0 and N = 28.
75 0.6
Current (amps)
0.4
0.2
0
-0.2
-0.4
-0.6 0
0.01
0.02 0.03 Time (sec)
0.04
0.05
Fig. 2.7.14 Current waveform of a two phase induction motor for two level PWM scheme obtained using MATLAB Simulation for phase A with f = 60 Hz, fc = 1400 Hz, M = 1.0 and Z = 1.0 and N = 23.
0.6
Current (amps)
0.4
0.2
0
-0.2
-0.4
-0.6 0
0.005
0.01
0.015
0.02 0.025 Time (sec)
0.03
0.035
0.04
0.045
Fig. 2.7.15 Current waveform of a two phase induction motor for two level PWM scheme obtained using MATLAB Simulation for phase A with f = 70 Hz, fc = 1400 Hz, M = 1.0 and Z = 1.0 and N = 20.
76 0.6
Current (amps)
0.4
0.2
0
-0.2
-0.4
-0.6 0
0.01
0.02
0.03 Time (sec)
0.04
0.05
0.06
Fig. 2.7.16 Current waveform of a two phase induction motor for two level PWM scheme obtained using MATLAB Simulation for phase A with f = 50 Hz, fc = 1600 Hz, M = 1.0 and Z = 1.0 and N = 32.
0.6
Current (amps)
0.4
0.2
0
-0.2
-0.4
-0.6 0
0.01
0.02 0.03 Time (sec)
0.04
0.05
Fig. 2.7.17 Current waveform of a two phase induction motor for two level PWM scheme obtained using MATLAB Simulation for phase A with f = 60 Hz, fc = 1600 Hz, M = 1.0 and Z = 1.0 and N = 27.
77 0.6
Current (amps)
0.4
0.2
0
-0.2
-0.4
-0.6 0
0.005
0.01
0.015
0.02 0.025 Time (sec)
0.03
0.035
0.04
0.045
Fig. 2.7.18 Current waveform of a two phase induction motor for two level PWM scheme obtained using MATLAB Simulation for phase A with f = 70 Hz, fc = 1600 Hz, M = 1.0 and Z = 1.0 and N = 23.
0.6
Current (amps)
0.4
0.2
0
-0.2
-0.4
-0.6 0
0.01
0.02
0.03 Time (sec)
0.04
0.05
0.06
Fig. 2.7.19 Current waveform of a two phase induction motor for two level PWM scheme obtained using MATLAB Simulation for phase A with f = 50 Hz, fc = 1400 Hz, M = 0.9 and Z = 1.0 and N = 28.
78 0.5 0.4 0.3
Current (amps)
0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0
0.01
0.02
0.03 Time (sec)
0.04
0.05
0.06
Fig. 2.7.20 Current waveform of a two phase induction motor for two level PWM scheme obtained using MATLAB Simulation for phase A with f = 50 Hz, fc = 1400 Hz, M = 0.8 and Z = 1.0 and N = 28.
0.6
Current (amps)
0.4
0.2
0
-0.2
-0.4
-0.6 0
0.01
0.02
0.03 Time (sec)
0.04
0.05
0.06
Fig. 2.7.21 Current waveform of a two phase induction motor for two level PWM scheme obtained using MATLAB Simulation for phase A with f = 50 Hz, fc = 1600 Hz, M = 0.9 and Z = 1.0 and N = 32.
79 0.5 0.4 0.3
Current (amps)
0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0
0.01
0.02
0.03 Time (sec)
0.04
0.05
0.06
Fig. 2.7.22 Current waveform of a two phase induction motor for two level PWM scheme obtained using MATLAB Simulation for phase A with f = 50 Hz, fc = 1600 Hz, M = 0.8 and Z = 1.0 and N = 32.
0.6
Current (amps)
0.4
0.2
0
-0.2
-0.4
-0.6 0
0.01
0.02
0.03 Time (sec)
0.04
0.05
0.06
Fig. 2.7.23 Current waveform of a two phase induction motor for two level PWM scheme obtained using MATLAB Simulation for phase A with f = 50 Hz, fc = 1000 Hz, M = 1.0 and Z = 1.0 and N = 20.
80 0.6
Current (amps)
0.4
0.2
0
-0.2
-0.4
-0.6 0
0.01
0.02
0.03 Time (sec)
0.04
0.05
0.06
Fig. 2.7.24 Current waveform of a two phase induction motor for two level PWM scheme obtained using MATLAB Simulation for phase A with f = 50 Hz, fc = 1200 Hz, M = 1.0 and Z = 1.0 and N = 24.
Figures 2.7.1-2.7.12 give the current waveform for three cycles with the variation of various parameters as was done in earlier section for analyzing PWM patterns for three level PWM scheme. Next Figs. 2.7.13-2.7.24 give the current waveform for two level PWM scheme. Waveforms are taken for five sets of data for both three level and two PWM schemes. In the first two sets fundamental frequency is varied from 10 Hz to 100 Hz keeping carrier frequencies constant at 1400 Hz and 1600 Hz. In the second set of data modulation index is changed from 0.1 to 1.0 keeping carrier frequencies constant at 1400 Hz and 1600 Hz. In the third set of data carrier frequency is changed with other parameters at constant value. For all sets of data it is observed that the distortion factors are much higher in three level PWM scheme. Besides, as observed from the figures the current waveforms in three level scheme are severely distorted. The current waveforms are more sinusoidal in two level schemes than that in three level schemes as observed from these figures. This happens because, at the instant of switching the transistor will become ON and the current will start flowing through the inverters, but when it is OFF current cannot become zero instantaneously due to the presence of inductance in motor’s phase. So it flows through the diode across the transistor and the lower
81 DC source (here a capacitor) of the inverter. In three level PWM scheme pulses are positive or negative in one sampling interval while in three level PWM scheme pulses are alternately positive or negative. So, in two level PWM scheme distortion factors in the output current are much lower than that in the three level PWM scheme. As fundamental frequency is increased or carrier frequency is decreased the number of samples in one carrier period decreases. Thus distortion factors decrease. Again, if the modulation index is increased the width of the pulse is increased. So, the duty cycles of the samples are increased. Thus distortion factor increases.
2.8
Summary
In this chapter theory of the proposed scheme is developed. Then torque equations for two phase induction motor are derived. From here torque speed characteristics are obtained. Then system is simulated using MATLAB to get PWM patterns and current waveforms with the variation of various parameters. These patterns and waveforms are then analyzed and distortion factors are plotted using the simulated data. All of these simulated data and results are used in chapter 4 for comparison with the experimental results. In the next chapter hardware implementation of the proposed scheme is described.
82
Chapter 3 Implementation Scheme Using DSP 3.1
Introduction
In this chapter, at first, hardware implementation scheme using DSP is described with a block diagram of the whole system. Then development of the software and description of the program is given. The complete circuit diagram and its actual circuit in the PCB and the operation of the circuit are described in chapter 4. In this proposed digital signal processor controlled PWM phase modulator for two phase voltage source inverter the following provisions have been incorporated to vary the output voltage:
Change of modulation index, which causes speed adjustment
Change of phase modulation index for speed adjustment and smooth reversal of speed
Change of carrier frequency only to adjust the speed
Change of fundamental frequency, also for speed adjustment.
3.2
Hardware Architecture Using Digital Signal Processor
Figure 3.2.1 shows the block diagram of the main structure of the Digital Signal Processor (DSP) controlled PWM phase modulator for two-phase voltage source inverter for two-phase induction motor. It consists of a two-phase induction motor, a half-bridge type inverter, a driving circuit, a fixed DC voltage source, a PWM controller circuit using two EPROMs and a digital signal processor (DSP) kit (TMS302C50). Besides, a PC is required to compile the main program written in ANSI C to produce codes for DSP and upload the program codes in the TMS320C50 module. In the following subsections a brief description of this system is provided.
3.2.1 Personal Computer The function of the personal computer is to compile, link and convert the ANSI C program to TMS320C50 compatible Hex codes. The personal computer communicates to the TMS320C50 DSP module through its standard serial port having RS-232C interface.
83 Hardware Interfacing Circuit
SERIAL PORT
PORT C
8255
PB0-6
PC0
EPROM2 PA7 PB7
SERIAL PORT
BUFFERS
GATES
TDM PORT text TMS320C50
RS-232C
CONTROL
BUFFER & OPTO ISOLATION CIRCUIT
D0 - D15
PERSONAL COMPUTER
PULSE STRETCHER
EPROM1
ANALOG INTERFACE TLC 320C40
RCA JACK ANALOG
8251A
PORT A
KEY
PA0-6
SWITCHING CIRCUIT
A0 - A15 XDS510 PORT
JTAG Emulation Port
14 PIN HEADER
CLOCK & COUNTER
LCD
PC1-4
PORT B
32K*16 SRAM
PULSE AMPLIFIER & GATE ISOLATION CIRCUIT EXPANSION CONNECTOR
A/D CONVERTER 16 BIT
D/A CONVERTER 16 BIT
ANALOG IN 4 CHANNEL
ANALOG OUT 4 CHANNEL
Vs
Inverter Controller Circuit
32K*16 PROM
TWO PHASE MOSFET INVERTER
TWO PHASE INDUCTION MOTOR
Fig. 3.2.1 Block Diagram of the Digital Signal Processor Controlled PWM Phase Modulator for Two-Phase Voltage Source Inverter for Two-Phase Induction Motor.
3.2.2 Digital Signal Processor Kit (TMS320C50) The Texas Instrument (TITM) TMS320 digital signal processors (DSPs) are fabricated with static CMOS integrated circuit technology; the architectural design is based upon that of an earlier TI DSP, TMS320C25. The combination of advanced Harvard architecture, on-chip peripherals, onchip memory, and a highly specialized instruction set is the basis of the operational flexibility and speed of the „C5x devices. They execute up to 50 million instructions per second (MIPS).
84 The „C5x devices offer the following advantages:
Enhanced TM320 architectural design for increased performance and versatility
Modular architectural design for fast development of spin-off devices
Advanced integrated circuit processing technology for increased performance
Upward-compatible source code
Enhanced TM320 instruction set for faster algorithms and for optimized high-level language operation
New static-design techniques for minimizing power consumption and for maximizing radiation tolerance
The TMS320C50 with a clock of 40 MHz takes about 200 microseconds for computing a sine function. Hence the DSP alone will not be able to generate high-resolution PWM patterns at higher operating frequencies. For this reason a ROM look up table based external hardware is used for generating the real time PWM patterns. The DSP is involved for computing the duty cycle of the PWM pulses for two phases. It then sends the PWM codes to the 8255 I/O ports where an external ROM based circuit (using EPROM and other ICs) generate the real time PWM waveforms. In the program the 8255 (PPI) is configured to use port A and B as the output port and port C as the input port. Port A or B sends the generated PWM code to the low order data lines (D0-D6) of the EPROM (27C256) that generates the real time PWM patterns for phase A or B (at output lines, O0-O7). Port C is used for checking various status of the external circuit. The PC0 line of the input port C checks the ripple carry output of the counter (i.e. the completion of 8 bit up counting). PC1 and PC2 are used to send signals to the DSP to increase and decrease the modulation index respectively using two simple push button switches. PC3 and PC4 are used to increase and decrease the phase modulation index respectively.
3.2.3 RS 232C Serial Interface RS 232C interface standard allows for two full duplex data channels transmitting serial data, either synchronously or asynchronously, with or without handshake. For the RS 232C signal levels, the binary 0 (also called a Space or ON condition) is more positive than the binary 1 (also called the Mark or OFF condition). Connection between the PC and MDA DSP kit is made by this interface. The connection can be done in two ways as shown in Fig. 3.2.2 (a) and (b).
85 IB M P C
MDA DSP
( 2 5 p i n S e r i a l P o r t)
( 9 p i n S e r i a l P o r t)
R S -2 3 2 C C a b le
2
2
3
3
7
5
(a ) IB M P C
MDA DSP
( 9 p i n S e r i a l P o r t)
( 9 p i n S e r i a l P o r t)
R S -2 3 2 C C a b le
2
2
3
3
5
5
(b )
Fig. 3.2.2 Connection Diagram of MDA-DSP Kit with PC: (a) PC 25 Pin, MDA-DSP 9 Pin Connection, (b) PC 9 Pin, MDA-DSP 9 Pin Connection.
3.2.4 Hardware Interfacing Circuit I.
Clock, Counter and Pulse Stretcher Circuit
For the clock circuit TTL 7404 inverter is used. Three inverters together with a resistor of 1K and a capacitor of 0.001F are used to generate the clock frequency as shown in figure 3.2.3. To set the clock frequency to a different value one need to simply change the value of the resistor.
10 11
C LK R ST
U2 40 40
T o tw o E P R O M s a d d r e s s e s , A 0 -A 7
This clock frequency determines the pulse width of the PWM pattern.
9 7 6 5 3 2 4 13 12 14 15 1
V C C ( +5V )
R8
C8
10 k
0.01 uF
74 04
C E X T
R1
1 4
5 U 1C
R E X T /C E X T
A B C L R
6
1 5
1 2 3
Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q 10 Q 11 Q 12
U 5A
1k
74 123 2
3
U 1A
4 U 1B
C1
74 04
1 3
4
74 04
Q
Q
1
PC 0 0.00 1uF
Fig. 3.2.3 Clock, Counter and Pulse Stretcher Circuit.
86 The following equation is used to find out the value of the clock frequency f
1
(3 .2 .1 )
3RC
Now putting the value of R and C into the above equation the value of the clock frequency is found as follows 1
f
3
3 * 1 * 1 0 * 0 .0 0 1 * 1 0
10
6
6
3 3 3 3 .3 3 K H z
(3 .2 .2 )
The output of the clock circuit is applied to the input of a CMOS counter CD4040. In every falling edge of the clock the 12-bit counter increments its count by 1. Of them first eight bits are applied to the address lines (A0-A7) of the EPROM 27C256, since there are 256 (28 = 256) addresses in the EPROM. The 9th (pin 12) bit becomes high after the end of counting of eight bits completely i.e. when all 8 bits are 1, but immediately after that the entire 12 bit goes to zero since this bit is connected to the active high reset input (pin 11) of the counter (Fig. 3.2.3). The first line, PC0 of the input port C of the DSP kit should also scan this line (pin 12) so that the DSP kit can send the PWM pattern of the next cycle through its output port A and B to the data lines (D0-D7) of two EPROMs. But due to the presence of this pulse for a very short duration of time, the PC0 line may not scan it properly. So this pulse needs to be stretched further. That is why, a pulse stretcher circuit is constructed using TTL 74LS123 monostable timer. The 9th bit (pin 12) is connected to the positive edge trigger input (pin 2) of the TTL 74LS123 monostable timer. As soon as this 9th bit goes high, it triggers the output of this timer from low to high. The output pulse width is determined by the values of the external capacitance (Cext) and timing resistance (Rext). When Cext > 1000pF, the pulse width is defined by the following equation: 0 .7 t w 0 .2 8 R ext C ext 1 R ext
3 .2 .3
In this circuit, Rext = 10 K and Cext = 0.01 F. So, the output pulse width ist w 0 .2 8 1 0 1 0 0 .0 1 1 0 3
0 .0 2 8 0 0 1 9 6 m s
6
0 .7 1 3 10 10
3 .2 .4
This time is sufficient for the PC0 line to scan this high pulse at least once in a carrier period.
87 II.
Data Storage Devices
Two EPROMs (27C256) are used for storing PWM pattern for the two phases. They have fast access time of 5 ns. The lower order address lines (A0-A7) of the EPROM are connected to the first eight output lines (Q1-Q8) of the counter CD4040, and the seven higher order address lines (A8-A14) are connected to the seven lower order lines of the output port A (PA0-PA6) or B (PB0-PB6) of the 8255 as shown in Fig. 3.2.4. Of the eight output lines of the EPROM, the first one or two lines (pin 11 and pin 12) are used to get the required PWM pattern depending on the level of the PWM scheme to be used. In order to activate the EPROM logically and to obtain data to the output pins, the chip enable (pin 20) and the output enable (pin 22) pins should be
P A 0 -P A 6 F ro m
F r o m f ir s t 8 o u t p u t li n e s o f t h e c o u n t e r , O 0 -O 7
connected to ground. These two control functions are independent with each other.
10 9 8 7 6 5 4 3 25 24 21 23 2 26 27
O0 O1 O2 O3 O4 O5 O6 O7
11 12 13 15 16 17 18 19
T o i n v e r tin g b u ffe r
U4 0 1 2 3 4
27 C 256
CE OE VPP
T o
a n o th e r E P R O M
20 22 1
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A1 A1 A1 A1 A1
Fig. 3.2.4 Data Storage Devices using EPROM 27C256.
Since the EPROM has eight address lines, so there are 256 address locations inside the IC. In these locations, 256 samples of PWM patterns, each of 8-bit in length, are stored using an EPROM programmer. This programmer uses 12.5V DC for programming the EPROM. First a dat file is generated where the required binary data of PWM pattern is stored. Then using the software provided with the EPROM programmer this dat file is uploaded into the buffer and from where the binary data is stored into the EPROM.
88 III.
Buffers and Gates
The most significant line of the output ports A or B of 8255 (PA7 or PB7) are used for decoding the PWM pattern for the two transistors of the same leg of the inverter using two AND gates and a NOT gate to generate the three level PWM pattern from one output line (pin 11) of the EPROM as shown in Fig. 3.2.5 (a). For the two level PWM pattern generations, this decoding is not necessary. Because for two transistors of the same leg of the inverter, the outputs are taken
S1
F r o m p in 1 1 o f th e E P R O M
5
4
3
U 6B
2
1
U 6A
40 49
A1 U 8A
2
40 49
3
74 08
4
A2 U 8B
7
F r o m P A 7 l i n e o f p o rt A
6
5
U 6C
6
T o t h e G a te s o f th e M O S F E T s
from the two output lines (pin 11 and 12) of the EPROM as shown in Fig. 3.2.5 (b).
74 08
40 49
S1
F r o m p in 1 1 o f th e E P R O M
5
4
3
U 6B
2 U 6A
40 49
40 49
S4
F r o m p in 1 2 o f th e E P R O M
7
6 U 6C
14
15 U 6F
40 49
T o t h e G a te s o f th e M O S F E T s
(a)
40 49
(b)
Fig. 3.2.5 Decoding of signals for the two transistors of the same leg of the power inverter: (a) in Three Level PWM Scheme, (b) in Two Level PWM Scheme.
The CMOS buffers CD4049 enhance the strength of the output signal obtained from the output lines (pin 11 and pin 12) of the EPROM. Since this is inverting type buffer, so two inverters are used consecutively. Fro three level PWM pattern generation, the 8th line (PA7 or PB7) of the output port of the 8255 remains high until the seven low order data (PA0-PA6 or PB0-PB6) lines are sending data for the positive half cycle of the PWM pattern. Then it goes low. So, the output of the buffer CD4049 is decoded further for two transistors of the same leg of the inverter. As shown in Fig. 3.2.5 (a), the output of the buffer CD4049 is connected to one of the inputs of both AND gates (TTL 74LS08). The 8th line of the output port of 8255 is connected directly to the other input of the first AND gate and the input of the CMOS inverter CD4049. The output of this inverter is
89 connected to the other input of the second AND gate. Thus two signals for the gate of the MOSFETs are obtained for one leg of the power inverter. Another circuit like this one is used to get two signals for the gate of the MOSFETs of the other leg of the power inverter.
3.2.5 Inverter Controller Circuit I.
Buffers and Opto-Isolation Circuit
The TTL inverting buffer 74LS14 is used at the first stage of the inverter controller circuit to take the signals from the hardware interfacing circuit. Each input of this inverter has hysteresis, which increases the noise immunity and transforms a slowly changing input signal to a fast changing, jitter free output. The biasing voltage for this stage is +5V and it given from the previous stages. The purpose of this inverting buffer is to enhance and invert the signal level. The output of the inverter is connected to the LED of the opto-coupler via a 100 resistance in series as shown in Fig. 3.2.6. This resistor actually limits the current through the LED. In the opto-isolation stage the opto-coupler (4N25) is used. This stage provides the ground isolation between the DSP and the power inverter circuit. Thus it prevents any current flow between the two systems.
T o th e H a rd w a re In te rfa c i n g C i rc u it VC C U 1A
F r o m th e fin a l 1 o u tp u t o f th e H ardw are In te rfa c i n g C i rc u it
+5V 2
R1
1
10 0 ohm
U2
4N 2 5
6 5
R9
V1
10 0K
74 14
4
+12 V
2
To CMO S i n v e r te r R5 1K
Fig. 3.2.6 Buffer and Opto-isolation Circuit.
The opto-couplers are in a package that contains both an infrared LED and a photodetector called phototransistor. The phototransistor could be a Darlington pair. The biasing voltage of this phototransistor of each opto-coupler is provided from the separate +12V DC power supplies of the corresponding stage. The wavelength response of each device is tailored to be as identical as possible to permit the highest possible coupling. There is a transparent insulation cap between each set of elements embedded in the structure to make a passage for the light. They are
90 designed with response times so small that they can be used to transmit data in the megahertz range. The typical values of turn-on time ton = 2 to 5 s and turn-off time toff = 300 ns. The output signal is taken across a 1K resistor, which is connected between the emitter terminal of the phototransistor and the ground of the +12V DC power supply. A 100K resistor is connected between the emitter and the base of the phototransistor as a feedback element.
II.
Buffer, Gate Isolation Circuit and Current Amplifier
This stage contains CMOS inverting buffers CD4049, one pair of complimentary transistors BD135 (npn) and BD136 (pnp) and three +12V DC power supplies as shown in Fig. 3.2.7.
V1 +12 V U 6A
F r o m th e o u tp u t o f th e o p to - c o u p l e r
3
QN1 BD 1 35
2
R 13
T o th e g a te o f th e M O S F E T
10 0oh m 40 49
QP1 BD 1 36
Fig. 3.2.7 Buffers, Current Amplifiers and Gate Isolation Circuits.
The purpose of the CMOS buffer is to enhance and revert the signal level. For biasing each buffer of the two upper MOSFETs of the inverter, two separate +12V DC power supplies are used, and for the remaining two buffers of the lower MOSFETs of the inverter another +12V DC power supply is used. Thus grounds of the two upper buffers are different but grounds of the lower buffers are the same. So, two inverters from two separate ICs (i.e. CD4049) must be used as the buffer of the upper half of the inverter and two inverters from the same IC can be used as the buffer of the lower half of the inverter [Fig. 4.2.5]. For operating power transistors as switches, an appropriate gate voltage or base current must be applied to drive the transistors into the saturation mode for low on-state voltage. The control voltage should be applied between the gate and source terminals (for the case of a MOSFET) or between the base and emitter terminals (for the case of a BJT). The power converters generally require multiple transistors and each transistor must be gated individually. The PWM pulses those are to be applied to the gate and are generated from the logic circuit, are shifted in time to perform the required logic sequence for power conversion from dc to ac. However, all four logic pulses have a common terminal, which may be connected to the ground
91 terminal of the main dc power supply; and if it is done then all the PWM pulses applied to the gates of the MOSFET will be with respect to this ground. But the pulses must be applied to the gate with respect to the source terminals, and all the source terminals are not connected to this common ground. Therefore, there is a need for isolation and interfacing circuits if the logic signals are compatible with the gate drive requirements of the transistors. The importance of gating a transistor between its gate and source rather than applying gating voltage between the gate and common ground can be understood from the following discussions. All devices comprising an MOS device are made on a common substrate. As a result, the substrate voltage of all devices is normally equal. However, in inverters, two MOSFETs are connected in series. This may result in an increase in source-to-substrate voltage as one proceeds vertically upward along the series chain. Under normal conditions, that is, when gate to source voltage Vgs is greater than the threshold voltage Vt, the depletion-layer width remains constant and charge carriers are pulled into the channel from the source. However, as the substrate bias Vsb (Vsource - Vsubstrate) increases, the width of the channel-substrate depletion layer also increases, resulting in an increase in the density of the trapped carriers in the depletion layer. For charge neutrality to hold, the channel charge must decrease. The resultant effect is that the substrate voltage, Vsb, adds to the channel-substrate junction potential. This increases the gate-channel voltage drop. The overall effect is an increase in the threshold voltage, Vt. There are various ways of floating or isolating the control or gate signal with respect to the ground. In this work, three separate DC power supplies are used for the gate isolation. For the MOSFETs in the lower half of the inverter, there is no problem in connecting the pulse to the gate terminal, because the sources of these MOSFETs are connected directly to the ground. But for the MOSFETs in the upper half of the inverter, the ground is to be isolated as the source of these MOSFETs are not connected directly to the ground rather to the drain terminals of the MOSFETs of the lower half of the inverter. While designing these DC power supplies centertapped step-down transformers are used. Therefore, the grounds are isolated through inductive coupling. A push-pull type current amplifier using a pair of complimentary transistors (BD135 and BD136) are used for further improvement of the current before applying the signal to the gate of the MOSFET. These transistors have fast switching speeds.
92
3.2.6 Power Inverter Circuit Using MOSFETs Two-phase half bridge inverter circuit consisting of four MOSFETs (IRF840) as switching devices are arranged as shown in Fig. 2.4.9. Two capacitors of 4700f, 250V are connected in series to split the dc supply voltage into two parts. The middle point is used as the ground terminal of the two phase load. So, each phase of the load gets half of the supply voltage V s. As the load, a two-phase induction motor of 0.5 hp is used. The MOSFET IRF840 is an n-channel enhancement mode MOSFETs, which can sustain a maximum drain to source voltage of 500V. Their current rating is also very high. Power MOSFETs are chosen as switching devices as their switching times are of the order of nanoseconds. They don‟t have the problems of second breakdown phenomena as do BJTs do. The other specialties of power MOSFETs to be used in inverters are temperature stability of the electrical parameters and ease of paralleling.
3.2.7
Switching Matrices for the Variation of Modulation Index
A switching matrix is used for the variation of the modulation index. Four push button type switches and four 1K resistors are used. One end of all the switches is connected together with the +5V DC power supply. The other ends of the switches are connected to the one end o a 1K resistor and also to the PC1, PC2, PC3 and PC4 lines of the input port C. The other ends of all the resistors are connected to the ground terminal of the +5V supply. Two switches (SW1 and SW2) are used to increase and decrease the modulation index, M and the remaining two switches (SW3 and SW4) are used to increase and decrease the phase modulation index, Z.
V C C ( +5V )
SW 1 PC 1
SW 2 PC 2
SW 3 PC 3
SW 4 PC 4
R1
R1
R1
R1
1K
1K
1K
1K
S w i tc h i n g a rr a n g e m e n t fo r v a ry i n g v o lta g e m o d u l a ti o n in d e x ( M )
S w i tc h i n g a rr a n g e m e n t fo r v a ry i n g p h a s e m o d u l a ti o n in d e x ( Z )
Fig. 3.2.8 Switching matrices for the variation of the modulation index.
93
3.3
Software Development Using ANSI C Compiler
The control of power electronic system is very time critical, and therefore, assembly language is normally used which provides fast execution time. But a program developed in assembly language is time consuming, tedious, complex to interpret, and may require many iterations. On the other hand, with today‟s faster microcomputer, the amount of execution time saved by the assembly language other than high-level language is not so important. That is why, a high-level language like C or C++ can be used to develop the software for this type of system and thus made the program easy to develop, generous to perceive and compatible to other automation environment as well. In this work, the ANSI C compiler supplied by the Texas Instrument is used to write the program and generate the machine codes for the Digital Signal Processor (DSP) kit using a PC. After successful compilation of the program in the PC, it is uploaded to the DSPs memory. Then the program is run either from the PC or from the DSP. This causes to send the desired pulse patterns to the output port A or B and receive signal at the input port C of the 8255 peripheral interface IC. To use the port A and B as the output port and port C as the input port, this IC needs to be configured in the software.
3.3.1 Configuring the 8255 Peripheral Interface The 8255 is a widely used, programmable, parallel I/O device. It can be programmed to transfer data under various conditions, from simple I/O to interrupt I/O. The 8255 has 24 I/O pins that can be grouped primarily in two 8-bit parallel ports: A and B, with the remaining eight bits as port C. The eight bits of port C can be used as individual bits or be grouped in two 4-bit ports: Cupper and Clower. The functions of these ports are defined by writing a control word in the control register. All the functions of the 8255 are classified into two modes: the Bit Set/Reset (BSR) mode and the I/O mode. The I/O mode is further divided into three modes: Mode 0, Mode 1 and Mode 2. In Mode 0, all ports function as simple I/O ports. The control word specifies an I/O function for each port. If bit D7 = 1, bits D0-D6 determine I/O functions in various modes. Since in this work it needs to configure all of the three ports as I/O ports, Mode 0 can be used. In this mode, ports A and B are used as two simple 8-bit I/O ports and port C as two 4-bit ports. Each port (or half-port, in case of C) can be programmed to function as simply an input or an output port. In Mode 0, outputs are latched, inputs are not latched and ports do not have
94 handshake or interrupt capability. Figure 3.3.1 shows how configuration of the ports can be done writing a control word. The configuring of the port must be done in the software. In this work, 89H is sent to the 8255D of the DSP kit from the program to configure the ports.
C o n tr o l W o r d D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
0
1
0
0
1
= 89H P o rt C
L
= In p u t
P o rt B = O u tp u t P o rt B in M o d e 0 P o rt C
U
= In p u t
P o rt A = O u tp u t P o rt A in M o d e 0 I/O fu n c tio n s o f th e p o rt A , B & C
Fig. 3.3.1 Control word for 8255 to configure port A and B as output and port C as input port.
3.3.2 Development of the Program The developed programs “PWM3L2PH.C” (for three level PWM pattern generations) and “PWM2L2PH.C” (for two level PWM pattern generations) are given in the Appendix. Here the flow charts of the program and descriptions of the programs are given. The flow charts of these two programs are given in Figs. 3.3.2 and 3.3.3 respectively. First of all, appropriate header files, math.h and c50.h are included. The math.h is used to call various mathematical functions (such as, sine trigonometric function) and to perform various mathematical operations such as multiplication, division, addition and subtraction operations. The c50.h header file is used to call various functions for I/O operations. Such as to send or receive data to or from the port A, B and C of 8255, PPIA, PPIB and PPIC keywords are used. PPICW keyword is used to send an appropriate control word to the 8255D to configure the ports of 8255 as output or input port. Then all the integer and float types variables and arrays are declared. The naming of all the variables is shown in the main program. Then in the main function body all the variables are initialized with appropriate values. The ratio of fc and f should be integer as it defines the number of pulses, N in one complete cycle of a fundamental period. Then switching points of a
95 sine wave and starting value of a PWM cycle are calculated. Next ports A and B are configured as output ports and all 8-bits of port C as input port using the control word Hex 89. Then the program enters into an infinite “for loop”, for(; ; ) so that the program never terminates by itself rather it continues to execute the commands inside the body of this loop for indefinite period of time. To terminate the program the reset key of DSP kit should be pressed. A definite period of time is elapsed by the control parameter j. The value of j is increased by 1 at every time the infinite “for loop” starts. If the value of j is not equal to 10 then the commands inside the body of the “if statement” will not be executed. Once j is equal to 10 the program first scans the input port C, that is, it checks the pin 2, 3, 4 and 5 of the input port C. Then Hex number 02 is ANDed with the data of pin 2. If the result is Hex 02, i.e. if pin 2 is high and also the modulation index is less than 1 then the modulation index, M will be increased by 0.1 (since the maximum value of the modulation index is 1). Similarly, the value of data at pin 3, 4 and 5 are checked using the Hex numbers 04, 08 and 10 respectively, and accordingly modulation index M or Z will be varied (the minimum value of M is 0 and the maximum and the minimum values of Z are +1 and -1 respectively). After that the value of j must be reset to zero. Then another “for loop” is used to count the switching instants for all the Nth samples for both phase A and B. The calculated values of sampled signals are stored in two different arrays, and from here duty cycles are calculated. Since only seven bits of data are to be used by the EPROM so the sine functions are multiplied by 127 (for three level PWM pattern generation) or 63 (for two level PWM pattern generation). In each duty cycle calculations the sampled sine functions are multiplied by the voltage modulation index to get the actual pulse width. Since the DSP processor that is used in this work has no floating-point support, all the calculated duty cycles are converted into integer type data by using “int” keyword. For three level PWM scheme positive, negative and zero vale can arise in the PWM patterns in a particular sampling period. Since through the ports only positive values can be sent, so flags are used to make the data positive. At first, the calculated integer values of the duty cycles are checked whether it is negative or not and accordingly flag values are set. The flag values can be +1, -1 or 0. After that multiplying the duty cycles by appropriate flag values, only positive values of the duty cycles are obtained. According to the value of this flag 128 samples are added to the already calculated duty cycles, Dx and Dy to get the proper values of duty cycles for the two phases, PMW_A and PWM_B.
96 S ta r t d e fi n e a n d i n i ti a l i z e a l l th e v a r i a b l e s a s p e r r e q u i r e m e n ts
j = 0 S e n d 8 9 H to p o r t D o f 8 2 5 5 A
2
fo r ( ; ; )
j = j + 1 N
j = 10? Y
S c a n th e p o r t C P C 1 to P C 4 N PC 1 = 1? Y N M < 1 .0 ? Y
M = M + 0 .1
PC 2 = 1?
N
Y N
M > 0 .0 ? Y
M = M - 0 .1
N PC 3 = 1? Y N Z < 1 .0 ? Y
Z = Z + 0 .1
PC 4 = 1?
N
Y N
Z > 0 .0 ? Y
Z = Z - 0 .1
2
3
1
C o n ti n u e d to th e n e x t p a g e . . . . .
97
2
3
1
j = 0
fo r ( i = 1 ; i < = N ; i + + )
C a lc u la te P W M s a m p le s u s in g th e ta , th e ta S a n d p h a s e m o d u la tio n in d e x in s in e fu n c tio n s fo r p h a s e A & B C a lc u la te d u ty c y c le s fo r p h a s e A & B C o n v e r t th e s e c a lc u la te d d u ty c y c le s in to in te g e r v a lu e s o f D x & D y fo r p h a s e A & B r e s p e c tiv e ly
D x < 0?
N
N
D x > 0?
Y
Y
fla g A = - 1
fla g A = 1
fla g A = 0
D x = D x * fla g A
D y < 0?
N
N
D y > 0?
Y
Y
fla g B = - 1
fla g B = 1
fla g B = 0
D y = D y * fla g B
fla g A = 1 & fla g B = - 1
Y
2
4
5
N
fla g A = 1 & fla g B = 1
Y
N
fla g A = - 1 & fla g B = 1
N
fla g A = - 1 & fla g B = - 1
Y
Y
A 1 = D x + 128
A 1 = D x + 128
A1 = Dx
A1 = Dx
B1 = Dy
B 1 = D y + 128
B 1 = D y + 128
B1 = Dy
6
C o n ti n u e d to th e n e x t p a g e . . . . .
98
2
4
6
5
S c a n th e p o r t C o n ly p in P C 0
N
P C 0 = 1? Y
S e n d th e c a lc u la te d s a m p le s A 1 & B 1 to th e p o r t A & p o r t B o f 8 2 5 5 A
4
2
Fig. 3.3.2 Flow Chart for developing the software in ANSI C to generate PWM patterns in three level PWM scheme Now in this stage, the program checks the status of the counter‟s counting sequence through the PC0 line of port C. To do this the data obtained from the port C is logically ANDed with Hex 01. Then all the bits of PC become zero except the bit in PC0. If pin 1 is high then PC0 is 1 otherwise it is zero. If the counting of the counter is complete then pin 1 becomes high for the duration of 28.00196 s. This time is sufficient to scan the input port at least once. Then the program comes out of the do loop, and immediately after that already calculated PWM patterns for the two phases are sent to the output port A and B of 8255 using the commands PPIA and PPIB respectively.
For two level pattern generation the main structure of the program is the same as that of the three level PWM pattern generations. The difference lies in the case of duty cycle calculations. For two level PWM scheme PWM samples become positive or negative alternately in a particular sampling period. Here with both the duty cycles 64 are added directly, and sine samples are multiplied by 63 to get appropriate duty cycles, Dx and Dy. Now in this stage, the program checks the status of the counter‟s counting sequence of EPROM‟s address through the PC0 line of the input port C. If counting is complete then the program comes out of the do loop, and immediately after that already calculated PWM patterns for the two phases are sent to the output port A and B of 8255 using the commands PPIA and PPIB respectively.
99 S ta r t d e fi n e a n d i n i ti a l i z e a l l th e v a r i a b l e s a s p e r r e q u i r e m e n ts
j = 0 S e n d 8 9 H to p o r t D o f 8 2 5 5 A
2
fo r ( ; ; )
j = j + 1 N
j = 10? Y
S c a n th e p o r t C P C 1 to P C 4 N PC 1 = 1? Y N M < 1 .0 ? Y
M = M + 0 .1
PC 2 = 1?
N
Y N
M > 0 .0 ? Y
M = M - 0 .1
N PC 3 = 1? Y N Z < 1 .0 ? Y
Z = Z + 0 .1
PC 4 = 1?
N
Y N
Z > 0 .0 ? Y
Z = Z - 0 .1
2
3
1
C o n ti n u e d to th e n e x t p a g e . . . . .
100 2
3
1
j = 0
4 fo r ( i = 1 ; i < = N ; i + + )
C a lc u la te P W M s a m p le s u s in g th e ta , th e ta S a n d p h a s e m o d u la tio n in d e x in s in e fu n c tio n s fo r p h a s e A & B C a lc u la te d u ty c y c le s fo r p h a s e A & B C o n v e r t th e s e c a lc u la te d d u ty c y c le s in to in te g e r v a lu e s o f D x & D y fo r p h a s e A & B r e s p e c tiv e ly
S c a n th e p o r t C o n ly p in P C 0
N
P C 0 = 1? Y
S e n d th e c a lc u la te d s a m p le s D x & D y to th e p o r t A & p o r t B o f 8 2 5 5 A
4
2
Fig. 3.3.3 Flow Chart for developing the software in ANSI C to generate PWM patterns in two level PWM scheme
3.4
Summary
The implementation scheme is described in this chapter in detail; especially the hardware architecture and software development is described. First, description of the DSP kit is given. Then the function of each component and the purpose of using each component in the circuit with their advantages are described. Then the flow chart and description of the program is given in detail. In the next chapter, the complete circuit diagram of the hardware architecture and the operation of the whole circuit are described. The real-time waveforms for PWM patterns and currents obtained from the oscilloscope screen are presented and analyzed also.
101
Chapter 4 Experimental Result Analysis 4.1
Introduction
In this chapter the experimental inverter and its operation is described. The PWM patterns and current waveforms of the inverter are recorded for different operating conditions. Oscillogram of the PWM patterns and current are recorded by a camera for both two-level and three-level PWM schemes. These plots are analyzed and compared with the simulated data presented in chapter two.
4.2
Inverter Operation
The complete circuits of proposed scheme are shown in Figs. 4.2.1-4.2.3. Figure 4.2.1 shows the hardware interfacing circuit for three-level PWM scheme, Fig. 4.2.2 shows the same for twolevel and Fig. 4.2.3 shows the inverter and its controller circuits. The hardware interfacing and electronic control circuits are placed on a PCB. The photographs of the real-time circuits implemented on the PCBs are also shown. To operate the inverter using PC and MDA DSP kit the integrated development environment (IDE) supplied with this kit is used.
4.2.1 The Integrated Development Environment The Integrated Development Environment (IDE) links an editor with MS-DOS or the Assembler or the Compiler. The IDE lets specify and use other development tools conveniently. When combined with macro assembler and compilers the IDE is effective tool to aid in development and debugging. Errors reported by the Assembler/Compiler show the user, where, the errors were detected in the source code. The IDE puts all projects tools a few keystrokes away to simplify and effectively reduce development time.
102
4.2.2 MDA-DSP Windows The MDA-DSP IDE screen is divided into 8 windows, each of which serves a specific purpose. Of the 8 windows, one can use 6 windows (Main and Sub Menu, Program, MMR, Block B2, Block B0-B1 window). Active window is black screen and inactive window is blue screen.
4.2.3 The Main and Sub Menu This is where most of the user interaction with MDA-DSP IDE takes place. The primary MDADSP IDE Main Menus are listed across the top line with the sub-menus are on the line below.
4.2.4 The Program Window The disassembled code for the program of the working file is displayed here along with an address, machine language, and mnemonic code at the left of each line. The yellow line at the left of the program memory window is the current cursor, and is used to select a line of code for some action. The bar at the left of the program window is the current PC location. The program window cannot be written by the data. The user program memory region of the MDA-DSP kit is the 0800H-2B7FH.
4.2.5 The MMR (Memory Mapped Register) Window The values displayed here are updated after a breakpoint is encountered when executing normally, after every instruction while single stepping. The upper part of the MMR window displays the memory mapped registers. The lower part of the MMR window displays the memory mapped registers, which does not displays the upper part.
4.2.6 The Block B2 Window This displays the block B2 (60H-7FH). The values displayed here are updated after a breakpoint is encountered when executing normally, after every instruction while single stepping.
4.2.7 The Block B0-B1 Window This displays the block B0-B1 (0100H-04FFH). The values displayed here are updated after a breakpoint is encountered when executing normally, after every instruction while single stepping.
103
4.2.8 The Basic Operation Procedure The MDA -DSP IDE basic operation procedure is described below:
Turn off PC’s power
Connect RS-232 cable to either communication port 1 or 2 on PC as shown in chapter 3.
Now turn on PC and MDA-DSP Kit. Move the T1 switch, located to the up-right part of the keyboard, to the PC marking.
Push the reset switch.
Run the MDA-DSP IDE. After a few moments, the main screen will be displayed.
From the work menu open the file.
From the work menu go to the edit sub menu to write the program using ANSI C Compiler or edit the previously written program
Save the program from the editor.
Now from the work menu compile and link the file that contains source code.
From file menu load the hex file generated after compilation of the program into MDA-DSP IDE & MDA-DSP kit.
Finally run the program from the run menu.
4.2.9 Operation of the Inverter A. Three-level PWM Pattern Generation The complete circuit diagram and its real-time circuit implemented on the PCB for the generation of three-level PWM pattern are given in Fig. 4.2.1 and 4.2.2 respectively. Immediately after running the program, it will send data to the port A and B of 8255A. The seven bit data from ports A (PA0-PA6) and B (PB0-PB6) come to the lower part of the addresses of the two EPROMs. As the power is ON, the clock circuit generates the clock signal for the counter and the counter starts counting up with each falling edge of the clock. That is the upper part of the address of the two EPROMs simultaneously being counted up. With the combination of this address and data value, the EPROMs send required PWM output at its output pins. When the counter ends up counting 8-bits, i.e. when all 8 bits become 1 then at the next falling edge of the clock all the first 8-bits become zero and the 9th bit becomes 1. Since it is connected to the active high reset input of the same counter as soon as the 9th bit is 1 all the output bit of the counter resets to zero. So, the duration of the high pulse at the 9th bit of the counter is very short, it depends only on the propagation delay of the counter. The monostable
104 circuit stretches it. At the rising edge of the 9th bit of the counter the monostable circuit is triggered and its output remains high for a duration determined by the external timing resistance and capacitance. The output of the monostable circuit is applied to the PC0 line of the input port C. The stretched pulse ensures the input port C will scan ending up of the counting the addresses of the two EPROMs at least once. As soon as it gets this information DSP sends the calculated duty cycles of the next cycle to the port A and B. With each complete counting of the counter, each EPROM sends its 256 stored samples from the corresponding address location sequentially to its output lines. The PWM pattern is taken from the first output line (pin 11) of the two EPROMs for two phases. The inverter and AND gate produces two complimentary signals (A1 and A2 for phase A and B1 and B2 for phase B) for the same vertical arm of the inverter from one output line of the EPROM. Thus when the upper transistor is ON, the lower transistor remains OFF. These signals are then applied to the inverter controller circuit. S1 9 7 6 5 3 2 4 13 12 14 15 1
CLK
Q1 Q2 RST Q3 Q4 Q5 U2 Q6 Q7 4040 Q8 Q9 Q10 Q11 Q12
11
PA0-PA6
10
10 9 8 7 6 5 4 3 25 24 21 23 2 26 27 20 22 1
VCC (+5V)
R8 10k
A0 O0 A1 O1 A2 O2 A3 O3 A4 O4 A5 O5 A6 O6 A7 O7 A8 U4 A9 A10 27C256 A11 A12 A13 A14
11 12 13 15 16 17 18 19
5
U6B
4
3
4049
U6A
2
1
A1 U8A
2
4049
3
7408
4
A2 U8B
7
PA7
U6C
6
5
6
7408
4049
CE OE VPP
C8 S3
0.01uF 14
15
1 2 3
CEXT
REXT/CEXT
A B CLR Q
Q
PB0-PB6
U5A 74123
10 9 8 7 6 5 4 3 25 24 21 23 2 26 27
13
4
20 22 1
A0 O0 A1 O1 A2 O2 A3 O3 A4 O4 A5 O5 A6 O6 A7 O7 A8 U4 A9 A10 27C256 A11 A12 A13 A14
11 12 13 15 16 17 18 19
5
U7B
4
3
4049
U7A
2
1
B1 U9A
2
4049
3
7408
4
B2 U9B
PB7
7
U7C
6
5
6
7408
4049
CE OE VPP
PC0 VCC (+5V) 6
U1C
5 SW1
7404
R1
PC1
SW2 PC2
SW3 PC3
SW4 PC4
1k
1
U1A
2
3
7404
U1B
4
R1 1K
R1 1K
R1 1K
R1 1K
7404 C1
Sw itching arrangement for varying voltage modulation index (M)
Sw itching arrangement for varying phase modulation index (Z)
0.001uF
Fig. 4.2.1 Hardware Interfacing Circuit for the digital signal processor controlled PWM phase modulator for two-phase voltage source inverter (for three-level PWM pattern).
105
Fig. 4.2.2 Photograph of the Real-time Hardware Interfacing Circuit, implemented on the PCB, for the digital signal processor controlled PWM phase modulator for two-phase voltage source inverter (for three-level PWM scheme).
If any one of the switches SW1 to SW4 is pressed then a path is established form +5V DC source to the ground and the current flows through the 1K resistor and the voltage drop across this 1K resistor is +5V. Thus the input port connected to that resistor gets a +5V (i.e. binary 1). According to the value of this switch the corresponding modulation index (either M or Z) is changed. The program uses this changed value of modulation index to calculate the duty cycles of the PWM pattern of its next cycle. Thus on-line variation of the modulation index is possible. If M is changed then width of the pulses are changed in the PWM pattern, therefore the output voltage of the inverter is changed and thereby changing the speed of the motor. But if Z is changed then waveform of phase B shifts with respect to the waveform of phase A, therefore, the speed changes and /or reverses. It depends on the value and sign of the phase modulation index, Z. If no switch is pressed then all these ports get 0V to its input and no change of value of either M or Z is occurred.
B. Two-level PWM Pattern Generation The complete circuit for the generation of two-level PWM pattern is given in Fig. 4.2.3 and its real time implementation in PCB is given in Fig. 4.2.4. The operation of the hardware interfacing circuit is almost same except at the output of the EPROM. The AND gates are now
106 removed and for one phase the complimentary signals are taken from the two successive output lines (pin 11 and 12) of the EPROM. Here also two separate EPROMs generate the required PWM patterns for the two phases and are applied to the same inverter controller circuit. It controls a two phase half bridge inverter that ultimately drives the two phase induction motor.
S1 C LK
11
9 7 6 5 3 2 4 13 12 14 15 1
Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q 10 Q 11 Q 12
R ST
U2 40 40
P A 0 -P A 6
10
20 22 1
V C C ( +5V )
R8
10 9 8 7 6 5 4 3 25 24 21 23 2 26 27
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A1 A1 A1 A1 A1
O0 O1 O2 O3 O4 O5 O6 O7
11 12 13 15 16 17 18 19
5
11 12 13 15 16 17 18 19
5
4
3
U 6B
2 U 6A
40 49
40 49 S4
7
6
14
U 6C
15 U 6F
40 49
40 49
U4 0 1 2 3 4
27 C 256
CE OE VPP
C8
10 k
S3
0.01 uF
1 4
1 5
C E X T
R E X T /C E X T
A B C L R
P B 0 -P B 6
1 2 3
U 5A 74 123
Q
Q
10 9 8 7 6 5 4 3 25 24 21 23 2 26 27
1 3
4
20 22 1
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A1 A1 A1 A1 A1
O0 O1 O2 O3 O4 O5 O6 O7
4
3
U 7B
2 U 7A
40 49
40 49 S2
7
6 U 7C 40 49
14
15 U 7F 40 49
U4 0 1 2 3 4
27 C 256
CE OE VPP
PC 0 V C C ( +5V )
6
5 U 1C SW 1
74 04
R1
PC 1
SW 2 PC 2
SW 3 PC 3
SW 4 PC 4
1k
1
2
3
U 1A
4 U 1B
74 04
R1
R1
R1
R1
1K
1K
1K
1K
74 04 C1
S w i tc h i n g a rr a n g e m e n t fo r v a ry i n g v o lta g e m o d u l a ti o n in d e x (M )
S w i tc h i n g a rr a n g e m e n t fo r v a ry i n g p h a s e m o d u l a ti o n in d e x (Z )
0.00 1uF
Fig. 4.2.3 Hardware Interfacing Circuit for the digital signal processor controlled PWM phase modulator for two-phase voltage source inverter (for two-level PWM scheme).
107
Fig. 4.2.4 Photograph of the Real-time Hardware Interfacing Circuit, implemented on the PCB, for the digital signal processor controlled PWM phase modulator for two-phase voltage source inverter (for two-level PWM scheme).
C. The operation of the inverter controller circuit The complete diagram of the controller circuit for either three or two level PWM scheme is given in Fig. 4.2.5 and its real time implementation in PCB is given in Fig. 4.2.6. As the inverter controller circuit gets the PWM signals from the output of the buffers of the EPROMs it is first inverted and buffered by using a TTL inverting buffer. The 100 resistor limits the current through the LED of the opto-coupler. The opto-isolator makes the ground isolation of the circuit from the DSP kit. The output signals are taken across the resistor at the emitter terminal of the phototransistor inside the opto-coupler. The bias of these phototransistors is applied from three separate DC power supplies that use step down transformers. Thus the grounds of the PWM output signals are isolated from one another. The subsequent sections of this controller circuit uses corresponding DC voltages of the phototransistors for the biasing of that particular section. Therefore, all of the four MOSFETs of the inverter get the same level of voltage at its corresponding gates with respect to its source terminals. The signal obtained from the emitter of the phototransistor is reverted and buffered by using a CMOS inverting buffer. After that a push pull type current amplifier is used to amplify the current. The two series capacitor connected in parallel with the DC supply voltage divides the supply voltage of the inverter equally across them. When a MOSFET is ON, then current drawn
108 from one of the capacitors flows through that MOSFET and one phase of the motor. Thus each phase of the motor gets half of the DC supply voltage Vs. But when that MOSFET becomes OFF, current in that phase of the motor cannot instantaneously becomes zero. So a counter emf is generated for continuation of this current. It then forward biases the diode in the complimentary transistor and sinks current into the other capacitor or DC source until it decays down to zero. The photographs of the complete system and the MDA-DSP kit are presented in Figs. 4.2.7 and 4.2.8 respectively. VCC (+5V) U1A A1 1
2
R1
1 U2
6
100ohm
5
7414
R9 100K
4
V1 12V
U6A
2
3
R13
2
4N25
QN1 BD135
100ohm R5 1K
QP1
4049
U1B A2 3
4
R2
1
1 U3
2
VCC (+5V)
2
BD136
Q1 IRF540_1
1
Q3 IRF540_1
6 R10 100K
4 2
QN4 BD135 V3 12V
U7A 3
R14
2
4N25
100ohm R6 1K
Winding of Phase A
QP4
4049
3
5
3
100ohm 7414
C3 4700uF
BD136
VS 90V
VCC (+5V) U1C B1 5
6
R3
1 U4
Winding of Phase B
6
100ohm
2
3
QN3 BD135
R15
2
4N25
1
100ohm
1
Q2 IRF540_1
C4 4700uF
3
QP3 BD136
4049
3
R7 1K
Q4 IRF540_1
2
R11 U8A 100K
4
2
5
7414
V2 12V
VCC (+5V) U1D B2 9
8
R4
1 U5
100ohm
6 5
7414
R12 100K
4 2
QN2 BD135
U7B 5
4
4N25
R16 100ohm
R8 1K
4049
QP2 BD136
Fig. 4.2.5 Circuit diagram of a two-phase half-bridge inverter and its controller circuit (for both two and three level PWM scheme).
109
Fig. 4.2.6 Photograph of the real-time two-phase half-bridge inverter and its controller circuit implemented on a PCB (for both two and three level PWM schemes).
Fig. 4.2.7 Photograph of the MDA-DSP kit (TMS320C50).
110
Fig. 4.2.8 Photograph of the complete system of digital signal processor controlled PWM phase modulator for two phase induction motor using two level PWM scheme.
4.3
PWM Patterns and Current Waveforms
To analyze the performance of the proposed system, it is tested on a prototype 0.5 hp two phase induction motor whose winding resistance is 80 and inductance is 50 mH. The DC supply voltage of the inverter is 90V. The motor runs at no load condition. A 20 MHz dual channel oscilloscope is used to observe the PWM patterns and the phase current of the motor. The PWM pattern, applied to the gate of the Q1 MOSFET obtained from the output of the CMOS inverting buffer whose input is connected to the output of the EPROM, is observed at the channel one of the oscilloscope. To obtain the waveform of the phase current of the motor, two current transformers with 1/60A ratio is connected with the two phases of the motor. At the primary one turn of the phase wire is given, therefore, at the secondary 60 times greater current will be obtained (since the phase current is very low). The secondary current is passed through a 0.25 , 5W resistor across which the voltage drop is observed at the channel two of the oscilloscope. For various modulation parameters the PWM patterns and phase current waveforms of phase A are taken at the same time from the oscilloscope screen using a 90 mm zoom lens camera.
111 Besides, some photographs are taken for the phase currents of the two phases of the motor simultaneously to show the variation of phase angle between the two phase of the motor and hence the torque and direction of rotation. Finally, a comparison is made between the two level and three level PWM schemes.
Fig. 4.3.1 PWM patterns obtained at the output of the EPROM for Q1 MOSFET and the phase current waveform of phase A for three level PWM scheme with f = 50 Hz, fc = 1400 Hz, M = 1.0, Z = 1.0 and N = 28.
Fig. 4.3.2 PWM patterns obtained at the output of the EPROM for Q1 MOSFET and the phase current waveform of phase A for three level PWM scheme with f = 60 Hz, fc = 1400 Hz, M = 1.0, Z = 1.0 and N = 23.
112
Fig. 4.3.3 PWM patterns obtained at the output of the EPROM for Q1 MOSFET and the phase current waveform of phase A for three level PWM scheme with f = 70 Hz, fc = 1400 Hz, M = 1.0, Z = 1.0 and N = 20.
Fig. 4.3.4 PWM patterns obtained at the output of the EPROM for Q1 MOSFET and the phase current waveform of phase A for three level PWM scheme with f = 50 Hz, fc = 1400 Hz, M = 0.9, Z = 1.0 and N = 28.
113
Fig. 4.3.5 PWM patterns obtained at the output of the EPROM for Q1 MOSFET and the phase current waveform of phase A for three level PWM scheme with f = 50 Hz, fc = 1400 Hz, M = 0.8, Z = 1.0 and N = 28.
Fig. 4.3.6 PWM patterns obtained at the output of the EPROM for Q1 MOSFET and the phase current waveform of phase A for three level PWM scheme with f = 50 Hz, fc = 1600 Hz, M = 1.0, Z = 1.0 and N = 32.
114
Fig. 4.3.7 PWM patterns obtained at the output of the EPROM for Q1 MOSFET and the phase current waveform of phase A for three level PWM scheme with f = 50 Hz, fc = 1600 Hz, M = 0.9, Z = 1.0 and N = 32.
Fig. 4.3.8 PWM patterns obtained at the output of the EPROM for Q1 MOSFET and the phase current waveform of phase A for three level PWM scheme with f = 50 Hz, fc = 1600 Hz, M = 0.8, Z = 1.0 and N = 32.
115
Fig. 4.3.9 PWM patterns obtained at the output of the EPROM for Q1 MOSFET and the phase current waveform of phase A for three level PWM scheme with f = 50 Hz, fc = 1200 Hz, M = 1.0, Z = 1.0 and N = 24.
Fig. 4.3.10 Phase current waveforms for phase A and phase B for three level PWM scheme with f = 50 Hz, fc = 1400 Hz, M = 1.0, Z = 1.0 and N = 28.
116
Fig. 4.3.11 Phase current waveforms for phase A and phase B for three level PWM scheme with f = 50 Hz, fc = 1400 Hz, M = 1.0, Z = 0.5 and N = 28.
Fig. 4.3.12 Phase current waveforms for phase A and phase B for three level PWM scheme with f = 50 Hz, fc = 1400 Hz, M = 1.0, Z = 0.0 and N = 28.
117
Fig. 4.3.13 Phase current waveforms for phase A and phase B for three level PWM scheme with f = 50 Hz, fc = 1400 Hz, M = 1.0, Z = -0.5 and N = 28.
Fig. 4.3.14 Phase current waveforms for phase A and phase B for three level PWM scheme with f = 50 Hz, fc = 1400 Hz, M = 1.0, Z = -1.0 and N = 28.
118
Fig. 4.3.15 PWM patterns obtained at the output of the EPROM for Q1 MOSFET and the phase current waveform of phase A for two level PWM scheme with f = 50 Hz, fc = 1400 Hz, M = 1.0, Z = 1.0 and N = 28.
Fig. 4.3.16 PWM patterns obtained at the output of the EPROM for Q1 MOSFET and the phase current waveform of phase A for two level PWM scheme with f = 60 Hz, fc = 1400 Hz, M = 1.0, Z = 1.0 and N = 23.
119
Fig. 4.3.17 PWM patterns obtained at the output of the EPROM for Q1 MOSFET and the phase current waveform of phase A for two level PWM scheme with f = 70 Hz, fc = 1400 Hz, M = 1.0, Z = 1.0 and N = 20.
Fig. 4.3.18 PWM patterns obtained at the output of the EPROM for Q1 MOSFET and the phase current waveform of phase A for two level PWM scheme with f = 50 Hz, fc = 1400 Hz, M = 0.9, Z = 1.0 and N = 28.
120
Fig. 4.3.19 PWM patterns obtained at the output of the EPROM for Q1 MOSFET and the phase current waveform of phase A for two level PWM scheme with f = 50 Hz, fc = 1400 Hz, M = 0.8, Z = 1.0 and N = 28.
Fig. 4.3.20 PWM patterns obtained at the output of the EPROM for Q1 MOSFET and the phase current waveform of phase A for two level PWM scheme with f = 50 Hz, fc = 1600 Hz, M = 1.0, Z = 1.0 and N = 32.
121
Fig. 4.3.21 PWM patterns obtained at the output of the EPROM for Q1 MOSFET and the phase current waveform of phase A for two level PWM scheme with f = 50 Hz, fc = 1600 Hz, M = 0.9, Z = 1.0 and N = 32.
Fig. 4.3.22 PWM patterns obtained at the output of the EPROM for Q1 MOSFET and the phase current waveform of phase A for two level PWM scheme with f = 50 Hz, fc = 1600 Hz, M = 0.8, Z = 1.0 and N = 32.
122
Fig. 4.3.23 PWM patterns obtained at the output of the EPROM for Q1 MOSFET and the phase current waveform of phase A for two level PWM scheme with f = 50 Hz, fc = 1200 Hz, M = 1.0, Z = 1.0 and N = 24.
Fig. 4.3.24 Phase current waveforms for phase A and phase B for two level PWM scheme with f = 50 Hz, fc = 1400 Hz, M = 1.0, Z = 1.0 and N = 28.
123
Fig. 4.3.25 Phase current waveforms for phase A and phase B for two level PWM scheme with f = 50 Hz, fc = 1400 Hz, M = 1.0, Z = 0.5 and N = 28.
Fig. 4.3.26 Phase current waveforms for phase A and phase B for two level PWM scheme with f = 50 Hz, fc = 1400 Hz, M = 1.0, Z = 0.0 and N = 28.
124
Fig. 4.3.27 Phase current waveforms for phase A and phase B for two level PWM scheme with f = 50 Hz, fc = 1400 Hz, M = 1.0, Z = -0.5 and N = 28.
Fig. 4.3.28 Phase current waveforms for phase A and phase B for two level PWM scheme with f = 50 Hz, fc = 1400 Hz, M = 1.0, Z = -1.0 and N = 28.
125 The PWM patterns for the Q1 MOSFET in phase A and current waveforms for phase A are presented in Figs. 4.3.1-4.3.14 for three level PWM scheme and in Figs. 4.3.15-4.3.28 for two level PWM scheme with the variation of various modulation parameters. Since no negative voltages are generated using the DSP kit so here in each half cycle of the PWM pattern only positive voltages are shown, and in the other half cycle zero voltages are shown. That means at that time the complimentary MOSFET remains ON. By changing the fundamental and carrier frequency the number of pulses in each PWM cycle can be changed. By changing the voltage modulation index the width of each of the pulses in the PWM pattern can be changed. By doing so the range of operation of the motor is found. The operating range for the motor is 0.5 to 1.0 for M, -0.25 to -1.0 and 0.25 to 1.0 for Z, 30 Hz to 100 Hz for fundamental frequency (f) for the case of both two level and three level PWM schemes. In the program fc can be varied from 800 Hz to 1800 Hz. The actual carrier frequency is set by the external resistance and capacitance values of the of the clock circuit. It can be changed on line if a potentiometer or a gang capacitor is used for the external clock generator circuit instead of using fixed resistor or capacitor. The range of the modulation index can be increased if the supply voltage to the inverter is increased more. Besides, it is observed that on line variation of the modulation index and phase modulation index was possible. Hence speed, torque and direction of the motor can be altered. For this variation of the modulation parameters keeping the motor in running condition the performance of the system is not disturbed. The current waveforms for both two and three level PWM schemes are sinusoidal and also the magnitude of the current is same for the same set of modulation parameters. But in three level PWM schemes the harmonic contents are higher and hence distortions are greater for this case. The current waveform would have been more sinusoidal if the inductance of the motor winding is increased. At first, the fundamental frequency is varied and it is observed that the motor draws less current from the dc source at lower frequency. Hence speed is higher. As the modulation index, M is decreased the phase current of the motor is increased as more power is required to drive the motor with same speed since f is unchanged. As fc is increased in the program the motor current is decreased. Because, as the number of pulses increases, the rms voltage increases and hence current decreases to draw same power for the same speed of the motor. The last five figures for both level of PWM schemes are shown for the variation of the phase modulation index (Z) keeping the other parameters unchanged. These clearly show that the smooth variation of the phase angle is possible and phase reversal is possible. Besides, by
126 decreasing the magnitude of Z to zero one can turn off the motor. The motor can change its direction of rotation as well as can come to standstill from the running condition with the variation of Z. When Z is equal to 1 the motor rotates in counterclockwise direction. When Z is equal to -1 the motor rotates in clockwise direction. At Z = 0, the motor is at standstill condition, but still draws current from the DC source as is observed from the figures. This power is lost inside the motor. If the magnitude of Z is decreased then the motor draws more current from the DC source, since now the torque is reduced due to smaller phase angle difference between the two windings of the motor. The motor lowers its speed. It is also observed that for both direction of rotation motor draws same amount of current for the same magnitude of the phase modulation index, Z. That is, torque is uniform in both direction of rotation.
4.4
Summary
In this chapter first operation of the complete circuit and inverter is described with the circuit diagram and the photograph of the actual circuit implemented on a PCB. Then wave shapes for PWM pattern and phase current taken by a camera from the oscilloscope screen are presented for the variation of various modulation parameters. These patterns and waveforms are analyzed and compared with the simulated results produced by MATLAB given in chapter two. Experimental results are in good agreement to that of the simulated results.
127
Chapter 5 Conclusions 5.1
Conclusion
This chapter summarizes the thesis work on digital signal processor controlled PWM phase modulator for two-phase voltage source inverter. At first theoretical model of the proposed scheme is developed. Center justified symmetric regular sampling technique is used to develop the equation of switching instants, number of pulses in one carrier period and phase voltages for the two phase voltage source inverter. Both three level and two level PWM schemes are adopted to implement the proposed scheme. Then torque equation is derived for the two-phase induction motor under balanced and unbalanced condition of operation. Torque-speed characteristics are also plotted from the torque equation under unbalanced condition of operation. After that the scheme is simulated using MATLAB for harmonic spectrum, PWM pattern and current waveform. From the simulated results distortion factor is calculated and plotted on the graph. These plots suggest the suitable range of values of these modulation parameters for proper operation of the inverter. Finally, for the real-time implementation of the proposed scheme PCB is designed and the circuit is constructed on it in the laboratory. Practical implementation and observation of the system has been carried out successfully in the laboratory for various combinations of control parameters. For this system, digital signal processor kit MDA DSP kit TMS 320C50 is used as the main control unit. Coding of the program is developed using the ANSI C compiler supplied by Texas Instrument. To create coding, editing, compiling, loading and running the program a PC is used. After loading the program in the DSP kit from the computer, the program is run and the DSP performs various calculations to produce the required PWM patterns for two phases. The patterns generated for the two phases are taken from the port A and B of 8255A using 30-pin edge connector. This signal is then transmitted to the hardware interfacing circuit that produces required switching pattern for the inverter. This signal is
128 then transmitted to the electronic controller circuit, which drives the power inverter to produce ac voltage for two phases of the motor from the DC supply voltage. The power inverter then drives the motor at no load condition. To evaluate the performance of the practical system, the PWM patterns and phase currents of the motor are observed in the oscilloscope screen for different combinations of the control parameters without loading the motor. Simulated and experimental results are then compared and analyzed in chapter 4. It shows good agreement between them. The two-phase induction motor with identical windings is simpler in construction than the split-phase motor, capacitor-start motor etc. and permits a variable speed to be obtained when supplied from variable voltage variable frequency (VVVF) two phase voltage sources. Also speed reversals are possible when phase angle of one winding is varied from -900 to +900 with respect to the other winding. But two-phase supply having variable voltage, frequency and phase angle options is not readily available. The objective of this thesis was to develop a system for such types of applications. A rotating magnetic field is obtained within the whole range of speed variation, thus ensuring an easy start of the motor. By using this system, wide range of speed variation and speed reversals are possible by changing the voltage, frequency and phase angle. On line change of the parameters are also possible. The supply voltages can be widely varied by changing the modulation index, M. Although the proposed scheme is implemented and tested using both three level and two level PWM schemes, in practical applications the author suggests only two level PWM schemes because of the following advantages: 1. The two-level scheme provides more computation time for the same number of switching intervals per fundamental cycle. 2. The two-level scheme provides a maximum voltage equal to the dc bus voltage during each switching interval. In practice, probably only about 80% of the dc bus voltage is available during each switching interval with the three-level scheme. 3. The two-level scheme can produce positive or negative voltage pulses during each switching interval while the three-level scheme is intended to produce only positive voltage pulses on positive fundamental half cycles and negative voltage pulses on negative half cycles.
129
5.2
Limitations of the Proposed Systems
The main limitation of the system is that the main control unit the DSP kit has no floatingpoint support. So, all calculations need to be done using fixed-point arithmetic, and hence some data are needed to be dropped from the calculations. Of course, DSP kit with floatingpoint support is available but they are more expensive. Besides, the speed of the digital signal processor is 40MHz. So, to perform all instructions of a complete cycle one has to do it within 200s. The high-speed digital signal processor can solve this problem. It will be costlier also.
5.3
Recommendations for Future Works
In this work there is no provision for on-line parameter entry facilities. They can be changed only from one value to next higher or lower values in discrete steps. Besides, fundamental frequency cannot be changed or introduced into the system without stopping the motor. In the future works, provision may be made for on-line parameter entry facilities. Due to versatility of digital circuits, the proposed controller could also be used in other applications such three phase inverters for three phase motor control. For this some modifications in the program is needed. For the controller circuit Programmable Logic Devices (PLDs) may be used. Due to low price and high software and hardware capabilities of currently available digital components, the cost of the entire controller could be very low. In this work there is no option to get feedback into the program. The DSP has no control over the system in case of instability or short circuit. Due to aging effect the motor parameters may vary. Thus the system can be incorporated with a feature that the real-time identification of the motor parameters be used in the controller at every sampling instant, and thus speed control will always be attained with high accuracy. Besides, the proposed system was implemented using a half-bridge inverter with both three and two level PWM schemes, but it can be implemented using a full-bridge inverter also.
130
References [1]
[2] [3]
[4]
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Appendix The developed program “PWM3L2PH.C” for the three level PWM pattern generations using the ANSI C compiler provided by the Texas Instrument is given below: #include #include float pi = 3.141593; unsigned int PWM_A, PWM_B; int f; int fc; float M, Z; int N; int i, j; int flagA, flagB; int PC0, PC1, PC2, PC3, PC4;
float theta, thetaS; float sina[50], sinb[50]; float duty_a[50], duty_b[50]; int Dx, Dy;
/* PWM Pattern for phase A and phase B */ /* f = fundamental or modulating frequency */ /* fc = carrier or sampling frequency */ /* M = Voltage Modulation Index*/ /* Z = Phase Modulation Index */ /* N = Number of samples in a carrier period */
/* PC0-PC4 = Name of the port C PC0 = To check the status of the counter PC1 = To increase the value of M PC2 = To decrease the value of M PC3 = To increase the value of Z PC4 = To decrease the value of Z */ /* theta = Switching instants in radian angle */ /* thetaS = Starting phase angle for phase A & B */ /* Variables to store the sampled values */ /* Variables to store duty cycles of sampled values */ /* Integer values of the calculated duty cycle */
void main() { f = 50; fc = 1400; M = 1.0; Z = 1.0; N = (int) (fc/f); theta = 2*pi/N; thetaS = theta/2; j = 0; PPICW = 0x89; /* Configuring Port A and B as output port and Port C as input port.*/ for(;;) { j += 1;
/* Infinite loop, program never terminates by itself */
139 if (j == 10) { PC1 = PPIC; PC2 = PPIC; PC3 = PPIC; PC4 = PPIC;
/* Scan the 2nd pin of input port C */ /* Scan the 3rd pin of input port C */ /* Scan the 4th pin of input port C */ /* Scan the 5th pin of input port C */
if ((PC1 & 0x02) == 0x02) { if (M < 1.0) M += 0.1; /* Increase the value of M */ } if ((PC2 & 0x04) == 0x04) { if (M > 0.0) M -= 0.1; /* Decrease the value of M */ } if ((PC3 & 0x08) == 0x08) { if (Z < 1.0) Z += 0.1; /* Increase the value of Z */ } if ((PC4 & 0x10) == 0x10) { if (Z > -1.0) Z -= 0.1; /* Decrease the value of Z */ } j = 0; /* Reset the value of j */ } for (i = 1; i 0) flagA = 1; else flagA = 0; Dx = Dx*flagA; if (Dy < 0) flagB = -1; else if (Dy > 0) flagB = 1; else flagB = 0; Dy = Dy*flagB;
140 if (flagA == 1 && flagB == -1) { PWM_A = Dx + 128; PWM_B = Dy; } else if (flagA == 1 && flagB == 1) { PWM_A = Dx + 128; PWM_B = Dy + 128; } else if (flagA == -1 && flagB == 1) { PWM_A = Dx; PWM_B = Dy + 128; } else if (flagA == -1 && flagB == -1) { PWM_A = Dx; PWM_B = Dy; } do { PC0 = PPIC; } while ((PC0 & 0x01) == 0); PPIA = PWM_A; PPIB = PWM_B; } } }
/* Check the status of the pin PC0 */
/* Send PWM patterns to the port A of the 8255A */ /* Send PWM patterns to the port B of the 8255A */
141 The developed program “PWM2L2PH.C” for the two level PWM pattern generations using the ANSI C compiler provided by the Texas Instrument is given below: #include #include float pi = 3.141593; int f; int fc; float M, Z; int N; int i, j; int PC0, PC1, PC2, PC3, PC4;
float theta, thetaS; float sina[50], sinb[50]; float duty_a[50], duty_b[50]; int Dx, Dy;
/* f = fundamental or modulating frequency */ /* fc = carrier or sampling frequency */ /* M = Voltage Modulation Index */ /* Z = Phase Modulation Index */ /* N = Number of samples in a carrier period */ /* PC0-PC4 = Name of the port C PC0 = To check the status of the counter PC1 = To increase the value of M PC2 = To decrease the value of M PC3 = To increase the value of Z PC4 = To decrease the value of Z */ /* theta = Switching instants in radian angle */ /* thetaS = Starting phase angle for phase A & B */ /* Variables to store the sampled values */ /* Variables to store duty cycles of sampled values */ /* Integer values of the calculated duty cycle */
void main() { f = 50; fc = 1400; M = 1.0; Z = 1.0;
N = (int) (fc/f); theta = 2*pi/N; thetaS = theta/2; j = 0; PPICW = 0x89; /* Configuring Port A and B as output port and Port C as input port.*/ for(;;) { j += 1; if (j == 10) { PC1 = PPIC; PC2 = PPIC;
/* Infinite loop, program never terminates by itself */
/* Scan the 2nd pin of input port C */ /* Scan the 3rd pin of input port C */
142 PC3 = PPIC; PC4 = PPIC;
/* Scan the 4th pin of input port C */ /* Scan the 5th pin of input port C */
if ((PC1 & 0x02) == 0x02) { if (M < 1.0) M += 0.1; /* Increase the value of M */ } if ((PC2 & 0x04) == 0x04) { if (M > 0.0) M -= 0.1; /* Decrease the value of M */ } if ((PC3 & 0x08) == 0x08) { if (Z < 1.0) Z += 0.1; /* Increase the value of Z */ } if ((PC4 & 0x10) == 0x10) { if (Z > -1.0) Z -= 0.1; /* Decrease the value of Z */ } j = 0; /* Reset the value of j */ } for (i = 1; i
