Digital Video Broadcast: Systems and Implementations

Chapter 1 Digital Video Broadcast: Systems and Implementations Yue Zhang, Kok-Keong Loo, John Cosmas School of Engineering and Design, Brunel University, UB8 3PH, UK

1.

Development of DVB Infrastructure

Terrestrial broadcasting has brought entertainment and media information to mass audiences around the world for nearly a century. In the last two decades, the demand for consumption of multimedia services anywhere anytime has increased greatly. Because the spectrum resource is limited, a new spectrum efficient broadcasting technology is required to meet this demand. Digital broadcast technologies, such as the European Digital Video Broadcast - Terrestrial (DVB-T), moved terrestrial broadcast into the digital age. While analog broadcast can only deliver one programme per channel, digital broadcast namely DVB-T allows multi-programme broadcasting where 2 to 4 standard definition TV (SDTV) programmes can be transmitted with time division multiplexing in a single 8 MHz channel. The bandwidth of DVB-T (from 12 to 24 Mbit/s) can be allocated to offer different TV qualities, such as enhanced definition television (EDTV, requiring about 10 to 12 Mbit/s per programme) or high definition TV (HDTV, requiring about 24 Mbit/s per programme) [1]. In a nutshell, DVB-T has brought a higher quality service to TV program and it helps by reducing the use of spectrum, thus allowing other promising wireless technologies to diversity its applications. This leads to the development of emergence standard, Digital Video Broadcast - Handheld (DVB-H), that takes DVB-T a step further by making mobile reception of digital broadcasting possible with small, handheld devices.

The governments of different European countries have made their plans for analog to digital TV switchover and fully deploying DVB-T/H services. United Kingdom, in early 2007, switched off analog TV in one Welsh community as an experiment. It is expected that the analog TV is completely phased out by the end of 2012 [2] nationwide. Meanwhile, analog and digital TV continue to co-exist in such a way to enable a soft transition from analog to digital. This period which is known as the simulcast phase will entail increased spectrum needs.

2.

DVB Standard: Physical Layer

The DVB physical layer includes outer coder/decoder, inner coder/decoder, QAM mapping, Frame adaptation and TPS insertion, OFDM and up/down converter as shown in Figure 1 [3][4]. DVB Transmitter MPEG-2 TS Source

Scrambler

Outer Coder

Outer Interleaver

Inner Coder

Inner Interleaver

Up Converter

Guard Interleaval

OFDM

Frame Adaptation

QAM mapping

Down Converter

Guard Interval Remove

Frame Adaptation

QAM Demodulation

DVB Receiver OFDM demodulation

Channel Estimation MPEG-2 TS Sink

Descrambler

Outer Decoder

Outer Deinterleaver

Inner Decoder

Inner Deinterleave

Figure 1: Block diagram of DVB system

The functional blocks are discussed in the following sub-sections. 2.1

Scrambler / Descrambler

The MPEG2 Transport Stream (MPEG2-TS) is a source input to DVB physical layer that is organized in fixed length of 188-byte packet (see Figure 3a). Every first byte of the MPEG2-TS 188-byte packet is a syncword with a known value 47Hex. In order to ensure the energy dispersal of binary data, a scrambler is used to randomize the MPEG2-TS input stream

Deleted: are Deleted: ed Deleted: that

as shown in Figure 2. The scrambler is a 16-bit Pseudo Random Binary Sequence (PRBS) with generator polynomial, 1 + X14 + X15. The PRBS register is loaded with initial sequence "100 1010 1000 0000", and is reinitialized at the start of every group of 8 MPEG2-TS packets (see Figure 3b). The first sync byte in a group of 8 packets is inverted from 47HEX to B8HEX for identification of every randomized group of packets. In other words, the PRBS should have a period of 1503 bytes. The randomization process should stay active even if the modulator input bit-stream is nonexistent or non-compliant with the MPEG2-TS format (1 sync byte + 187 packet bytes). Reverse operation is carried out in descrambler at the receiver in order to obtain the sink MPEG-2 TS.

Deleted: it shall be

Figure 2: Scrambler schematic diagram

2.2

Outer Coder and Outer Interleaver

Reed-Solomon (RS) encoder is used as outer coder to generate 16-byte parity block for each randomized transport packet (188-byte) fed by the scramble. In essence, 51 null bytes are intentionally added to the input randomized transport packet such that a NASA-standard RS(255, 239, t=8) mother code can be used. The null bytes are discarded after the coding procedure leading to a RS codeword of N=204, including the 16-byte parity block appended at the end of each input as shown in Figure 3c. The RS code uses a generator polynomial, g(x)=(x+λ0)(x+ λ1)(x+ λ2)...(x+ λ15), where λ = 02HEX, and a primitive field generator polynomial is p(x) = x8 + x4 + x3 + x2 + 1, that has the capability of correcting up to 8-byte random errors. Following the RS coder, the error protected packets are fed into a 12 byte depth convolutional byte-wise interleaver. The interleaved data structure is composed of interleaved error protected packets and is delimited by the MPEG2-TS sync bytes (inverted or non-inverted) which preserving the periodicity of 204 bytes (see Figure 3d).

Deleted: which is the Deleted: sion of

Deleted: Deleted: in Comment [J1]: The bytes do not add up

a) MPEG-2 Transport MUX packet

8 Transport MUX data PRBS period 1503 bytes

SYNC1

Randomized data 187 bytes

SYNC2-8

Randomized data 187 bytes

b) Randomized MPEG-2 Transport MUX packet

c) Reed-Solomon RS (204, 188, 8) error protected packets

d) Data structure after Outer Interleaver Figure 3: Outer coding process

2.3 Inner coding In DVB system, a mother convolutional code of rate 1/2 with 64 states is used to create a range of punctured convolutional codes. The generator polynomials of the mother convolutional codes are G1=X+X1+X2+X3 for X output stream, and G2=X+X2+X3+X5 for Y output stream. With mother code of rate 1/2, the input bitstream is doubled by the convolutional coder and the output is reduced by using puncturing method to provide an appropriate punctured rate such as 2/3, 3/4, 5/6 and 7/8. For example, to obtain rate 2/3, one of each 4 bits data will be punctured. Similarly, to obtain rate 3/4, two of each 6 bits data will be punctured. At receiver, the punctured

bits are padded with zeroes such that the decoding is carried as if rate 1/2 code. In essence, the punctured bits are lost bits which increases system BER.

Figure 4: Convoluational code generator

2.4 Inner interleaver The inner interleaver is a group of joined blocks of demultiplexer, bitinterleaver and symbol-interleaver as shown in Figure 5. Firstly, the output of convolutional encoder is split into six sub-streams. The splitting scheme is defined as a mapping of the input bits onto the output bits in one of six sub-streams. Each sub-stream is then processed by a separate bitinterleaver. Bit-interleaver maps 128-bit input block onto 128-bit output block. The outputs of the six bit-interleavers are sequentially grouped to form six-bit symbols. These six-bit symbols are again interleaved by symbol-interleaver. In 2K mode, the symbol-interleaver interleaves 12 sets of 126, six-bit symbols, and in 8K mode, it interleaves 48 sets of 126 symbols. Furthermore, the in-depth interleaver used in 4K mode, which interleaves 24 sets of 126 symbols, is used for DVB-H systems. In additional to the 2K and 8K transmission modes provided originally by the DVB-T standard, the 4K mode with its in-depth interleaver brings additional flexibility in network design by trading off mobile reception performance and size of SFN networks. DVB-H is principally a transmission system allowing reception of broadcast information on single antenna hand-held mobile devices. In the DVBT system, the 2K mode is known to provide better mobile reception performance than the 8K mode, due to the larger inter-carrier spacing it implements. However, the associated guard interval duration of the 2K mode OFDM symbols, are very short. This makes the 2K mode only suitable for a small size SFN. However, 4K OFDM symbol has a longer duration and longer guard interval than 2K mode. This makes 4K mode suitable for medium size SFN networks. It can increase the spectral efficiency for SFN

network planning. As for 8K mode, the symbol duration of 4K mode is shorter than in the 8K mode and so the channel estimation can be done more frequently in the 4K mode demodulator. Therefore, it provides a better mobile performance than 8K mode, although not as high as with the 2K transmission mode, it is enough for the use of DVB-H scenarios. In this scenario, 4K mode provides a good tradeoff between the two important aspects of the system: spectral efficiency for the DVB-H network designers and high mobility for the DVB-H consumers.

Deleted: s

bits write

1,1

1,2

1,16

2,1

2,2

2,16

3,1

3,2

3,16

n,1

n,2

n,16

bits read

Figure 5: Inner interleaver

2.5 Frame Adaptation, TPS and QAM Map In an OFDM-based system, a group of complex symbols are modulating with frequency carriers of the equivalent length to create an OFDM symbol. In DVB, transmitted signal is organized in frames; a frame is composed of 68 OFDM symbols, and 4 frames constitute a super-frame. Besides carrying data, OFDM symbol also carries scattered pilots, continual pilots, and TPS (Transmission Parameter Signaling) carriers. For example, in 2K mode, an OFDM frame comprises 1705 carriers accommodating 1512 data carriers, 131 scattered pilots, 45 continual pilots, and 17 TPS carriers. In 8K mode, an OFDM frame has 6817 carriers (6048 data carriers, 177 continual pilots, 524 scattered pilots, 68 TPS carriers). The power of pilot carrier is 16/9 times stronger than data carrier, whereas TPS carrier is transmitted at normal power as a data carrier. While TPS carriers are

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used for signaling various transmission parameters, the pilot signals are used in frame adaptation (see Figure 1) in order to provide synchronization to the DVB frame structure through various methods such as frame synchronization, frequency synchronization, time synchronization and channel estimation. Note that the DVB receiver must be synchronized and equalized such that the received signal can be decoded successfully and to gain access to the information held by the TPS pilots. All data carriers in an OFDM frame are modulated using QPSK, 16-QAM, 64-QAM, nonuniform 16-QAM or non-uniform 64-QAM constellations as shown in Figure 6.

Figure 6 Continual pilots, scattered pilots and TPS carriers in the DVB constellation diagram

2.6 OFDM Structure OFDM is a proven technique for achieving high data rate whilst overcoming multipath fading in wireless communication [5][6][7]. OFDM can be thought of as a hybrid of multi-carrier modulation (MCM) and frequency shift keying (FSK) modulation. Orthogonality amongst the carriers is achieved by separating them by a frequency which is an integer multiple of the inverse of symbol duration of the parallel bit streams thus minimizing intersymbol interference (ISI). Carriers are spread across the complete channel, fully occupying it and hence using the bandwidth very efficiently. The OFDM receiver uses adaptive bit loading techniques based on a dynamic estimate of the channel response, to adapt its processing and compensate for channel propagation characteristics and achieves near ideal ca-

pacity. The most important advantage of OFDM systems over single carrier systems is obtained when there is frequency-selective fading. The signal processing in the receiver is rather simple; multiplying each sub-carrier by a complex transfer factor thereby equalizing the channel response compensates distortion of the signals. It is not feasible for conventional single carrier transmission systems to use this method. However some disadvantages of OFDM systems are that the peak–to-average power ratio (PAPR) of OFDM is higher than for a single carrier system and OFDM is sensitive to a flat fading channel. The OFDM signal consists of N orthogonal sub-carriers modulated by N parallel data streams. Denoting the frequency and complex source symbol of the kth sub-carrier as fk and dk respectively, the baseband representation of an OFDM is:

x(t ) =

1

∑d e N

j 2π f k t

k

,

0 ≤ t ≤ NT (1)

where dk is typical taken from a PSK or QAM symbol constellation, and NT is the duration of the OFDM symbol. The sub-carrier frequencies are equally spaced at f k = k / NT . The OFDM signal in equ(1) can be derived by using a single IFFT operation rather than using a bank of oscillators. Therefore the OFDM symbol can be represented:

1

Deleted: subcarrier

N −1 k =0

x[n] =

Deleted: subcarrier

N −1

∑d W N k

kn N

,

0 ≤ n ≤ N −1

(2)

k =0

where WN = e j 2π / N . 2.7 Differences between DVB-T and DVB-H There are major three differences between DVB-T and DVB-H which are the 4K mode, in-depth interleaver and TPS-bit signaling used in the DVBH. The 4K mode is architecturally compatible with existing DVB-T infrastructure, requiring only minor changes in the modulator. It constitutes a new FFT size added to the native DVB-T 2K and 8K FFT sizes, all other parameters being the same. As the C/N performance with the three channel models (AWGN, Rice and Rayleigh) is FFT size independent, so the 4K size provides the same performance as the other two modes in these

Deleted: subcarrier

channels. The real feature of the 4K mode is the performance enhancement in mobile reception. The current DVB-T standard provides excellent mobile performance with 2K mode, but with 8K mode the performance is unsatisfactory, especially with reasonable receiver complexity. The 4K mode provides roughly 2 times better Doppler performance than 8K mode. Compared to an existing 2K/8K DVB-T receiver, the addition of the 4K mode and of the in-depth symbol interleaver does not require extra memory, significant amounts of logic, or extra power. Secondly, there is an in-depth interleaver in 4K mode DVB-H [4] systems. The longer symbol duration of the 4K mode makes it more resilient to impulsive interference. For a given amount of noise power in a single impulse noise, power is averaged over 4096 sub-carriers by the FFT in the demodulator. Furthermore, TPS-bit signaling provides robust multiplex level signaling capability to the DVB-H transmission system. TPS is known to be a robust signaling channel as a TPS lock in a demodulator can be achieved with a low C/N value. Two formerly unused TPS bits have been allocated for DVB-H signaling. One is a Time-slicing indicator to signal that at least one time-sliced DVB-H service is available in the transmission channel. The other is an MPE-FEC indicator to signal that at least one DVB-H service in the transmission channel is protected by MPE-FEC. The DVB OFDM configuration for 2K, 8K and 4K modes are provided in Table 1 to 3, respectively. TABLE 1 OFDM PARAMETERS FOR THE 2K MODE

Parameter Elementary period T Number of carriers Value of carrier number Kmin Value of carrier number Kmax Duration Tu Carrier spacing 1/Tu Spacing between carriers Kmin and Kmax

2K mode 7/64 us 1705 0 1704 224us 4464Hz 7.61MHz

Allowed guard interval △/Tu Duration of symbol part Tu

1/4

1/8

1/16

1/32

2048×T 224us 512×T 56us 280us

256×T 28us 252us

128×T 14us 238us

64×T 7us 231us

Duration of symbol interval △ Symbol duration

Deleted: AWGN, Rice and Rayleigh

Deleted: subcarrier

Ts=△+Tu

TABLE 2 OFDM PARAMETERS FOR THE 4K MODE


4K mode 7/64 us 3409 0 3408 448us 2232Hz 7.61MHz

Allowed guard interval △/Tu Duration of symbol part Tu

1/4

Duration of symbol interval △ Symbol duration

1/8

4096×T 448us 1024×T 112us 560us

512×T 56us 504us

1/16

1/32

256×T 28us 476us

128×T 14us 462us

Ts=△+Tu

TABLE 3 OFDM PARAMETERS FOR THE 8K MODE


8K mode 7/64 us 6817 0 6816 896us 1116Hz 7.61MHz

Allowed guard interval △/Tu

1/4

1/8

1/16

1/32

Duration of symbol part Tu

8192×T 896us 2048×T 224us 1120us

1024×T 112us 1008us

512×T 56us 952us

256×T 28us 924us

Duration of symbol interval △ Symbol duration Ts=△+Tu

2.8 Compatibility between DVB-H and DVB-T The new DVB-H components are compatible to the existing DVB-T systems [4]. First of all, as for time-slicing and MPE-FEC, they do not raise any incompatibility issues and are fully compatible with the existing DVB physical layer such as DVB-T, S and C. Additionally time-slicing and MPE-FEC in DVB-H modify the MPE protocol in a fully backward compatible way. Allocating bytes of the MAC address fields, located in the MPE section header is fully supported by the DVB-SI standard. Furthermore, DVB-H signaling is fully backward compatible as there are bits reserved for future use and these are ignored by the DVB-T receivers. However, the proposed new 4K mode and in-depth symbol interleaver of DVB-H affects the compatibility with the current DVB-T physical layer specification. In system level, the new 4K mode could be considered just as an interpolation of the existing 2K and 8K mode, requiring only an additional parameter in the DVB-T system and a little control logic in the equipment. For receiver level, it is obvious that current 2K or 8K receivers will be unable to receive 4K signals, but this is not a severe restriction as any new DVB-H network using the 4K mode would be targeted towards new services and new types of hand portable terminals. The only restriction in this case arises when sharing the multiplex between traditional DVB-T and DVB-H services. The standard allows new 4K capable receivers to receive both 2K and 8K transmissions.

3.

Hardware Implementation of DVB Transmitter

The DVB transmitter (or receiver) system is, generally, composed of digital system and analog front-end as shown in Figure 7. The digital system for transmitter mainly consists of baseband signal processing and digital up-conversation. As far as the baseband signal processing is concerned, the DVB bandwidth and the transmission capacity can be tailored by changing only the system clock namely the elementary period, T of 7/64us (see Tables 1 to 3). The system clock is equivalent to 9.14MSPS which also means 9.14M symbols sampled per second. The analog front-end circuit for the transmitter mainly consists of signal amplification, bandwidth filtering and conversion from immediate frequency (IF) to the radio frequency (RF) of interest.

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×

×

Figure 7: Hardware design for DVB Transmitter

3.1

Digital System for DVB Transmitter

It is suggested that Xilinx Virtex-4 XtremeDSP FPGA development board (see Figure 8) is ideal for implementation of the digital part of the DVB transmitter (or receiver).

Figure 8 Xilinx Xtreme DSP FPGA development platform

Virtex-4 incorporates up to 200K logic cells, 500MHz performance and system architecture that is able to deliver twice the density, twice the per-

formance and half the power consumption of previous generation of Xilinx FPGAs. Virtex-4 has 192 DSP slices and new DSP algorithms allow higher levels of DSP integration. Most baseband signal processing is performed in Virtex-4.

Figure 9: The DACs and FPGAs Interfacing for DVB Transmitter

The Virtex-2 performs as a time/clock control for the Virtex-4 FPGA and AD9772A DAC. The DAC offers 14-bit resolution and a maximum conversion rate of 160MSPS. Additional control signals exist between the DAC and the FPGA i.e. “clock feedback” and “LVPECL” enables full control of the system clock and the DAC output sampling. The clock feedback controls the clocking of the main FPGA, in other words, system clock. The LVPECL clock from Virtex-2 controls the clocking of DAC output sampling. Having these features, the functional blocks in Figure 7 can be easily implemented on this FPGA platform. After the forward error correction (FEC) block, the error-controlled data stream is distributed uniformly over the entire channel and sent to the QAM Mapping and Frame adaptation. Through the QAM Mapping, all the payload carriers are then mapped depending on whether hierarchical or non-hierarchical modulation is used. This results in two tables, namely that for the real part Re(f) and that for the imaginary part Im(f). However, they also contain gaps into which the pilots and the TPS earners are then inserted by the frame adaptation block. Therefore, the complete tables,

comprising 2K, 4K or 8K values respectively, are then fed into the heart of the DVB modulator, the IFFT block. Here, the 2K UK mode is considered for the implementation in FPGA. IFFT with 2048 points are used to get the time domain of the transmitter signals. The Pipelined streaming I/O solution is adopted in the FFT and IFFT implementations, as shown in Figure 10.

Figure 10. IFFT implementation structure

The Pipelined streaming I/O pipelines several radix-2 butterfly-processing engines to offer continuous data processing [8]. Each processing engine has its own memory banks to store the input and intermediate data. The core has the ability to simultaneously perform transform calculations on the current frame of data, load input data for the next frame of data, and unload the results of the previous frame of data. This architecture supports unscaled and scaled fixed point arithmetic methods. In the scaled fixedpoint mode, the data is scaled after every pair of radix-2 stages. After IFFT block, the OFDM signal is separated into real and imaginary part in the time domain. The 2048 values respectively are stored in buffers organized along the lines of the pipeline principle. After the IFFT block, the digital fixed-point signals in time domain are alternately written into one buffer whilst the other one is being read out. During read-out, the end of the buffer is read out first as a result of which the guard interval is formed as shown in Figure 11.

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Figure 11. Guard interval insertion structure

The signals then are sent to the interpolation filter to get high sampling rate data. The interpolation filter can be divided into three stages as shown in Figure 12 [9].

×

×

Figure 12. Digital Up-converter

Figure 12 illustrates a block diagram of the DUC (Digital Up-converter) core. The DUC is a digital circuit which implements the conversion of a complex digital baseband signal to a real passband signal. The input complex baseband signal is sampled at a relatively low sampling rate, typically the digital modulation’s symbol rate 9.14MSPS in DVB systems. The baseband signal is filtered and converted to a higher sampling rate before

being modulated onto a direct digital synthesized (DDS) carrier frequency. The DUC performs pulse shaping and modulation of an intermediate carrier frequency appropriate for driving a final analog up-converter. From the beginning of the interpolation filter, the complex input signals are passed through three stages of filtering, each of which performs a sampling rate change and associated low pass interpolation filtering. The three filtering stages are as follows. Firstly, pulse shaping FIR filter P(z) provides a sampling rate increase of 2 and performs transmitter Nyquist pulse shaping. Second of all, compensation FIR filter C(z) provides a sampling rate increase of 2 and is used to compensate for the passband distortion of the third stage cascaded integrator-comb (CIC) filter. The FIR filters, P(z) and C(z), are implemented using efficient Multiplier-Accumulator (MAC) blocks. The multipliers are realized using the embedded multipliers available in the Virtex-4. Finally, the CIC interpolation filter structure implements sampling rate increases from 4 to 1448. The CIC filter design parameters permit the synthesis of a circuit with a fixed sampling rate increase, or one whose sampling rate increase is programmable in real-time. The complex data stream from the filtering stages is up-converted to an IF band by a mixing operation with a local oscillator generated by DDS in digital domain. The I and Q mixer outputs are combined to form the final DUC passband centred at 36MHz. CIC filters are multi-rate filters used for realizing large sample rate changes in digital systems. The filter structure use only addition operators, subtraction operators and registers. The CIC filter supports interpolation factors from 4 to 1448. The CIC filter structure can be presented in Figure 13.

Deleted: result

3 Stages Sample rate Fs

Zero pad

3 Stages Sample rate 4xFs

Figure 13. CIC filter structure block diagram

Figure 13 shows the CIC filter structure for 3 stages and 4 times interpolation. As for the implementation for DVB transmitter, the configuration the interpolation filter is P(z) with one time interpolation rate, C(z) with two times interpolation rate and CIC with five times interpolation rate. Overall, the magnitude response of the interpolation filters is presented in Figure 14.

Magnitude Response Estimate 0 -20

Magnitude (dB)

-40 -60 -80 -100 -120 -140 0

5

10

15

20 25 Frequency (MHz)

30

35

40

45

Figure 14. CIC filter structure block diagram

The magnitude response is centered at 36MHz with passband from 31.2 MHz to 40.8 MHz and stopband from 30 MHz to 42 MHz. The shoulder can be suppressed to 60dB to meet the requirement of DVB spectrum masks.

Figure 15. Spectrum of DDS with Fc=36Mhz, Fs=9.14Mhz and SFDR=80dB

The DDS is realized using the embedded multipliers available in the Virtex-4 FPGAs. The DDS employs an error feed-forward circuit, which produces a high-quality local oscillator with up to 115 dB of spurious free dynamic range (SFDR). The SFDR of the DDS is a selectable parameter with three choices, 115, 80 or 60 dB, to provide the option for reduced utilization of FPGA resources. The implementation requires a single block memory and multipliers. The phase accumulator is fixed at 32 bits. Figure 15 provides the spectrum plot of the DDS with Fs 91.4MHz, SFDR 80dB and center 36MHz. 3.2

Analog Front-End Circuit for DVB Transmitter

As shown in Figure 7, the analog front-end circuit includes IF Surface acoustic wave (SAW) filter, RF mixer, local oscillator, high power amplifier and channel filter. The IF SAW filter circuit is to remove unwanted mixer products from the IF signals constructed by the DUC (see Figure 12). The SAW filter can be easily obtained off the shelf with a range of supported frequencies. However, there is a significant power loss in the SAW filter; hence there is a need to employ an amplifier circuit after the filter stage. Figure 16 shows a simple interfacing of SAW filter to a ClassA amplifier circuit.

Figure 16: SAW filter

The RF mixer (see Figure 7) is to get RF band signal from IF band signal according to local oscillator. The high power amplifier is the UHF band low noise amplifier. The amplifier should be low noise with max 2dB noise figure and at least have moderate gain over 20dB. It also should be sufficiently linear to cope with full range of possible input signals. The selected component is RF Low Noise Amplifier: ZRL-1150LN+ (NF = 0.7 db typical, BW: 650 MHz- 1.4GHz, Gain at 730 MHz = 32db).

Deleted: y

The channel filter should be required to remove out of band power, which could saturate subsequent amplifier. It probably is a cavity or helical filter. However, this kind of UHF filter has some loss, makes RX noise figure worse. The filter should be low loss (a few dB max) and have a good rejection at frequencies where significant out of band power expected. The selected UHF filter in the design is 730MHz Band pass filter: VBFZ-780+ (2.5 dB points 710 MHz – 850 MHz, loss at 726MHz–734MHz ~1.8db).

4.

Hardware Implementation for DVB Receiver

Figure 17 illustrates the hardware system diagram for DVB receiver. It includes analog front-end and digital system implementation. Because the DVB-H standard has been recently developed to provide video broadcasting services for hand-held devices, the power consumption of a DVB-H baseband receiver must be strictly controlled in order to achieve long battery life. In the analog front-end for the receiver, it consists of several low power channel filters, amplifier, attenuators and mixer. In the digital system for receiver, it comprised of an OFDM demodulator and FEC blocks for complete symbol, carrier and timing recovery, channel equalization and data demodulation and correction.

×

×

Figure 17: Hardware design for DVB Receiver

Deleted: ,

4.1 Analog Front-End Circuit for DVB Receiver In Figure 17, UHF channel filter is required to remove out of band power (e.g. mobile phone) which could saturate the subsequent amplifier. The characteristics of a suitable UHF filter should be low loss (a few dB max), good rejection at frequencies where significant out of band power is expected. The selected UHF filter in the design is 730MHz Band pass filter: VBFZ-780+ (2.5 dB points 710 MHz – 850 MHz, loss at 726MHz– 734MHz ~1.8dB). The Low Noise Amplifier for UHF band should be low noise with max 2dB noise figure and at least moderate gain over 20dB. It also should be sufficiently linear to cope with full range of possible input signals. The selected component is RF Low Noise Amplifier: ZRL-1150LN+ (NF = 0.7 dB typical, BW: 650 MHz- 1.4GHz, Gain at 730 MHz = 32db). The UHF channel filter 2 should at least be able to remove power at image frequency with very low bandwidth. The variable attenuator is required in order to allow the analog front-end to work in dynamic range of RF frequency i.e. UHF and IF band. The selected component is ZX76-31R5-PN-S+ (0 – 2400MHz; 0.5dB steps). The Amplifier 2 is used to obtain a moderate gain. In normal operation, output power level should not overload the Mixer. The selected component is an RF Low Noise Amplifier: ZX60-6013E (NF = 3.3 dB typical, BW 20 MHz- 6GHz, Gain at 730 MHz = 16db). The Mixer is required to extract IF from the UHF band signal by setting the appropriate local oscillator. SAW filter is required to remove unwanted mixer products from the received IF signals. Amplifier 3 is the IF Low Noise Amplifier. It is used to obtain more gain to meet the signal level requirement of ADC. The selected component is ZX60-6013E (NF = 3.3 dB typical, wide bandwidth start 20 MHz- 6GHz, Gain at 30 MHz = 16dB). After the analog front-end, the DVB signal is converted down to a lower IF at 36MHz. This is followed by ADC sampling at 91.4 MHz. Following the ADC, the data stream should be now available at data rate of 91.4 MSPS.

Deleted: For

4.2 Digital Circuits System Design for DVB Receiver The digital system design can be divided into six stages including DDC (digital down-converter), symbol, carrier and timing recovery, OFDM demodulation, channel equalization, QAM demodulation and FEC for standard 4.98Mb/s to 31.67Mb/s data rates. The OFDM frame structure with a standard operational baseband frequency of 9.14MHz is used as an important parameter to synchronize the symbol timing and carrier recovery. 4.2.1 Digital Down Converter DDC is composed of DDS and several decimation filters as shown in Figure 18. It is the reverse process of DUC (see Figure 12). FsR

Input Sample Rate Fs

× DDS ~

×

P-Stage CIC downsample by 4:16383 (R)

FsRD1

CIC Coarse Gain Control 1:128

FsRD1D2

Polyphase Decimator by 2:8 (D1)

Polyphase Decimator by 2:8 (D2)

CFIR G(z)

PFIR H(z)

Optional component

Figure 18. Digital down converter design

The desired channel is translated to baseband using DDS comprising the two multipliers. DDS is the same component as in the DVB transmitter digital system design. The sample rate of the signal is then adjusted to match the DVB bandwidth. This is performed using a multi-stage multirate filter consisting of the CIC filter and the two polyphase decimators G(z) and H(z). In order to provide maximum flexibility in the datapath, each of the filters may be optionally inserted or excluded from the signal processing chain. Depending on a combination of master clock frequency, signal sample rate and decimation rates R, D1 and D2, the multipliers in the mixer, various components in the CIC filter and the CFIR and PFIR may be time division multiplexed to service both the inphase (I) and quadarature (Q) signals. Furthermore, a course gain adjustment may be applied at the output of the CIC filter to compensate for the bandwidth reduction performed by the CIC decimator. The signal gain can be boosted by 42 dB. If the signal power across the input bandwidth is relatively flat, as is the case in most frequency division multiplexed (FDM) systems, then one would want to

boost the signal power out of the CIC filter by a factor of the decimation rate of the CIC filter [10].

R , where R is

4.2.2 Symbol Carrier and Time Recovery Design After getting the DVB baseband signal from DDC, the next important stage is to get symbol synchronization. There are two stages of symbol synchronization in the DVB receiver design. Firstly, the robust synchronization is searched by using guard interval correlation structure. After that fine symbol synchronization is performed making use of the scattered pilots. As for the coarse symbol synchronization, autocorrelation based on guard interval is used to derive synchronization information [11]. Using autocorrelation, symbols are detected which exist in the signal several times and in the same way. For example, the received time domain samples are denoted by r (k ) . The estimation of the starting position of the symbol, kest can be found in equ(3) as follows: L −1

kest = arg max | ∑ r (k − i )r ∗ (k − i − N )) | k

i =0

(3)

where N is the number of the carriers and L is the size of guard interval in samples.

Figure 19. Coarse symbol synchronization design

The system diagram of coarse symbol synchronization is illustrated in Figure 19. To obtain the best performance, the length of the moving sum has to be same as the length of the guard interval, which is typically the same

as the lengths of the correlating parts. The Max block will detect maximum correlation value position inside a certain window, whose length is typically N+L samples. In an ideal case the maximum correlation values lies at N+L samples apart from each other. The coarse synchronization result of DVB-T 2K mode is shown in Figure 21. 1 0.9 0.8

Correlation Value

0.7 0.6 0.5 0.4 0.3 0.2 0.1

0

2000

4000

6000 8000 10000 DVB-T/H sample index

12000

14000

Figure 20. Result of coarse symbol synchronization for DVB-T samples

From Figure 20, six DVB-T symbols are detected by the coarse symbol synchronization. As for the fine symbol synchronization in DVB system the strategy is to use scattered pilots, which are also used for channel estimation and equalization. By collecting scattered pilots, the channel can be estimated in the frequency domain after post-FFT operation. After IFFT, the CIR (Channel Impulse Response) can be estimated according to the scattered pilots. The received demodulated signal with incorrect FFTwindow position can be described as in equ(4): ~

X ( n) =

1 N

N −1

∑ x(n)e n =0

j 2π k

ε N

e

− j 2π k

n N

(4) j 2π k

ε

where ε is the offset of the fine FFT-window in samples. Because e N is constant for each k, this can be seen as a time shift of the impulse response. It is assumed that the offset is in the direction that causes no Inter Symbol Interference (ISI) [12]. The optimal FFT-window position can be

Deleted: at

found by indicating the direction and the amount of the CIR movement from the ideal place, which is known for the first tap of CIR. The place of the first tap of CIR can be detected by using a threshold and detecting the parts where CIR values are over this threshold. The hardware design is shown in Figure 21. Channel equalization

FFT Scatted pilot Coarse Sync IFFT

CIR pos Fine Sync

Figure 21. Fine symbol synchronization design

4.2.3 Auto Frequency Control Design Besides the symbol synchronization, the frequency synchronization is also necessary for the DVB receiver implementation. If the receiver frequency differs from the transmitted frequency, all the constellation diagrams will rotate more or less quickly clockwise or anticlockwise. The system diagram is illustrated in Figure 22.

Figure 22. Auto frequency control design

It is necessary to measure the position of the continuous pilots in the constellation diagram. The phase difference is a directly controlled variable for the AFC and DDS. The DDS output frequency is changed until the phase difference becomes zero. The continuous pilots are located on the real axis, i.e. I (inphase) axis, at either 0° or 180° degrees, and have a defined amplitude. The continuous pilots are boosted by 3 dB compared with the average signal power and used for locking the receive frequency to the transmit frequency.

Deleted: Deleted: s

4.2.4 Channel Estimation Design In DVB receivers, channel estimation is usually carried out in frequency domain using known symbols, referred to the pilots as shown in Figure 23 [11].

Figure 23. Pilot arrangement in DVB systems

After the synchronization process, the relationship between received signals Y (n) , transmitted signals X (n) and the channel transfer function H (n) can be formulated as: Y (n) = H (n) ⋅ X (n) + W (n)

(5)

where W ( n) is the AWGN for the k-th sub-carrier after FFT. The received pilot signals are extracted from Y (n) . For the pilot sub-carriers, the trans-

Deleted: subcarrier Deleted: subcarrier

mitted inform X ( n p ) is known to the receiver. Therefore, the channel coefficients at the pilot frequencies can be estimated simply using: ~

H (n p ) =

Y (n p ) X (n p )

+ W ' (n p )

(6)

where W ' (n p ) is the noise effect existing at the estimated channel coefficients and n p is the sub-carrier index corresponding to pilot locations. Channel estimation scheme in equ(6) is based on the least-squares (LS) algorithm. In order to estimate the channel coefficients at data sub-carriers, the channel coefficients obtained at pilot frequencies are used for interpo-

Deleted: subcarrier

Deleted: subcarrier

~

lation. After the interpolation, all channel coefficients H (n) can be obtained. The pilot signals are first extracted from the received signals after FFT, and the reference channel coefficients for the interpolation are estimated in frequency domain by comparing the pilot signals before and after transmission. Then, the channel responses of the sub-carriers carrying data are estimated by interpolating neighboring pilot channel coefficients. In order to estimate the channel coefficients at data sub-carriers, the piecewise-linear interpolation method is applied. In the linear interpolation, two consecutive pilot carriers are used to determine the channel response for data sub-carriers. Assuming that the channel coefficient between H (n p ) and H ( n p +1 ) is estimated, then the channel response is obtained by: ~ ~

H (n) = (

~

H (n p +1 ) − H (n p ) n p +1 − n p

~

)(n − n p ) + H (n p )

(7)

However, the LS estimator is very sensitive to noise because it does not consider noise effects in obtaining its solution. To compensate for the weakness of the LS estimator, auto-regressive averaging method based on pilot-block is illustrated in Figure 24.

Deleted: subcarrier Deleted: subcarrier

Deleted: subcarrier

Figure 24. Channel Estimation Average

Since there is noise at the outputs of the FFT and IFFT circuits in the FPGA, it is necessary to take averages for the channel estimation. A simple first order IIR (Infinite Impulse Response) filter is used for averaging the channel estimation in which the function can be expressed as: ~

~

E ( n) = (1 − ς ) ⋅ ( E ( n)) + ς ⋅ ( E ( n − 1))

(8)

~

where E is the averaged channel estimation coefficient and E is the new coming channel estimation coefficient, and ς is the averaging factor which is just less than 1. 4.3 Forward Error Coding Implementation The FEC implementation in the receiver includes symbol/bit deinterleaver, Viterbi decoder, convolutional deinterleaver and Reed Solomon decoder as shown in Figure 25. These functions are available in the library of Xilinx ISE FPGA software tool. Hence, the implementation is rather straightforward.

Deleted: in

Figure 25. FEC system diagram

4.3.1 Viterbi Decoder The demapped data pass from the demapper into the symbol and bit deinterleaver where they are resorted and fed into the Viterbi decoder. The Viterbi decoder decodes the convolutional coded bitstream by finding maximum likelihood path through trellis for convolutional code [13]. The basic decoder consists of three main blocks as shown in Figure 26.

Figure 26. Viterbi decoder block diagram

The first block is the branch-metric-unit (BMU). The incoming data can be hard coded with bit width 1 or soft coded with a configurable bit width which can be set to any value from 3 to 8. Hard coded data is decoded using the Hamming method, whereas the soft data is decoded using an Euclidean metric. In hard decoding, the demodulator makes a firm (or hard decision) on whether a one or zero is transmitted and provides no other information to the decoder on how reliable is the decision. In soft decoding, the demodulator provides the decoder with some side information together with the decision. The extra information provides the decoder with a measure of confidence for the decision. Soft coded data gives a significantly better BER performance compared with hard coded data. Soft decision offers approximately a 3 dB increase in coding gain over hard decision decoding. The second block in the decoder is the add-compare-select-unit (ACS). This block selects the optimal path to each state in the Viterbi trellis. The ACS block uses the convolutional codes to extract the correct cost from the BMU for each branch in the trellis. The BER performance of the Viterbi algorithm varies with different convolutional code sets. The ACS module decodes for each state in the trellis. Thus, for a constraint length 7 decoder which has 64 states, there are 64 sub-blocks in the ACS block. If the hardware is implemented in serial mode, the amount of silicon required for each sub-blocks is only 2.5 slices.

Deleted: is

The final block in the decoder is the traceback block (TB). The actual decoding of symbols in order to obtain the original data sent is accomplished by tracing the maximum likelihood path through the trellis in a backward manner. Up to certain limit, a longer sequence of tracing through the trellis will result in a more accurate path. After a number of symbols equal to at least six times the constraint length, the decoded data is output. The traceback length is the number of trellis states processed before the decoder makes a decision on a bit. For the reduced latency option, the length of the traceback can be set to a multiple of 6 between 12 and 126. A best state option is to select the starting location for the traceback from the state with minimal cost. Figure 27 illustrates Xilinx Viterbi decoder IP core. It provides two implementation methods which may vary the decoding operation, i) a parallel implementation which gives fast data throughput at the expense of silicon area, and ii) a serial implementation which occupies a small area but requires a fixed number of clock cycles per decoded result.

Figure 27 Schematic symbol for Viterbi decoder in FPGA

Deleted: s

4.3.2 Convolutional De-interleaver Design After the Viterbi decoder, the output data is sent to the convolutional deinterleaver. Figure 28 illustrates the operation of the Xilinx convolutional interleaver/de-interleaver IP core. The core operates as a series of delay line shift registers given the DIN input and DOUT output symbols. Both commutator arms start at branch 0 and advance to the next branch after the next rising clock edge. After the last branch has been reached, the commutator arms both rotate back to branch 0 and the process is repeated. Although branch 0 appears to be a zero-delay connection, there still is a delay of the number of clock cycles between DIN and DOUT because of the fundamental latency of the FPGA core. Furthermore, the only difference between an interleaver and a deinterleaver is that branch 0 is the longest in the deinterleaver and the branch length is decremented by L rather than incremented and Branch (B-1) has length 0.

Figure 28. Convolutional interleaver/de-interleaver

4.3.3 Reed-Solomon Decoder Design Thereafter the convolutional deinterleaver, the output data is sent to ReedSolomon decoder. Figure 29 illustrates the schematic symbol of ReedSolomon decoder obtained from the Xilinx IP core library. The ReedSolomon decoder samples the n symbols on the DATA_IN port and attempts to correct errors. The corrected symbols are output on the DATA_OUT port after a fixed latency. The maximum number of symbol errors in a block is guaranteed to be corrected by the Reed-Solomon algorithm is t=(n-k)/2. The decoder can generally detect and indicate a failure to decode if the received block of symbols contains more than t errors.

Figure 29 Schematic symbol for RS decoder in FPGA

5 Summary This chapter discussed the fundamental functions of DVB physical layer which includes outer coder/decoder, inner coder/decoder, QAM mapping, Frame adaptation, TPS insertion and OFDM structure. The hardware implementation of DVB transmitter/receiver that includes the digital system for transmit/receive baseband signal processing and the analog front-end for RF-to-baseband signal conversion or vice-versa, were then presented. This chapter covered a detailed discussion on DUC/DDC, carrier and timing recovery channel estimation and FEC, which are the functions implemented in the digital system. The analog front-end circuit design which includes SAW filter, mixer, low noise amplifier and UHF/VHF channel filter were discussed. As a whole, the chapter intended to provide a good overall picture of both how the DVB system operates and how it can be implemented together with some design references which have not been previously covered by the existing literature.

Reference [1] Terrestrial digital television planning and implementation considerations, BNP005, third issue, summer 2001 [2] Rast, R.M.; The dawn of digital TV, IEEE Spectrum, Volume 42, Issue 10, Oct. 2005 Page(s): 26 – 31 [3] European Telecommunications Standard Institute ETSI.York: Digital Video Broadcasting (DVB); Framing structure, channel coding and modulation for digital terrestrial television. July 1999. EN 300 744 V1.2.1.

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[4] European Telecommunications Standard Institute ETSI.York: Digital Video Broadcasting (DVB); DVB-H Implementation Guidelines Feb 2005. TR 102 377 V1.1.1 [5] Yue Zhang; Cosmas, J.; YongHua Song; Bard, M.; “Future transmitter/receiver diversity schemes in broadcast wireless networks” IEEE Commun. Mag., Oct. 2006, Vol 44, No 10 pp 120-127. [6] Yue Zhang, J Cosmas, M. Bard, Y.H Song, “Obtain diversity gain for DVBH by using transmitter/receiver cyclic delay diversity,” IEEE trans. Broadcasting, Vol 52, Issue 4, pp 464-474, Dec. 2006., [7] Yue Zhang, J Cosmas, K.K Loo, M.Bard, R.D Bari, “Analysis of cyclic delay diversity on DVB-H systems over spatially correlated channel,” IEEE trans. Broadcasting, Vol 53, Issue 1, part2, pp 247-255, March. 2007., [8] J.G. Proakis and D.G. Manolakis, Digital Signal Processing Principles, Algorithms and Applications, Second Edition, Maxwell Macmillan International, New York, 1992. [9] E.B. Hogenauer, “An Economical Class of Digital Filters for Decimation and Interpolation”, IEEE ,Trans Acoust, Speech Signal Processing, Vol.29, No.2 pp. 155-162, April 1981 [10] Abu-Ai-Saud,W.A , Stuber, G.L; “Modified CIC filter for sample rate conversion in software radio systems”, IEEE, Signal Processing Letters, Vol 10, No.5, pp152-154, May 2003 [11] Michael Speth, Stefan A.F, G. Fock, H.Meyr; “Optimum receiver design for wireless broadband systems using OFDM-part II, A case study”, IEEE trans. Commum, Vol 49, No.4, pp.571-578, April 2001 [12] Beek, J.J., Sandell, M., and Borjession, P.O ; “ ML estimation of time and frequency offset in OFDM systems”, IEEE Trans. Signal Process, Vol 45, No.7, pp 1800-1805, 1997 [13] A.J. Viterbi; “Error bounds for convolutional codes and an asymptotically optimum decoding algorithm”, IEEE Trans. Information Theory, Vol IT-13, pp260-269, April, 1967